KR960008521B1 - Semiconductor device isolation method - Google Patents
Semiconductor device isolation method Download PDFInfo
- Publication number
- KR960008521B1 KR960008521B1 KR93014365A KR930014365A KR960008521B1 KR 960008521 B1 KR960008521 B1 KR 960008521B1 KR 93014365 A KR93014365 A KR 93014365A KR 930014365 A KR930014365 A KR 930014365A KR 960008521 B1 KR960008521 B1 KR 960008521B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating layers
- forming
- trench
- etching
- region
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
depositing an insulating layers (20) on the silicon substrate (1) and patterning a cell by photoresist; etching the insulating layers (20) gradiently using the pattern of the cell; forming a trench using the pattern formed by etching the insulating layers (20); increasing the size of the trench by growing up an oxide layer inside the trench and removing that oxide layer; forming a polysilicon layer (9) after forming an insulating layer (8) inside the trench; etching and planarization of the polysilicon (9) into the level of the insulating layers (20) and coating the cell region by photoresisit and patterning a circuit region; forming a field oxide (5) after etching the insulating layers (20) of the circuit region using mask; forming a component region (A) and an isolation region (B) after removing the rest of the insulating layers (20); planarization of the field oxide layer (5).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93014365A KR960008521B1 (en) | 1993-07-27 | 1993-07-27 | Semiconductor device isolation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93014365A KR960008521B1 (en) | 1993-07-27 | 1993-07-27 | Semiconductor device isolation method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950004489A KR950004489A (en) | 1995-02-18 |
KR960008521B1 true KR960008521B1 (en) | 1996-06-26 |
Family
ID=19360190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR93014365A KR960008521B1 (en) | 1993-07-27 | 1993-07-27 | Semiconductor device isolation method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960008521B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10173052A (en) * | 1996-12-13 | 1998-06-26 | Fujitsu Ltd | Semiconductor device and its manufacture |
-
1993
- 1993-07-27 KR KR93014365A patent/KR960008521B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950004489A (en) | 1995-02-18 |
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G160 | Decision to publish patent application | ||
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