KR100253268B1 - Semiconductor element isolation method - Google Patents

Semiconductor element isolation method Download PDF

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KR100253268B1
KR100253268B1 KR1019930003568A KR930003568A KR100253268B1 KR 100253268 B1 KR100253268 B1 KR 100253268B1 KR 1019930003568 A KR1019930003568 A KR 1019930003568A KR 930003568 A KR930003568 A KR 930003568A KR 100253268 B1 KR100253268 B1 KR 100253268B1
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oxide film
etched
layer
oxide layer
silicon substrate
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KR1019930003568A
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Korean (ko)
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KR940022787A (en
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박유배
송인정
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Abstract

PURPOSE: An isolation method for a semiconductor device is provided to reduce a junction parasitic capacitance and an isolation width. CONSTITUTION: In the method, the first oxide layer(2) and a nitride layer(3) are deposited in sequence on a silicon substrate(1), and then a hemispherical-grained polysilicon layer is formed thereon. Next, the second oxide layer is formed over the polysilicon layer, and then a portion of the second oxide layer is dry-etched to remain between hemispherical-grained surfaces of the polysilicon layer. Next, the resultantly exposed polysilicon layer is etched through the remaining second oxide layer, and subsequently the nitride layer(3) and the first oxide layer(2) are etched with the second oxide layer being wholly removed. Thereafter, resultantly exposed portions of the silicon substrate(1) are etched with the polysilicon layer being wholly removed. After a boron ion is then implanted, the etched silicon substrate(1) is oxidized to form a field oxide layer(12). Next, the first oxide layer(2) and the nitride layer(3) are removed.

Description

반도체 소자 절연방법Semiconductor Device Insulation Method

제1도의 (a) 내지 (h)는 종래 반도체 소자 절연방법 공정 순서도.Figure 1 (a) to (h) is a process flowchart of a conventional semiconductor device insulation method.

제2도의 (a) 내지 (g)는 본 발명 반도체 소자 절연방법 공정 순서도.2A to 2G are process flowcharts of a semiconductor device insulation method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 제1산화막1: silicon substrate 2: first oxide film

3 : 제1질화막 4 : 제2산화막3: first nitride film 4: second oxide film

5 : 포토레지스트 6,10,12 : 필드산화막5: photoresist 6,10,12: field oxide film

7 : 열산화막 8 : 제2질화막7: thermal oxide film 8: second nitride film

9 : 사이드웰 11 : HSG 폴리실리콘9: sidewell 11: HSG polysilicon

본 발명은 반도체 소자의 절연방법에 관한 것으로, 특히 단일 트랜지스터간의 절연에 있어서, 필드산화(Field Oxidation)시의 버드빅(Bird's Beak) 및 평탄화(planarixation)을 해결하도록 한 반도체 소자 절연방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of insulating semiconductor devices, and more particularly, to a method of insulating semiconductor devices in order to solve bird's beak and planarixation during field oxidation in insulation between single transistors. .

제1도의 (a) 내지 (h)는 종래 반도체 소자 절연방법 공정 순서도로서, 제1도의 (a)에 도시된 바와같이 실리콘기판(1)위에 제1 산화막(2), 제1질화막(3), 제2산화막(4)을 연속 증착한다.(A) to (h) of FIG. 1 are a flow chart of a conventional semiconductor device insulation method, and as shown in FIG. 1 (a), the first oxide film 2 and the first nitride film 3 on the silicon substrate 1 are shown. The second oxide film 4 is continuously deposited.

이후, 제1도의 (b)에 도시된 바와같이 상기 제2산화막(4)위에 포토레지스트(5)를 증착한후 사진식각공정(photolithography)으로 상기 제2산화막(4)을 에칭한 다음 남아있는 포토레지스트(5)를 제거한다.Thereafter, as shown in FIG. 1B, the photoresist 5 is deposited on the second oxide film 4, and then the second oxide film 4 is etched by photolithography. The photoresist 5 is removed.

상기와 같은 방법으로 상기 제1질화막(3) 제1 산화막(2)을 에칭하면 제1도의 (c)와 같은 패턴이 형성된다.When the first nitride film 3 and the first oxide film 2 are etched in the above manner, a pattern as shown in FIG. 1C is formed.

이후, 제1도의 (d)에 도시된 바와같이 로커스(LOCOS)를 이용하여 상기 실리콘기판(1)상에 필드산화막(6)을 형성한후 제1도의 (e)와 같이 상기 필드산화막(6)을 제거하는데 이때 상기 제2산화막(4)도 제거된다. 이후 제1질화막(3) 위에 열산화막(7)과 제2질화막(8)을 연속 증착한후 절연을 확실히 하기위해 이온주입법으로 보로(B)을 주입하여 사이드웰(9)를 형성한다음 상기 열산화막(Thermal Oxide Film)(7)과 제2질화막(8)을 선택적으로 에칭하면 제1도의 (f)와같은 패턴이 형성된다.Thereafter, as shown in (d) of FIG. 1, a field oxide film 6 is formed on the silicon substrate 1 using a LOCOS, and then the field oxide film 6 is formed as shown in (e) of FIG. ), And the second oxide film 4 is also removed. Thereafter, the thermal oxide film 7 and the second nitride film 8 are continuously deposited on the first nitride film 3, and the side well 9 is formed by implanting the boro B by ion implantation to ensure insulation. When the thermal oxide film 7 and the second nitride film 8 are selectively etched, a pattern as shown in FIG. 1 (f) is formed.

이후 제1도의 (g)와같이 재차 필드산화막(10)을 형성한후 실리콘기판(1)상의 제1산화막(2), 제1질화막(3), 열산화막(7), 제2질화막(8)을 제거하면, 제1도의 (h)와 같이 완성된 반도체소자 절연구조가 형성되어진다.After the formation of the field oxide film 10 again as shown in FIG. 1G, the first oxide film 2, the first nitride film 3, the thermal oxide film 7, and the second nitride film 8 on the silicon substrate 1 are formed. ), The completed semiconductor element insulating structure is formed as shown in FIG.

그러나, 상기에서 설명한 종래 반도체소자 절연방법은 버드빅(Bird's Beak)확산방지를 위해 2번의 질화막증착 및 에칭을 하기 때문에 실리콘의 결정격자 평면이 급격히 변화되고, 불순물인 보론(B)이 산화막내로 확산되므로 불순물의 양을 많이 주입해야 한다.However, in the above-described conventional semiconductor device insulation method, since the nitride film is deposited and etched twice to prevent the diffusion of Bird's Beak, the crystal lattice plane of silicon is changed drastically, and the impurities boron (B) diffuse into the oxide film. Therefore, a large amount of impurities should be injected.

따라서 접합기생 캐패시턴스(junction parastic capacitance)가 커지며, 절연폭을 1㎛이내로 줄이기 힘든 문제점과 필드산화를 2회에 걸쳐 수행하므로 번거로운 문제점이 있었다.Therefore, the junction parastic capacitance is increased, and it is difficult to reduce the insulation width to within 1 μm, and there is a troublesome problem because the field oxidation is performed twice.

본 발명은 이러한 문제점을 해결하기 위하여 확실한 매몰산화가 가능하고, HSG(Hemispherical Grained) 폴리실리콘을 마스크로 이용하여 절연하는 반도체소자 절연방법을 창안한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In order to solve this problem, the present invention has been made a semiconductor device insulation method that can be surely buried oxidation, and insulated using HSG (Hemispherical Grained) polysilicon as a mask, it will be described in detail with reference to the accompanying drawings Same as

제2도의 (a) 내지 (g)는 본 발명 반도체 소자 절연방법 공정 순서도로서, 제2도의 (a)에 도시한 바와같이 실리콘기판(1)상에 제1산화막(2), 제1질화막(3)을 연속증착한후 상기 제1질화막(3)위에 반구형의 오돌오돌한 폴리실리콘(Hemispherical Grained Poly-si : 이하 HSH 폴리실리콘이라 칭함)(11)을 증착한 다음 그 위에 화학기상증착법(CVD)으로 제2산화막(4)을 증착한다.2A to 2G are process flowcharts of the semiconductor device insulation method according to the present invention. As shown in FIG. 2A, the first oxide film 2 and the first nitride film (1) on the silicon substrate 1 are shown in FIG. After continuous deposition of 3), a hemispherical grained polysilicon (hereinafter referred to as HSH polysilicon) 11 is deposited on the first nitride film 3, followed by chemical vapor deposition (CVD). A second oxide film 4 is deposited.

이후, 제2도의 (b)에 도시한 바와같이 상기 제2산화막(4)위에 포토레지스트(5)를 도포한후 사진식각공정(photolithography)으로 상기 제2산화막(4)을 건식식각한다.Thereafter, as shown in FIG. 2B, the photoresist 5 is coated on the second oxide film 4, and then the second oxide film 4 is dry-etched by photolithography.

이때 상기 HSG 폴리실리콘(11)의 그레인(Grain) 사이에 제2산화막(4)이 잔존하게 된다.At this time, the second oxide film 4 remains between the grains of the HSG polysilicon 11.

이후 제2도의 (c)에 도시한 바와같이 상기의 포토레지스트(5)를 제거하고, 제2산화막(4)을 마스크로 사용하여 HSG 폴리실리콘(11)을 에칭하면, 에칭된 제2산화막(4)의 HSG 폴리실리콘(11)을 마스크로 사용하여 상기 제1질화막(3)을 에칭하고, 제2도의 (d)에 도시한 바와같이 에칭된 HSG 폴리실리콘(11)과 제1질화막(3)을 마스크로 사용하여 상기 제1산화막(2)을 에칭을 하는데 이때 HSG 폴리실리콘(11)상의 제2산화막(4)은 완전히 제거된다.Subsequently, as shown in FIG. 2C, the photoresist 5 is removed, and the HSG polysilicon 11 is etched using the second oxide film 4 as a mask. The first nitride film 3 is etched using the HSG polysilicon 11 of 4) as a mask, and the etched HSG polysilicon 11 and the first nitride film 3 are etched as shown in FIG. Is used as a mask to etch the first oxide film 2, wherein the second oxide film 4 on the HSG polysilicon 11 is completely removed.

또한 제2도의 (e)에 도시한 바와같이 상기 에칭된 제1질화막(3)과 제1산화막(2)을 마스크로 이용하여 상기 실리콘기판(1)을 에칭하는데 이 에칭중 상기 HSG 폴리실리콘(11)은 제거되며, 에칭된 실리콘기판(1)을 이온주입법을 사용하여 보론(BF2)을 주입하게된다.In addition, as shown in FIG. 2E, the silicon substrate 1 is etched using the etched first nitride film 3 and the first oxide film 2 as a mask, during which the HSG polysilicon ( 11) is removed, and boron (BF 2 ) is injected into the etched silicon substrate 1 using ion implantation.

이때 제2도의 (e)에서 보는바와같이 에칭된 부분사이에 남아있는 실리콘기판(1)의 길이를 ℓ이라 하면, 에칭된 부분으로 길이ℓ의 1/2두께(2999Å이하)에 해당하는 두께로 산화물을 산화하여 제2도의 (f)와같이 필드산화막(12)을 형성한다.At this time, if the length of the silicon substrate 1 remaining between the portions etched as ℓ as shown in (e) of FIG. 2 is ℓ, the etched portion has a thickness equivalent to 1/2 the thickness (less than 299929) of the length ℓ. The oxide is oxidized to form the field oxide film 12 as shown in FIG.

이후 상기 필드산화막(12)과 폴리실리콘(1)위에 제1산화막(2)과 제1질화막(3)을 제거하면 제2도의 (g)에 도시한 바와같이 완성된 반도체소자의 절연구조가 형성되어진다.Then, when the first oxide film 2 and the first nitride film 3 are removed on the field oxide film 12 and the polysilicon 1, the insulating structure of the completed semiconductor device is formed as shown in FIG. It is done.

상기에서 설명한 바와같이 본 발명은 산화시간이 짧고, 필드산화막의 두께가 얇으면서도 종래 방법에 의한 두께와 별차이가 없으며, 불순물양을 적게할 수 있어 접합기생캐패시턴스를 감소시킬수 있고, 또한 버드빅 폭을 필드산화시간으로 조정할수 있는 효과와, 버드빅 폭을 포함하여 0.5㎛수준으로 절연폭을 만들수 있고, 평활성을 높일수 있는 효과가 있다.As described above, the present invention has a short oxidation time, a thin field oxide film and no difference from the conventional method, and can reduce the amount of impurities, thereby reducing the junction parasitic capacitance and also the Budvik width. It can be adjusted to the field oxidation time, and the insulation width can be made to the level of 0.5㎛ including Budvik width, and the smoothness can be increased.

Claims (2)

실리콘기판(1)위에 제1산화막(2), 제1질화막(3), HSG 폴리실리콘(11), 제2산화막(4)을 연속형성하는 단계와, 상기 제2산화막(4), HSG 폴리실리콘(11), 제1질화막(3), 제1산화막(2), 실리콘기판(1)순으로 순차적으로 에칭하는 단계와, 상기 실리콘기판(1)의 에칭부분에 산화물을 산화하여 필드산화막(12)을 형성하는 단계와, 상기 필드산화막(12)위에 잔존하는 막을 제거하는 이루어짐을 특징으로 하는 반도체 소자 절연방법.Continuously forming the first oxide film 2, the first nitride film 3, the HSG polysilicon 11, and the second oxide film 4 on the silicon substrate 1, and the second oxide film 4 and the HSG poly Etching sequentially in order of the silicon 11, the first nitride film 3, the first oxide film 2, and the silicon substrate 1, and oxidizing an oxide in the etching portion of the silicon substrate 1 to obtain a field oxide film ( 12), and removing the remaining film on the field oxide film (12). 제1항에 있어서, 필드산화막(12) 형성시 산화막 뚜께를 2999Å이하인 것을 사용함을 특징으로 하는 반도체 소자 절연방법.The method of insulating a semiconductor device according to claim 1, wherein an oxide film thickness of 2999 kPa or less is used when forming the field oxide film (12).
KR1019930003568A 1993-03-10 1993-03-10 Semiconductor element isolation method KR100253268B1 (en)

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