KR960000373B1 - Step forming of semiconductor substratum surface - Google Patents
Step forming of semiconductor substratum surface Download PDFInfo
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- KR960000373B1 KR960000373B1 KR1019920017254A KR920017254A KR960000373B1 KR 960000373 B1 KR960000373 B1 KR 960000373B1 KR 1019920017254 A KR1019920017254 A KR 1019920017254A KR 920017254 A KR920017254 A KR 920017254A KR 960000373 B1 KR960000373 B1 KR 960000373B1
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- oxide film
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- epitaxial layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 230000001590 oxidative effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
Description
제1도는 종래의 기술에 따른 반도체 표면의 단차 형성 공정도.1 is a process diagram for forming a step of a semiconductor surface according to the prior art.
제2도는 본 발명에 따른 제1실시예의 반도체 표면의 단차 형성공정도.2 is a process chart for forming a step on the surface of the semiconductor of the first embodiment according to the present invention.
제3도는 본 발명의 제2실시예에 따른 단차 형성공정도.3 is a step forming process diagram according to a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2,6,9,10 : 산화막1: silicon substrate 2,6,9,10: oxide film
3 : 질화막 4a,4b,7a,7b : 포토레지스트3: nitride film 4a, 4b, 7a, 7b: photoresist
5a,5b : n-에피택셜층 8 : P-에피택셜층5a, 5b: n-epitaxial layer 8: P-epitaxial layer
본 발명은 반도체 표면의 단차 형성방법에 관한 것으로, 특히 선택적으로 에피택셜층을 성장시켜 경제면을 정확히 하고 단차 깊이 조정이 용이하도록 한 반도체 표면의 단차 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a step on a semiconductor surface, and more particularly, to a method of forming a step on a semiconductor surface in which an epitaxial layer is selectively grown to make the economic aspect accurate and the step depth adjustment is easy.
일반적으로 반도체 표면의 ′단차′의 의미는 표면부에서 함몰된 깊이를 말하고 있다. 반도체 제조공정에서 이러한 단차를 형성하는 목적은 메모리 장치(예. DRAM)등에서 셀(Cell)회로영역과 주변회로영역을 구분하여 셀(Cell)회로영역을 만들기 위해서이다.In general, the term 'step' of the semiconductor surface refers to the depth recessed in the surface portion. The purpose of forming such a step in a semiconductor manufacturing process is to make a cell circuit region by dividing a cell circuit region and a peripheral circuit region in a memory device (eg DRAM).
제1도는 종래의 방법에 따른 반도체의 단차 형성공정을 순서별로 도시하고 있다. 이하에서는 제1도를 참조하여 종래의 단차 형성방법을 설명하면 다음과 같다.1 shows a step forming process of a semiconductor according to a conventional method, in order. Hereinafter, a conventional step forming method will be described with reference to FIG. 1.
종래의 단차 형성방법은 제1도(a)에 도시한 바와 같이 실리콘기판(1)상에 두께 500Å∼100Å의 SiO2산화막(2a)를 성장시키고, 그 위에 다시 두께 1000Å-2000Å의 Si3N4질화막(3)를 형성한다.In the conventional step forming method, as shown in FIG. 1A, a SiO 2 oxide film 2a having a thickness of 500 to 100 Å is grown on the silicon substrate 1, and Si 3 N having a thickness of 1000 Å to 2000 Å is again formed thereon. Four nitride films 3 are formed.
이때, 산화막(2a) 두께와 질화막(3) 두께의 비율은 버즈 비크(Birds beak)를 고려하여 선정한다.At this time, the ratio between the thickness of the oxide film 2a and the thickness of the nitride film 3 is selected in consideration of the Birds beak.
그리고, 제1도(b)도와 같이 질화막(3)위에 포토레지스트(4a)를 피막하여, 반도체 칩내에서 셀회로가 형성될 영역(NMOS 영역)과 주변회로가 형성될 영역(CMOS 영역)을 한정한다.Then, as shown in FIG. 1 (b), a photoresist 4a is formed on the nitride film 3 to define a region (NMOS region) where a cell circuit is to be formed and a region where a peripheral circuit is to be formed (CMOS region) in the semiconductor chip. do.
제1도 (c)와 같이 포토레지스트(4a)를 마스크로 하여 셀회로 영역내의 질화막(3)를 건식 식각한다.As shown in Fig. 1 (c), the nitride film 3 in the cell circuit region is dry-etched using the photoresist 4a as a mask.
제1도 (d)와 같이 포토레지스트(4a)를 제거한다.As shown in Fig. 1 (d), the photoresist 4a is removed.
제1도 (e)와 같이 산소분위기에서 열처리하여 노출된 실리콘기판(1)에 산화막을 0.5㎛~1.5㎛ 두께로 성장시켜 회생산화막(2b)로 만든다.As shown in FIG. 1 (e), an oxide film is grown to a thickness of 0.5 μm to 1.5 μm on the exposed silicon substrate 1 by heat treatment in an oxygen atmosphere to form a ashed film 2b.
제1도 (f)와 같이 마스크로 사용된 질화막(3a,3b)를 제거한다.As shown in FIG. 1 (f), the nitride films 3a and 3b used as masks are removed.
제1도 (g)와 같이 상기 회생산화막(2b)를 제거하여 희생산화막(2b)를 제거한 부위에 단차를 형성한다.As shown in FIG. 1 (g), the ashing film 2b is removed to form a step at a portion from which the sacrificial oxide film 2b is removed.
도면을 참조한 설명으로부터 알 수 있는 바와 같이 셀 회로영역과 주변회로영역 사이의 표면단차는 희생산화막의 두께에 의하여 결정되어지며, 단차의 경사에 의한 경계지역의 너비 및 경사형태는 산화막과 질화막의 두께비율과, 희생산화막의 두께에 의하여 결정되어진다.As can be seen from the description with reference to the drawings, the surface step between the cell circuit area and the peripheral circuit area is determined by the thickness of the sacrificial oxide film, and the width and the slope shape of the boundary area due to the stepped slope are the thickness of the oxide film and the nitride film It is determined by the ratio and the thickness of the sacrificial oxide film.
그러나 이와 같은 종래의 단차 형성방법에 있어서는 다음과 같은 문제점이 있었다. 즉, 셀 회로영역에 단차를 형성하기 위하여 셀 회로영역에 선택적으로 희생산화막을 형성하고 희생산화막을 제거하여 단차를 형성하므로 희생산화막의 두께로 단차의 깊이를 조절해야 한다.However, the conventional step formation method has the following problems. That is, in order to form a step in the cell circuit region, a sacrificial oxide film is selectively formed in the cell circuit region and the sacrificial oxide film is removed to form a step, so the depth of the step must be controlled by the thickness of the sacrificial oxide film.
그런데 희생산화막 성장시 성장시간에 의해 희생산화막의 두께가 결정되므로 해서 희생산화막과 두께 조절이 어렵고 더블어 단차의 깊이 조절이 어렵다.However, since the thickness of the sacrificial oxide film is determined by the growth time during the growth of the sacrificial oxide film, it is difficult to control the thickness of the sacrificial oxide film and to control the depth of the double step.
뿐만 아니라, 희생산화막 형성시 가장자리 부분은 버즈-빅 형상으로 희생산화막이 성장되므로 버즈-빅 형상으로 인하여 셀 회로영역과 주변회로영역의 경계면이 정확하게 구별되지 않기 때문에 집적도가 저하된다.In addition, since the sacrificial oxide film grows in a buzz-big shape when the sacrificial oxide film is formed, the density decreases because the interface between the cell circuit area and the peripheral circuit area is not accurately distinguished due to the buzz-big shape.
가장 이상적인 셀 회로영역과 주변회로영역의 경계면은 수직을 이루는 것이 바람직하다.It is desirable that the interface between the most ideal cell circuit region and the peripheral circuit region be perpendicular.
또한 기판 재료로 단결정 실리콘을 사용하기 때문에 기판이 물리적으로 약하다.In addition, the substrate is physically weak because single crystal silicon is used as the substrate material.
본 발명의 목적은 종래의 이러한 문제점을 개선한 것으로서, 반도체 표면의 단차조정과 경계면 형태조정이 가능하며, 기판을 물리적으로 강한 에피택셜층을 이용한 반도체 표면단차 형성방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION An object of the present invention is to solve such problems in the related art, and to provide a method for forming a semiconductor surface step using a stepped epitaxial layer and a step height adjustment of the semiconductor surface, and an interface shape adjustment.
이하에서는 제2도 및 제3도를 참조한 실시예의 설명을 통하여 본 발명의 반도체 표면의 단차 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a step on a semiconductor surface of the present invention will be described with reference to FIGS. 2 and 3 as follows.
제2도 (a)-(m)도는 본 발명 일실시예에 따른 표면단차형성 공정도이다.2 (a)-(m) are surface step forming process diagrams according to an embodiment of the present invention.
단차형성을 위한 1단계로 (a)도처럼 실리콘 기판(1)상에 두께 500Å~1000Å의 SiO2산화막(2)을 전기로에서 성장시킨 후, 이 위에 두께 0.5㎛~1.5㎛의 SiO2산화막(3)을 CVD로 증착한다.A step for forming the step (a) around the column the silicon substrate 1 in an electric furnace, after growing an SiO 2 oxide film 2 having a thickness of 500Å ~ 1000Å on, the over thickness of 0.5㎛ ~ 1.5㎛ SiO 2 oxide ( 3) is deposited by CVD.
2단계(b도)는 산화막(3)위에 셀 회로영역과 주변 회로영역을 구분하기 위해 포토레지스트(3)를 피막하고 노광 및 형상공정으로 셀 회로영역상에 포토레지스트 (3)을 잔존시킨다.Step 2 (b) coats the photoresist 3 on the oxide film 3 to separate the cell circuit region and the peripheral circuit region, and leaves the photoresist 3 on the cell circuit region by exposure and shape processes.
그 다음에는 3단계(c도)로, 상기 포토레지스트(3)를 마스크로 이용하여 주변 회로영역의 산화막(2,3)을 제거 한다.Next, in step 3 (c), the oxide films 2 and 3 in the peripheral circuit region are removed using the photoresist 3 as a mask.
식각을 행할때에는 드러나는 실리콘기판(1)의 표면이 손상되지 않도록 건식 식각법이나 건식과 습식식각을 겸용하여 사용한다.When etching, dry etching or dry and wet etching are used in combination so as not to damage the surface of the exposed silicon substrate (1).
다음은 4단계(d)로 포토레지스트(4)를 제거하는 공정이다.The following is a process of removing the photoresist 4 in four steps (d).
(e)와 같이 산화막(2,3)이 제거된 주변 회로영역에 n-에피택셜층(5a,5b)을 선택적으로 형성한다.As shown in (e), n-epitaxial layers 5a and 5b are selectively formed in the peripheral circuit region from which the oxide films 2 and 3 are removed.
제 6단계(f도)는 n-에피택셜충(5a,5b)과 산화막(3)상에 두께 1000Å 이하의 SiO2산화막(6)을 형성하는 공정이다.The sixth step (degree f) is a step of forming a SiO 2 oxide film 6 having a thickness of 1000 Å or less on the n-epitaxial charges 5a and 5b and the oxide film 3.
제7단계(g도)는 셀 회로영역의 산화막(2,3,6)을 제거하기 위하여 포토레지스트(7a,7b)를 피막하여 셀 회로영역을 구분하는 공정이다.In the seventh step (g), the photoresists 7a and 7b are coated to remove the oxide films 2, 3 and 6 of the cell circuit region, thereby distinguishing the cell circuit regions.
8단계(h도) 및 9단계(i도) 포토레지스트(7a,7b)를 이용하여 산화막을 제거한 후, 포토레지스트(7a,7b)를 제거했을 때의 상태를 도시하고 있다.The state when the photoresist 7a, 7b is removed after removing the oxide film using the photoresist 7a, 7b in steps 8 (h) and 9 (i) is shown.
10단계(j도)는 셀 회로영역에만 P형이 도핑된 에피택셜층(8)을 선택적으로 성장시킨다.Step 10 (j degrees) selectively grows the epitaxial layer 8 doped with P type only in the cell circuit region.
이때에 에피택셜층(8)의 두께는 다음 공정에서 토폴로지(topology)로 기인되는 포토레지스트 공정의 촛점심도문제를 보상하여 줄 수 있도륵 주변회로 영역의 P형 에피택셜층과 비교하여 적정하게 선택한다.At this time, the thickness of the epitaxial layer 8 is appropriately selected in comparison with the P-type epitaxial layer in the peripheral circuit region to compensate for the depth of focus problem of the photoresist process caused by the topology in the following process. do.
11단계(k도) 및 12단계(l도)는 각각 주변회로 영역의 산화막(6)의 제거공정과, 표면단차경계면의 단차형태를 부드럽게 하기 위하여 희생산화막(9)을 성장하는 공정을 도시하고 있다.Step 11 (k degrees) and step 12 (l degrees) respectively show a step of removing the oxide film 6 in the peripheral circuit region and a step of growing the sacrificial oxide film 9 to smooth the stepped shape of the surface step boundary surface. have.
13단계(m도)는 마지막 공정으로서 희생산화막(9)을 제거한 후의 상태를 도시하고 있다.Step 13 (m degrees) shows the state after removing the sacrificial oxide film 9 as a final step.
제3도는 본 발명 다른 실시예에 따른 반도체표면의 단차형성 공정단면도이다.3 is a cross-sectional view of a step forming process of a semiconductor surface according to another embodiment of the present invention.
즉, 제2도(e)와 같이 산화막(2,3)이 제거된 주변회로 영역에 n-에피택셜층 (5a,5b)를 선택적으로 형성한다음, 정정 촛점 심도의 보상을 위한 산화막의 두께를 선정하고 셀 회로영역은 기판실리콘을 사용한다면 제3도 (a)와 같이 산화막(2,3)을 제거한다.That is, as shown in FIG. 2E, n-epitaxial layers 5a and 5b are selectively formed in the peripheral circuit region from which the oxide films 2 and 3 are removed, and then the thickness of the oxide film to compensate for the depth of correction focus. If the cell circuit region is made of silicon, the oxide films 2 and 3 are removed as shown in FIG.
그리고 제3도(b)와 같이 표면 단차면의 단차형태를 부드럽게 하기 위하여 열산화공정으로 노출된 기판전면에 희생산화막(10)을 형성하고 제3도(c)와 같이 희생산화막을 제거하므로 한번의 선택적 에피택셜층 성장으로 표면 단차를 형성할 수도 있다. 이상에서 설명한 바와 같은 본 발명의 표면 단차형성방법에 있어서는 선택적 에피택셜층 성장에 의해 단차를 형성하므로 버즈 빅 형상에 의한 경제면의 부정확성을 방지하는 에피택셜층의 높이에 의해 단차 깊이를 쉽게 조절할 수 있으므로 단차 깊이 조정이 용이하는 등의 효과가 있다In addition, since the sacrificial oxide film 10 is formed on the entire surface of the substrate exposed by the thermal oxidation process as shown in FIG. 3 (b) and the sacrificial oxide film is removed as shown in FIG. Selective epitaxial layer growth of may form a surface step. In the surface step forming method of the present invention as described above, since the step is formed by the selective epitaxial layer growth, the step depth can be easily adjusted by the height of the epitaxial layer which prevents the inaccuracy of the economic surface due to the buzz big shape. There are effects such as easy step height adjustment.
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| KR1019920017254A KR960000373B1 (en) | 1992-09-22 | 1992-09-22 | Step forming of semiconductor substratum surface |
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| KR1019920017254A KR960000373B1 (en) | 1992-09-22 | 1992-09-22 | Step forming of semiconductor substratum surface |
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| KR940007996A KR940007996A (en) | 1994-04-28 |
| KR960000373B1 true KR960000373B1 (en) | 1996-01-05 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920017254A KR960000373B1 (en) | 1992-09-22 | 1992-09-22 | Step forming of semiconductor substratum surface |
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| Country | Link |
|---|---|
| KR (1) | KR960000373B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980030446A (en) * | 1996-10-29 | 1998-07-25 | 김영환 | Semiconductor substrate and formation method thereof |
| KR100504940B1 (en) * | 2000-12-29 | 2005-08-03 | 주식회사 하이닉스반도체 | Method of forming a selective monocrystal silicon film in a semiconductor device |
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1992
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| Publication number | Publication date |
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| KR940007996A (en) | 1994-04-28 |
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