KR940022787A - Semiconductor Device Insulation Method - Google Patents

Semiconductor Device Insulation Method Download PDF

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Publication number
KR940022787A
KR940022787A KR1019930003568A KR930003568A KR940022787A KR 940022787 A KR940022787 A KR 940022787A KR 1019930003568 A KR1019930003568 A KR 1019930003568A KR 930003568 A KR930003568 A KR 930003568A KR 940022787 A KR940022787 A KR 940022787A
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KR
South Korea
Prior art keywords
oxide film
width
semiconductor device
budvik
insulation
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Application number
KR1019930003568A
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Korean (ko)
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KR100253268B1 (en
Inventor
박유배
송인정
Original Assignee
문정환
금성알렉트론 주식회사
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Priority to KR1019930003568A priority Critical patent/KR100253268B1/en
Publication of KR940022787A publication Critical patent/KR940022787A/en
Application granted granted Critical
Publication of KR100253268B1 publication Critical patent/KR100253268B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자 절연방법에 관한 것으로, 종래의 반도체 소자 절연방법은 버드빅 확산방지를 위해 2회의 질화막증착 및 에칭을 하므로 실리콘의 결정적소자가 급격히 변화되고, 불순물의 양을 필요보다 크게 해야 하기 때문에 접합기생캐패시턴스가 커지며, 절연폭을 1㎛ 이내로 줄이기 어렵고, 2회에 걸쳐 필드산 화막을 형성함으로 공정에 번거로운 문제점이 있었다.The present invention relates to a method for insulating a semiconductor device, and the conventional method for insulating a semiconductor device performs two deposition and etching of nitride films to prevent Budvik diffusion. Therefore, the critical device of silicon is rapidly changed and the amount of impurities must be larger than necessary. Therefore, the parasitic capacitance of the junction becomes large, and it is difficult to reduce the insulation width to within 1 μm, and there is a troublesome process in forming the field oxide film twice.

본 발명은 이러한 문제점을 해결하기 위하여 확실한 매몰산화가 이루어지면서 HSG폴리실리콘을 마스크로 사용하여 절연을 하는 것으로써 버드빅 폭을 필드산화시간으로 조정가능하고, 불순물양을 적게 할 수 있어 접합기생캐패시턴스를 줄일수 있으며, 절연폭을 버드빅 폭을 포함하여 0.5㎛ 수준으로 만들수 있게 된다.In order to solve the above problems, the present invention is able to adjust Budvik width by field oxidation time and reduce the amount of impurities by performing insulation using HSG polysilicon as a mask while making sure investment oxidation. The insulation width can be reduced to 0.5㎛ including Budvik width.

Description

반도체 소자 절연방법Semiconductor Device Insulation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가) 내지 (사)는 본 발명 반도체소자 절연방법 공정 순서도이다.2A to 2G are process flowcharts of the semiconductor device insulation method of the present invention.

Claims (2)

실리콘기판(1)위에 제1산화막(2), 제1질화막(3), HSG폴리실리콘(11), 제2산화막(4)을 연속형성하는 단계와, 상기 제2산화막(4), HSG폴리실리콘(11), 제1질호막(3), 제1산화막(2), 실리콘기판(1) 순으로 순차적으로 에칭하는 단계와, 상기 실리콘기판(1)의 에칭부분에 산화물을 산화하여 필드산화막(12)을 형성하는 단계와, 상기 필드산화막(12) 위에 잔존하는 막을 제거하는 이루어짐을 특징으로 하는 반도체소자 절연방법.Continuously forming the first oxide film 2, the first nitride film 3, the HSG polysilicon 11, and the second oxide film 4 on the silicon substrate 1, and the second oxide film 4 and the HSG poly Etching sequentially in order of the silicon 11, the first protective film 3, the first oxide film 2, and the silicon substrate 1, and oxidizing an oxide in the etching portion of the silicon substrate 1 to form a field oxide film. (12), and removing the remaining film on the field oxide film (12). 제1항에 있어서, 필드산화막(12) 형성시 산화막 두께를 2999Å 이하인 것을 사용함을 특징으로 하는 반도체 소자절연 방법.The semiconductor device insulation method according to claim 1, wherein an oxide film thickness of 2999 kPa or less is used when forming the field oxide film (12). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003568A 1993-03-10 1993-03-10 Semiconductor element isolation method KR100253268B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003568A KR100253268B1 (en) 1993-03-10 1993-03-10 Semiconductor element isolation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003568A KR100253268B1 (en) 1993-03-10 1993-03-10 Semiconductor element isolation method

Publications (2)

Publication Number Publication Date
KR940022787A true KR940022787A (en) 1994-10-21
KR100253268B1 KR100253268B1 (en) 2000-04-15

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KR1019930003568A KR100253268B1 (en) 1993-03-10 1993-03-10 Semiconductor element isolation method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990077613A (en) * 1998-03-06 1999-10-25 클라크 3세 존 엠. Electronic isolation utilizing lateral fill recessed locos

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990077613A (en) * 1998-03-06 1999-10-25 클라크 3세 존 엠. Electronic isolation utilizing lateral fill recessed locos

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Publication number Publication date
KR100253268B1 (en) 2000-04-15

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