KR950011642B1 - Dram using a bit line contact or capacitor contact - Google Patents

Abstract

The method for fabricating the DRAM comprises the steps of forming a gate insulation layer and a field insulation layer on the silicon substrate and forming a gate electrode thereon; forming a mask pattern by spreading a positive photoresist layer thereon; etching the first polysilicon layer by using the mask pattern and laying a second polysilicon layer thereon; forming a plug contact hole for a bit line and a capacitor by etching the first plane insulation layer and the first insulation layer; forming a sensitive film pad pattern; forming a sensitive contact pattern for the bit line by using the positive photoresist layer for the bit line; forming a polysilicon bit line contact mask of the spacer shape; and forming the bit line with the bit line contact; forming a sensitive contact pattern of the capacitor contact; and forming a capacitor contact.

Description

DRAM with bitline contacts and capacitor contacts

1 is a cross-sectional view of a semiconductor device showing the steps of forming a gate insulating film and a field insulating oxide film on a silicon substrate, forming a gate electrode thereon, and sequentially stacking the first insulating film and the first planarization insulating film thereon.

FIG. 2 is a cross-sectional view of a semiconductor device illustrating a step of forming a mask pattern by applying a photoresist layer after laminating a first polysilicon layer on the first planarization insulating film of FIG.

3 is a cross-sectional view of a semiconductor device illustrating etching a first polysilicon layer using a mask pattern and then stacking a second polysilicon layer thereon.

FIG. 4 is a semiconductor device illustrating etching a second polysilicon layer of FIG. 3 to form a polysilicon contact mask having a spacer structure, and then etching a lower insulating layer to form a plug contact hole for a bit line and a capacitor. Section.

FIG. 5 illustrates stacking a plug polysilicon layer on top of a plug contact hole and a spacer structure formed in FIG. 4, and then etching the plug polysilicon layer without a mask as necessary, and then negative on the plug polysilicon layer. A cross-sectional view of a semiconductor device showing a step of applying a photoresist layer to form a photosensitive film pad pattern.

FIG. 6 illustrates etching the plug polysilicon layer and the first polysilicon layer using the photosensitive film pad pattern of FIG. 5, and then laminating a second insulating layer and a third polysilicon layer on top of each other, and forming a positive photoresist layer. A cross-sectional view of a semiconductor device showing a step of forming an oversized photoresist contact pattern of a bit line contact by using.

FIG. 7 illustrates etching the third polysilicon layer by using the oversized photoresist contact pattern of FIG. 6 and then laminating and etching the fourth polysilicon layer thereon to form a polysilicon bit line contact mask having a spacer structure. Sectional drawing of the semiconductor element which shows.

8 illustrates etching a predetermined portion of the second insulating layer using a polysilicon bit line contact mask, and sequentially forming a bit line polysilicon layer and a silicide layer on top thereof, and then forming a bit line through an etching process. Sectional drawing of the semiconductor element which shows the step to carry out.

FIG. 9 is a planarized layer of a third insulating film and a second planarization insulating film on the bit line silicide layer of FIG. 8, and then a fifth polysilicon layer is laminated and a positive photoresist layer is coated on the photoresist contact of the capacitor contact. A cross-sectional view of a semiconductor device showing a step of forming a pattern.

FIG. 10 illustrates etching the fifth polysilicon layer using the photosensitive film contact pattern of FIG. 9, stacking the sixth polysilicon layer on the upper portion thereof, and performing an etching process to form a polysilicon capacitor contact mask having a spacer structure. Cross-sectional view of a semiconductor device showing the steps.

FIG. 11 is a semiconductor device illustrating a step of forming a capacitor contact by sequentially etching a second planarization insulating film, a third insulating film, and a second insulating film using the polysilicon capacitor contact mask of FIG. 10, and then stacking a polysilicon layer for a capacitor. Section.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 gate insulating film

3: gate electrode 4: field insulating film

5: first insulating film 6: first planarization insulating film

7: first polysilicon layer

8: positive photoresist for bit line and capacitor contact mask

9: second polysilicon layer 9 ': second polysilicon spacer

10: plug polysilicon layer for bitline and capacitor

11: negative photosensitive film 12: second insulating film

13: third polysilicon layer

14 positive photoresist layer for bit line contact mask

15: fourth polysilicon spacer 16: bitline polysilicon layer

17 bit line silicide layer 18 third insulating film

19: second planarization insulating film 20: fifth polysilicon layer

21: Positive photoresist film for capacitor contact mask

22: sixth polysilicon spacer 23: polysilicon layer for capacitor

The present invention relates to a DRAM (Dynamic Random Access Memory) having a bit line contact and a capacitor contact and a method of manufacturing the same, and in particular, to secure a sub-half μm-sized bit line and a capacitor contact even in a flattened high step. The present invention relates to a DRAM (Dynamic Random Access Memory) having a bit line contact and a capacitor contact and a method of manufacturing the same.

In general, as the degree of integration of semiconductor devices increases, the design value decreases, while the topology becomes deeper. Therefore, when manufacturing an ultra-high density device having an integration degree of 16M DMAM or higher, As one of the methods, the planarization process is generally implemented. However, in order to adopt the planarization process described above, development of a technology capable of stably forming a contact having a reduced design value and a planarized high step must be preceded.

As a conventional photoresist pattern forming method for forming a contact having a sub-half μm size, after manufacturing a hard mask contact pattern having a spacer structure, the contact etching is performed using the contact pattern as a mask. When the above method is applied to a contact having a high step by the planarization process, wear of the mask itself is greatly generated during contact etching, which makes it difficult to implement reproducible contact etching.

Therefore, in order to solve the above-mentioned problems, the present invention provides a DRAM having a bit line capacitor contact which can stably secure a sub-half μm-sized bit line and capacitor contact even in a high level flattened step. It is an object to provide a method.

In order to achieve the above object, the present invention provides a method of forming a silicon substrate, forming a gate insulating film and a field insulating film on the silicon substrate, and forming a gate electrode thereon, and a first insulating film on the gate electrode. And sequentially stacking a first planarization insulating layer, stacking a first polysilicon layer on the first planarization insulating layer, and then applying a positive photoresist layer thereon to form a mask pattern; Etching the first polysilicon layer using a pattern and then laminating a second polysilicon layer thereon; and etching the second polysilicon layer to form a polysilicon contact mask having a spacer structure. Etching the first planarization insulating layer and the first insulating layer to form a plug contact hole for the bit line and the capacitor; After stacking the bit line and capacitor plug polysilicon layer on the first polysilicon layer of the plug contact hole and spacer structure for the capacitor, the plug polysilicon layer is etched without mask as necessary, and then the negative photoresist layer on the top. Forming a photoresist pad pattern, etching a predetermined portion of the plug polysilicon layer and the first polysilicon layer for the bit line and the capacitor using the photoresist pad pattern, and then forming a second insulating layer Stacking a third polysilicon layer, forming a bit line photoresist contact pattern using a bit line positive photoresist layer, and using a bit line photoresist contact pattern, a predetermined portion of the third polysilicon layer After etching, the fourth polysilicon layer is laminated thereon, and the fourth polysilicon layer is etched to form a spacer structure. Forming a polysilicon bitline contact mask, etching a predetermined portion of the second insulating layer using the polysilicon bitline contact mask, and sequentially forming a bitline polysilicon layer and a bitline silicide layer thereon; After stacking, forming a bit line contact on the bit line plug polysilicon layer through an etching process, laminating and planarizing a third insulating film and a second planarization insulating film on the bit line silicide layer, Stacking a 5 polysilicon layer, applying a positive photoresist layer thereon, and forming a photoresist contact pattern of a capacitor contact; and using the photoresist contact pattern of the capacitor contact, using the second planarization insulating film and the third After etching to the predetermined portion of the insulating film and the second insulating film, the plug polysilicon layer for capacitor is deposited Characterized in that it comprises a step of forming a capacitor over the contact.

The present invention also provides a silicon substrate, a gate electrode formed on the gate insulating film and a field insulating film formed on the silicon substrate, a first insulating film and a first planarization insulating film formed on the gate electrode, and the first flattening. Bit line and capacitor plug polysilicon layers formed by depositing a polysilicon layer in the bit line and capacitor plug contact holes formed by etching the insulating film and the first insulating layer, and on top of the plug polysilicon layer for the bit line and capacitor A pad having a second polysilicon spacer formed thereon, a second insulating layer formed on the pad, a bit line polysilicon layer formed thereon after etching the second insulating layer, and a bit line silicide And a third polysilicon layer and a fourth polysilicon spacer under the layer and the third insulating layer, A bit line contact formed on the polysilicon layer, a second planarization insulating film formed on the third insulating film, a fifth polysilicon layer formed on the second planarizing insulating film, and having a sixth polysilicon spacer; And a capacitor contact formed by etching the second planarization insulating layer, the third insulating layer, and the second insulating layer to a predetermined portion, and then depositing a capacitor polysilicon layer on the capacitor plug polysilicon layer.

Hereinafter, the present invention will be described in detail with the accompanying drawings.

1 shows a gate insulating film 2 and a field insulating film 3 formed on a silicon substrate 1, a gate electrode 4 formed thereon, and a first insulating film 5 and a first planarization formed thereon. A cross-sectional view of a semiconductor device showing the steps of sequentially stacking the insulating film 6, and FIG. 2 shows a first polysilicon layer 7 stacked on top of the first planarization insulating film 6 in FIG. A cross-sectional view of a semiconductor device showing a step of applying a resist layer 8 to form a mask pattern, when forming a mask pattern, forming an oversized photoresist contact pattern larger than the actual contact size for bit lines and capacitor contacts. do.

FIG. 3 is a cross-sectional view of a semiconductor device illustrating etching the first polysilicon layer 7 using the photoresist pattern of FIG. 2 and then laminating a second polysilicon layer 9 thereon. Since the polysilicon contact hard mask pattern of the spacer structure having a size reduced to about 1/2 the thickness of the second polysilicon layer 9 is formed, it is possible to form a fine plug contact pattern having a Sub-Half μm size.

The second polysilicon layer 9 of FIG. 3 is etched to form a polysilicon contact mask having a spacer structure, and then the first planarization insulating layer 6 and the first insulating layer 5 are etched to form bit lines and A cross-sectional view of a semiconductor device showing a step of forming a plug contact hole (A) for a capacitor, wherein the second polysilicon layer (9) is etched by dry etching without a mask to form a polysilicon contact mask having a spacer structure and then masked it As a result, electrolytic etching is performed on the lower insulating film to simultaneously form the plug contact hole A of the bit line and the capacitor.

FIG. 5 shows the plug polysilicon layer as necessary after stacking the plug polysilicon layer 10 for the bit line and the capacitor on the first polysilicon layer 7 of the structure in the plug contact hole A and the spore of FIG. After etching without a mask, a cross-sectional view of a semiconductor device showing a step of forming a photoresist pattern by applying a negative photoresist layer 11 thereon, wherein the bit line and capacitor plug polysilicon layer 10 having a predetermined thickness is formed. After laminating, the oversized contact masks for the bit line and capacitor contacts are used again, but the photoresist film is operated with a negative photoresist to form a photoresist pad pattern corresponding to an oversized contact size larger than the actual contact size on the pollug. Form.

In this case, the pad formation is possible without additionally using a mask for pad formation, and the overlap margin between the pad P and the plug is automatically secured by the lamination thickness value of the second polysilicon layer 9.

FIG. 6 illustrates etching the bit line and capacitor plug polysilicon layer 10 and the first polysilicon layer 7 using the photosensitive film pad pattern of FIG. 3 is a cross-sectional view of a semiconductor device showing the steps of stacking a polysilicon layer 13 and forming an oversized photoresist contact pattern of a bit line contact using the positive photoresist layer 14.

FIG. 7 illustrates the etching of the third polysilicon layer 13 using the oversized photoresist contact pattern of FIG. 6, followed by stacking and etching a fourth polysilicon layer (not shown) on top of the fourth polysilicon spat. (15) A cross-sectional view of a semiconductor device showing a step of forming a polysilicon bit line contact mask having a structure, wherein after forming an oversized photoresist contact pattern on the third polysilicon layer 13 by dry etching, fourth polysilicon is formed. The layers are laminated and dry etched without a mask to form a polysilicon bitline contact mask having a fourth polysilicon spacer 15 structure.

8 illustrates etching a predetermined portion of the second insulating layer 12 using the polysilicon bit line contact mask of FIG. 7, and sequentially stacking the bit line polysilicon layer 16 and the silicide layer 17 thereon. A cross-sectional view of a semiconductor device showing a step of forming a bit line through an etching process, and since etching is performed only to the upper portion of the bit line plug 10 during the bit line contact etching by dry etching, the spacer 15 structure Even when dry etching using the polysilicon layer as a mask, instability of mask layer wear is reduced, thereby making it possible to stably secure a bit line contact having a Sub-Half μm size.

FIG. 9 illustrates a planarization process by stacking a third insulating film 18 and a second planarization insulating film 19 such as BPSG on top of the bit line silicide layer of FIG. 8, and etching the fifth polysilicon layer 20 thereon. Next, a cross-sectional view of the semiconductor device, which illustrates a method of forming a photoresist contact pattern of a capacitor contact after laminating a sixth polysilicon layer (not shown) on the top and applying a photoresist layer 21 on the top thereof. Forming a polysilicon capacitor contact mask having a sixth polysilicon spacer 22 structure by laminating the fifth polysilicon layer 20 by using a photosensitive film contact pattern of 9 degrees and performing an etching process. It is a cross section.

FIG. 11 is a cross-sectional view of forming a capacitor contact by dry etching and stacking a polysilicon layer 23 for a capacitor. Since the etching of the capacitor contact only needs to be performed to the upper portion of the capacitor plug 10 ″, the sixth polysilicon spacer (22) Even when dry etching is performed using the polysilicon layer having a mask as a mask, instability is reduced due to wear of the mask layer, thereby making it possible to stably secure a capacitor contact having a Sub-Half µm size.

As described above, according to the DRAM having the bit line contact and the capacitor contact of the present invention and a method of manufacturing the same, while performing etching using a polysilicon contact pattern having a spacer structure as a mask, a plug pad may be used to reduce wear of the mask. By performing contact etching after performing the etching to be formed, it is possible to reproducibly secure a contact having a Sub-Half µm size with respect to the flattened high step.

Claims (6)

A method of forming a DRAM having a bit line contact and a capacitor contact, the method comprising: providing a silicon substrate 1, forming a gate insulating film 2 and a field insulating film 3 on the silicon substrate 1, and on top of the silicon substrate 1; Forming a gate electrode 4, sequentially laminating a first insulating film 5 and a first flattening insulating film 6 on the gate electrode 4, and forming an upper portion of the first flattening insulating film 6. After laminating the first polysilicon layer (7) on, and applying a positive photoresist layer (8) thereon to form a mask pattern, the first polysilicon layer (7) using the mask pattern After etching the step of laminating a second polysilicon layer (9) on top, and etching the second polysilicon layer (9) to form a polysilicon contact mask having a structure (9 ') in the spe, The first planarization insulating layer 6 and the first insulating layer 5 are etched to form bit lines and a cache. Forming a plug plug contact hole (A) for the sheeter, and a plug for the bit line and capacitor on the first polysilicon layer (7) having the plug contact hole (A) and the spacer (9 ') structure for the bit line and the capacitor. Stacking the polysilicon layer 10 and etching the plug polysilicon layer without a mask as necessary, and then applying a negative photoresist layer 11 thereon to form a photoresist pad pattern, and the photoresist pad pattern After etching, a predetermined portion of the plug polysilicon layer 10 and the first polysilicon layer 7 for the bit line and the capacitor is etched, and the second insulating layer 12 and the third polysilicon layer 13 are disposed thereon. And forming a bit line photoresist contact pattern using the bit line positive photoresist layer 14, and using the bit line photoresist contact pattern, predetermined of the third polysilicon layer 13. Etched part Stacking a fourth polysilicon layer thereon and etching the fourth polysilicon layer to form a polysilicon bitline contact mask having a spacer 15 structure, and using the polysilicon bitline contact mask After etching a predetermined portion of the second insulating layer 12, the bit line polysilicon layer 16 and the bit line silicide layer 17 are sequentially stacked thereon, and then the plug poly for the bit line is subjected to an etching process. Forming a bit line having a bit line contact on the silicon layer 10 ', and planarizing a third insulating film 19 and a second planarization insulating film 20 on the bit line silicide layer 17 by laminating it. Thereafter, laminating a fifth polysilicon layer, applying a positive photoresist layer thereon, and forming a photoresist contact pattern of a capacitor contact, and forming a photoresist contact pattern of the capacitor contact. By performing etching to a predetermined portion of the second planarization insulating film 19, the third insulating film 18 and the second insulating film 12, and then depositing a capacitor plug polysilicon layer 23 to form a capacitor contact. And a bit line contact and a capacitor contact. A DRAM having a bit line contact and a capacitor contact, comprising: a silicon substrate 1, a gate insulating film 2 formed on the silicon substrate 1, and a gate electrode 4 formed on the field insulating film 3; And a bit line and a capacitor formed by etching the first insulating film 5 and the first planarization insulating film 6 formed on the gate electrode 4, and the first flattening insulating film 6 and the first insulating film 5. Bit line and capacitor plug polysilicon layer 10 formed by depositing a polysilicon layer inside the plug contact hole (A) for the bit line and the capacitor is formed on the plug polysilicon layer 10 above, After etching the pad P having the second polysilicon spacer 9 ', the second insulating film 12 formed on the pad P, and the second insulating film 12 thereon. Bitline polysilicon layer 16 formed, bitline silicide layer 17 and third A bit line contact having a third polysilicon layer 13 and a fourth polysilicon spacer 15 under the smoke screen 18 and a lower portion, and formed on the plug polysilicon layer 10 'for the bit line; A second planarization insulating film 19 formed on the insulating film 18, a fifth polysilicon layer 22 formed on the second planarization insulating film 19, and having a sixth polysilicon spacer 20; After etching to a predetermined portion of the second planarization insulating film 19, the third insulating film 18, and the second insulating film 12, the capacitor polysilicon layer 23 is deposited on the capacitor plug polysilicon layer 10 ″. And a capacitor contact, wherein the DRAM has a bit line contact and a capacitor contact. 3. The DRAM according to claim 2, wherein the bit line and capacitor contact patterns formed on the first polysilicon (7) are formed larger than the actual contact size. The size of the photoresist pad pattern for the bit line capacitor formed on the bit line and the capacitor plug polysilicon layer 10 deposited in the bit line and the capacitor plug contact hole A is larger than the actual contact size. And a bit line contact and a capacitor contact formed. 3. The DRAM of claim 2 wherein the bitline contact pattern formed on the third polysilicon layer (13) is larger than its actual size. 3. The DRAM of claim 2, wherein a capacitor contact pattern formed on the second planarization insulating film (20) is formed larger than its actual size.