KR20010036327A - Fabricating method of capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to simplify a manufacturing process and reduce manufacturing time and cost, by simultaneously forming a storage node contact and an electrode through deposition and etch-back of the second polysilicon. CONSTITUTION: The first insulating layer is formed on a semiconductor substrate(21) having a plug(24) selectively connected to a specific region of a device, and a bitline(26) is patterned on the first insulating layer. The second and third insulating layers are sequentially formed on the resultant structure, and a storage node photolithography process is performed regarding the third insulating layer until the second insulating layer is exposed. The first polysilicon is deposited on the resultant structure and etched back to form the first polysilicon sidewall on an etched side surface of the third insulating layer. The second insulating layer is etched by using the third insulating layer and a sidewall as a mask. The second polysilicon is deposited on the entire surface after the plug is exposed and is etched back. A dielectric layer(31) and a plate electrode(32) are sequentially formed on the entire surface of the resultant structure.

Description

Capacitor Manufacturing Method {FABRICATING METHOD OF CAPACITOR}

The present invention relates to a capacitor manufacturing method, and more particularly, to a capacitor manufacturing method for simplifying the storage node (storage node) formation of the capacitor.

A detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1F attached to a capacitor manufacturing method of a conventional COB (capacitor over bit line) structure.

First, as shown in FIG. 1A, an insulating film 3 is formed on the semiconductor substrate 1 on which the field region 2 and the device (not shown) are formed, and then a portion thereof is etched and filled with a conductive material to identify the device. A plug 4 selectively connected to the region is formed, and an insulating film 5 is formed on the upper surface to insulate and planarize interlayers, and a bit line 6 is formed by depositing and patterning a conductive material on the insulating film 5. do.

As shown in FIG. 1B, the insulating film 7 and the polysilicon 8 are sequentially formed on the upper surface of the structure in which the bit line 6 is patterned, and then the polysilicon in the region where the plug 4 is formed. (8) is selectively etched to expose the insulating film 7.

In addition, as shown in FIG. 1C, polysilicon is deposited on the resultant and then etched back to form sidewalls 9 of polysilicon on the etched side of the polysilicon 8. .

As shown in FIG. 1D, the polysilicon 8 and the sidewall 9 are applied as a mask to etch the lower insulating layers 7 and 5 to form a contact hole so that the plug 4 is exposed. A storage node contact is formed by depositing polysilicon 10 on the upper surface and etching back with the polysilicon 8 and the sidewall 9 to fill the contact hole until the insulating layer 7 is exposed. Next, an oxide film 11 is formed on the upper front surface.

As shown in FIG. 1E, the storage node contact is selectively etched by applying a storage node photolithography on the oxide layer 11, and then the polysilicon 12 and the insulating layer 13 are sequentially formed on the upper surface thereof. The insulating layer 13 is etched back until the polysilicon 12 is exposed, and then the exposed polysilicon 12 is etched back to form a storage node electrode.

As shown in FIG. 1F, the insulating layer 13 is removed by wet etching, and a dielectric layer 14 of NO material and a plate electrode 15 of polysilicon are sequentially formed on the upper surface thereof.

However, the conventional capacitor manufacturing method as described above requires two photolithography processes, four polysilicon deposition processes, and one wet etching process as the storage node contact and electrode formation are performed separately. Due to this, there is a problem in that the production time and cost increase and the yield is lowered.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a capacitor manufacturing method that can simplify the process by proceeding the storage node contact and electrode formation at the same time.

1A to 1F are cross-sectional views showing a conventional capacitor manufacturing method.

2a to 2f are cross-sectional views showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

21: semiconductor substrate 22: field area

23, 25, 27, 28: insulating film 24: plug

26: bit line 29: polysilicon sidewall

30: polysilicon 31: dielectric film

32: plate electrode

A capacitor manufacturing method for achieving the object of the present invention as described above forms a first insulating film on a semiconductor substrate with a plug selectively connected to a specific region of the device, and patterning the bit line on top of the first insulating film Process of doing; Sequentially forming second and third insulating layers on the bit patterned structure, and then etching the second insulating layer by exposing a storage node photolithography on the third insulating layer to expose the second insulating layer; Depositing first polysilicon on the upper surface of the structure and then etching back to form first polysilicon sidewalls on the etched side of the third insulating layer; Etching the second insulating layer by applying the third insulating layer and the sidewalls as a mask to expose the plug, and then depositing and etching back the second polysilicon on the upper surface; And a step of sequentially forming a dielectric film and a plate electrode on the upper front surface of the resultant.

Referring to the cross-sectional view of the procedure of Figure 2a to 2f attached to the capacitor manufacturing method according to the present invention as an embodiment in detail as follows.

First, as shown in FIG. 2A, an insulating film 23 is formed on the semiconductor substrate 21 on which the field region 22 and the element (not shown) are formed, and then a portion thereof is etched to fill the conductive material to identify the element. A plug 24 is formed to be selectively connected to the region, and an insulating film 25 is formed on the upper surface thereof to insulate and planarize interlayers, and then a bit line 26 is formed by depositing and patterning a conductive material on the insulating film 25. do.

As shown in FIG. 2B, insulating layers 27 and 28 are sequentially formed on the upper surface of the structure in which the bit lines 26 are patterned, and then a storage node photolithography is applied on the insulating layer 28 to form an insulating layer (FIG. Etch until 27) is exposed. At this time, it is preferable to form the material having the etching selectivity with each other as the insulating film 27 must remain at the time of etching the insulating film 28, and the insulating film 28 is a conventional capacitor oxide film, considering the capacitance of the capacitor and is appropriate. Deposit to height.

As shown in FIG. 2C, polysilicon is deposited on the upper surface of the resultant and then etched back to form polysilicon sidewalls 29 on the etched side of the insulating layer 28.

As shown in FIG. 2D, the plug 24 is exposed by etching the insulating film 27 by applying the insulating film 28 and the sidewall 29 as a mask.

As shown in FIG. 2E, polysilicon 30 is deposited on the upper surface of the resultant and then etched back to simultaneously form a storage node contact and an electrode. At this time, it is preferable that the etch-back of the polysilicon 30 proceed excessively to prevent short circuit between adjacent capacitors.

As shown in FIG. 2F, the NO dielectric layer 31 and the polysilicon plate electrode 32 are sequentially formed on the upper surface of the resultant product.

Capacitor manufacturing method according to the present invention as described above is a photolithography process and two polysilicon deposition process according to the storage node contact and the electrode formation is formed at the same time through the deposition and etch-back of the second polysilicon 30 And the wet etching process can be omitted so that the process is simplified, thereby reducing the manufacturing time and cost has the effect of improving the yield.

Claims (2)

Forming a first insulating film on a semiconductor substrate having a plug selectively connected to a specific region of the device, and patterning a bit line on the first insulating film; Sequentially forming second and third insulating layers on the bit patterned structure, and then etching the second insulating layer by exposing a storage node photolithography on the third insulating layer to expose the second insulating layer; Depositing first polysilicon on the upper surface of the structure and then etching back to form first polysilicon sidewalls on the etched side of the third insulating layer; Etching the second insulating layer by applying the third insulating layer and the sidewalls as a mask to expose the plug, and then depositing and etching back the second polysilicon on the upper surface; And a step of sequentially forming a dielectric film and a plate electrode on the upper surface of the resultant. The method of claim 1, wherein the second and third insulating layers are formed of materials having etch selectivity.