KR20010037699A - Capacitor forming method - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to increase capacitance without increasing an etching aspect ratio, by compounding the heights of the third and fourth oxide layers to control the capacitance. CONSTITUTION: The first oxide layer(20), a cell plug(30), a bit line conductive layer(40), a bit line cap(50) and a bit line sidewall(60) are sequentially formed on a semiconductor substrate(10) to form a bit line. The second oxide layer(70), the first nitride layer(80) and the third oxide layer(90) are formed on the resultant structure, and a storage node contact(100) connected to the cell plug is formed. The second nitride layer(110) is deposited on the resultant structure. The fourth oxide layer(120) is deposited on the resultant structure. The fourth oxide layer and the second nitride layer are dry-etched to expose the storage node contact and to form a hole. Polysilicon(130) is deposited on the resultant structure. Spin-on-glass(SOG) is applied to fill the hole, and an etch-back process is performed. The polysilicon exposed by the etch-back process is etched, and the SOG is eliminated. The fourth oxide layer between lower electrode of a capacitor and the second nitride layer under the fourth oxide layer are dry-etched. The exposed third oxide layer is wet-etched to extend the surface area of the lower electrode of the capacitor. A dielectric material(150) and a plate electrode(160) of the capacitor are deposited on the resultant structure.

Description

Capacitor Formation Method {CAPACITOR FORMING METHOD}

The present invention relates to a method of forming a capacitor, and in particular, in the semiconductor memory manufacturing process, it is possible to increase the surface area without increasing the oxide layer that determines the height of the capacitor, thereby increasing the capacity and increasing the capacity of the oxide layer during etching. It relates to a method of forming a capacitor to be suitable.

The conventional capacitor forming method will be described with reference to the procedure cross-sectional view of FIGS. 1A to 1C as follows.

The first oxide film 2, the cell plug 3, the bit line conductive film 4, the bit line cap 5, and the bit line side wall 6 are sequentially formed on the semiconductor substrate 1 on which the MOS transistor is formed. Forming a line, forming a second oxide film 7 thereon, forming a storage node contact 8 to be connected to the self-lug 3, and depositing a nitride film 9 on the structure; Etching prevention film forming process; The third oxide film 10 is deposited on the upper surface of the formed structure, and the third oxide film 10 and the nitride film 9 are dry-etched to expose the storage node contact 8 to form holes, and then the upper part of the structure. A process of forming a capacitor lower electrode to deposit polysilicon (11) on the surface, and to apply spin-on glass (12) thereon to fill the formed holes and then to etch back; After etching the polysilicon 11 exposed by the etch back, the spin-on glass 12 is removed, and the third oxide film 10 between the capacitor lower electrodes exposed in the process is dry-etched and then sequentially removed from the upper surface of the structure. The capacitor upper electrode 14 is formed by depositing the dielectric material 13 and the capacitor upper electrode 14.

First, as illustrated in FIG. 1A, a first oxide film 2 is deposited on the semiconductor substrate 1 on which the MOS transistor is formed, and dry-etched to expose the source / drain region S / D of the formed MOS transistor. After that, polysilicon is deposited and planarized thereon to form a cell plug 3.

The bit line conductive film 4 and the bit line cap 5 are sequentially deposited on the upper surface of the formed structure, and then dry-etched to fit the region where the bit line is to be formed, and the formed bit line conductive film 4, The bit line is formed by forming the bit line side wall 6 using an insulating film on the side of the bit line cap 5 structure.

A second oxide film 7 is formed on the formed structure, and the deposited second oxide film 7 is dry-etched to be connected to the self-lug 3 to form a storage node contact hole, and then, on the structure. Polysilicon is deposited and planarized to form a storage node contact 8, and then a nitride film 9 is deposited on the upper portion and the second oxide layer 7 and used as an etch stop layer. In this case, the structure becomes a memory cell except for a capacitor.

Next, as shown in FIG. 1B, a third oxide film 10 is deposited on the upper surface of the formed structure, and the third oxide film 10 and the nitride film 9 are mounted so that the storage node contact 8 is exposed. After etching to form a hole, polysilicon 11 is deposited on top of the structure, spin-on glass 12 is applied on the top of the structure to fill the formed hole, and then etch back until the polysilicon 11 is exposed. In order to form a capacitor lower electrode, the spin-on glass 12 is over-etched during the etch back process so that the upper portion of the formed hole is not filled.

Next, as shown in FIG. 1C, the polysilicon 11 exposed by the etch back is etched to remove the polysilicon 11 located on the upper portion of the structure until the spin on glass 12 is located. After dry etching the spin-on glass 12, and removing the third oxide film 10 between the capacitor lower electrodes exposed in the process of removing the polysilicon 11, the dielectric material ( 13), the capacitor upper electrode 14 is deposited.

However, the conventional capacitor formation method as described above wastes the portion surrounded by the storage node contact, the capacitor lower electrode, and the bit line cap, and increases the height of the third oxide film to increase the capacitance of the capacitor to increase the height of the capacitor lower electrode. Since the height is used, the aspect ratio increases when the etching is performed, thereby making the subsequent process difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to use a portion surrounded by a storage node contact, a capacitor lower electrode, and a bit line cap to increase the capacity of a capacitor without increasing the third oxide layer. In the case of forming the lower electrode of the capacitor by etching the same, the aspect ratio can be adjusted to provide a capacitor formation method which can increase the capacity of the capacitor in an easy process.

1 is a cross-sectional view showing a conventional capacitor forming method.

Figure 2 is a cross-sectional view showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

10 semiconductor substrate 20 first oxide film

30: cell plug 40: bit line conductive film

50: bit line cap 60: bit line side wall

70 second oxide film 80 first nitride film

90: third oxide film 100: storage node contact

110: second nitride film 120: fourth oxide film

130: polysilicon 140: spin on glass

150: dielectric material 160: capacitor upper electrode

A capacitor forming method for achieving the object of the present invention as described above is to form a bit line by sequentially forming a first oxide film, a cell plug, a bit line conductive film, a bit line cap, and a bit line side wall on a semiconductor substrate on which a MOS transistor is formed. And forming a second oxide film, a first nitride film, and a third oxide film on top of each other, forming a storage node contact so as to be connected to the self-lug, and forming a contact and an etch stop layer to deposit a second nitride film on the structure. Process; After depositing a fourth oxide film on the upper surface of the formed structure, dry etching the fourth oxide film and the second nitride film to expose the storage node contact to form a hole, and then depositing polysilicon on top of the structure, Forming a capacitor lower electrode by applying spin-on glass to fill the formed holes and then to etch back; After etching the polysilicon exposed by the etch back, the spin-on glass is removed, and the fourth oxide film between the capacitor lower electrodes exposed in the process and the second nitride film disposed under the dry etching are removed, and the agent exposed through the process is removed. After the oxide film is wet-etched to extend the surface area of the lower electrode of the capacitor, a capacitor expansion and an upper electrode forming process of depositing a dielectric material and a capacitor upper electrode in sequence on the upper surface of the structure.

Referring to the cross-sectional view of the procedure of Figure 2a to 2c attached to the capacitor forming method according to the present invention as an embodiment in detail as follows.

First, as illustrated in FIG. 2A, the first oxide layer 20 is deposited on the semiconductor substrate 10 on which the MOS transistor is formed, and then dry-etched to expose the source / drain region S / D1 of the formed MOS transistor. Thereafter, polysilicon is deposited and planarized thereon to form a cell plug 30.

The bit line conductive film 40 and the bit line cap 50 are sequentially deposited on the upper surface of the formed structure, and then dry-etched to fit the region where the bit line is to be formed, and the formed bit line conductive film 40, The bit line is formed by forming the bit line side wall 60 using an insulating film on the side of the bit line cap 50 structure.

A second oxide film 70, a first nitride film 80, and a third oxide film 90 are sequentially formed on the formed structure, and the deposited insulating films 90, 80, and 70 are connected to the self-lug 30. ) To form a storage node contact hole by dry etching, and then depositing and planarizing polysilicon on the structure to form a storage node contact 100, and then forming a second nitride layer 110 on the upper portion and the third oxide layer 90. ) Is used as an etching prevention film. In this case, the structure becomes a memory cell except for a capacitor.

Next, as shown in FIG. 2B, a fourth oxide layer 120 is deposited on the upper surface of the formed structure, and the fourth oxide layer 120 and the second nitride layer 110 are exposed to expose the storage node contact 100. Dry etching to form a hole, and then deposit polysilicon 130 on the structure, and apply the spin-on glass 140 on the top of the structure to fill the formed hole until the polysilicon 130 is exposed The back electrode is etched to form a capacitor lower electrode. During the etch back process, the spin-on glass 140 is over-etched so that the upper portion of the formed hole is not filled.

Next, as shown in FIG. 2C, the polysilicon 130 exposed by the etch back is etched to remove the polysilicon 130 located on the upper portion of the structure until the spin on glass 140 is located. Dry etching the spin-on glass 140, and dry etching the fourth oxide film 120 between the capacitor lower electrode and the second nitride film 110 disposed thereunder, which are exposed in the process of removing the polysilicon 130. After removal, the third oxide film 90 exposed through the process is wet-etched to expand the surface area of the capacitor lower electrode, and then deposit dielectric material 150 and capacitor upper electrode 160 on the upper surface of the structure.

As described above, the capacitor forming method according to the present invention uses a portion of the storage node contact, the capacitor lower electrode, and the bit line cap, which are not conventionally used, as the lower electrode to combine the heights of the third oxide film and the fourth oxide film. The capacity can be adjusted so that even when the capacitor capacity is increased, the etching aspect ratio does not increase, thereby facilitating the production of the product and improving the quality.

Claims (1)

The first oxide film, the cell plug, the bit line conductive film, the bit line cap, and the bit line side walls are sequentially formed on the semiconductor substrate on which the MOS transistor is formed, and the second oxide film, the first nitride film, and the first oxide film are sequentially formed thereon. Forming an oxide layer, forming a storage node contact to be connected to the self-lug, and depositing a second nitride layer on the structure; After depositing a fourth oxide film on the upper surface of the formed structure, dry etching the fourth oxide film and the second nitride film to expose the storage node contact to form a hole, and then depositing polysilicon on top of the structure, Forming a capacitor lower electrode by applying spin-on glass to fill the formed holes and then to etch back; After etching the polysilicon exposed by the etch back, the spin-on glass is removed, and the fourth oxide film between the capacitor lower electrodes exposed in the process and the second nitride film disposed under the dry etching are removed, and the agent exposed through the process is removed. 3. The method of forming a capacitor comprising a capacitor expansion and an upper electrode forming process of wetting an oxide film to expand a surface area of a capacitor lower electrode and then depositing a dielectric material and a capacitor upper electrode on the upper surface of the structure.