KR100442783B1 - method for fabricating capacitor - Google Patents

Abstract

The present invention discloses a method of forming a capacitor of a cylindrical structure capable of improving capacitance.

The method of forming a capacitor of the present invention disclosed above provides a semiconductor substrate on which a transistor including a source / drain and a gate is manufactured, and each first opening for covering the transistor on the substrate and exposing the source / drain and the gate. Forming an interlayer insulating film having an interlayer insulating film, filling a first opening, and forming a storage node contact plug and a bit line contact plug made of a silicon layer by epitaxial growth, and covering the storage node contact plug on the interlayer insulating film. Forming a mask having a second opening that exposes the bit line contact plug, forming a bit line filling the second opening, removing the mask, and electrically connecting the storage node contact plug to the interlayer dielectric layer. Forming a conductive film connected to each other, and selectively etching the conductive film And a step of forming a storage node formed on the storage node, the dielectric layer and a plate electrode.

Description

Method for fabricating capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a capacitor having a cylindrical structure capable of improving capacitance.

As is generally known, as the number of memory cells constituting the DRAM semiconductor device has recently increased, the occupied area of each memory cell is gradually decreased. On the other hand, the capacitor formed in each memory cell needs a sufficient capacity for reading the correct stored data. Accordingly, current DRAM semiconductor devices require a memory cell in which a capacitor having a larger capacity while forming a smaller area is formed.

Therefore, in order to increase the capacitance of the capacitor, a TaON film having a high dielectric constant is used as the dielectric film to secure sufficient charge capacity required for the operation of the semiconductor device or to grow a so-called HSG (HemiSpheric Glass) film on the storage node, thereby increasing the electrode surface area. There is a way to increase.

The method of increasing the capacitance by growing the HSG film uses an unusual physical phenomenon in the process of transforming an amorphous silicon film into a polycrystalline silicon film, and deposits amorphous silicon on a substrate and then heats the amorphous silicon film to form a fine hemispherical grain. The grains are formed to make the effective area of the lower electrode wider.

However, there is a problem in that the surface area of a capacitor is increased by using the HSG film in a highly integrated DRAM semiconductor device.

Accordingly, an object of the present invention is to provide a method of forming a capacitor capable of increasing the surface area of a cylindrical storage node by epitaxial growth.

1A to 1F are cross-sectional views illustrating a capacitor formation according to the present invention.

According to one aspect of the present invention, there is provided a method of forming a capacitor, comprising: providing a semiconductor substrate on which a transistor including a source / drain and a gate is fabricated, and covering the transistor on the substrate and exposing the source / drain and gate Forming an interlayer insulating film having a first opening, embedding the first opening, forming a storage node contact plug and a bit line contact plug made of a silicon layer by epitaxial growth, and forming a storage node contact on the interlayer insulating film Forming a mask having a second opening covering the plug and exposing the bit line contact plug, forming a bit line filling the second opening, removing the mask, and storing the storage node on the interlayer dielectric layer. Forming a conductive film electrically connected to the contact plug, and selecting the conductive film That includes the steps of forming a storage node, the dielectric layer and a plate electrode for forming a storage node by etching the features.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a process of forming a capacitor according to the present invention.

In the capacitor forming method of the present invention, as shown in FIG. 1A, the gate 106 is formed on the semiconductor substrate 100 having the field oxide film 102 via the gate insulating film 104. In this case, the first cap insulation layer 108 is formed on the gate 106, and the first insulation spacer 110 is formed on the side surface thereof. In addition, the source / drain 112 and 114 and the lightly doped drain 116 are formed under the substrate on both sides of the gate 106.

Subsequently, after the interlayer insulating layer 122 is deposited on the substrate on which the gate 106 is formed, the interlayer insulating layer 122 is selectively etched to expose the source / drain 112 and 114, respectively. Anisotropic epitaxial or anisotropic polysilicon is filled in to form respective storage node contact plugs 118a and bit line contact plugs. As shown in FIG. 1B, the first silicon nitride film and the first silicon oxide film are sequentially deposited on the resultant, and then the first silicon nitride film and the first silicon oxide film are removed by a photolithography process to remove the bitline contact plug. Masks 150 and 122 having openings 151 to be exposed are formed. Thereafter, as shown in FIG. 1C, a second silicon nitride film is deposited on the mask, and then the second silicon nitride film is deposited. Is etched back to form a second insulating spacer 128 covering the side surface of the opening 151. Next, after depositing a first conductive film such as polycrystalline silicon on the mask including the second insulating spacer 128, the first conductive film is removed by chemical-mechanical polishing or etch back process to connect with the bit line contact plug. Bit line 124 is formed. Subsequently, after depositing a third silicon nitride film to cover the bit line 124 on the mask, the second cap insulation layer remaining on the bit line by removing the silicon nitride film by a chemical-mechanical polishing or etch back process. Forms 128. Next, the mask is removed. Next, as shown in FIG. 1D, the epitaxial layer of the storage node contact plug 118a is used as a seed, and isotropic epi growth and anisotropic epi growth are sequentially performed. 130 is formed. Next, the second silicon oxide layer 132 is formed by performing a thermal process or a low pressure chemical vapor deposition (LPCVD) process on the resultant product on which the silicon layer 130 is formed.

Subsequently, as shown in FIG. 1D, the epitaxial layer of the storage node contact plug 118a is used as a seed to sequentially form isotropic epi growth and anisotropic epi growth to form the silicon layer 130. Next, a second silicon oxide layer 132 is formed by performing a thermal process or a low pressure chemical vapor deposition (LPCVD) process on the resultant product on which the silicon layer 130 is formed. Thereafter, as shown in FIG. 1E. After blanket drying the second silicon oxide layer to expose the center portion of the silicon layer, the center portion of the silicon layer exposed by the second silicon oxide layer is etched by a predetermined thickness. In this case, reference numeral 133 in FIG. 1E illustrates a second silicon oxide film remaining after the blanket dry etching process.

Then, after depositing a third silicon oxide film (not shown) on the resultant, the third silicon oxide film is excessively etched back to the upper surface of the remaining silicon layer 131 and the second silicon oxide film 133 Sidewalls of the third insulating spacer 134 is formed. Thereafter, the silicon layer is etched to a predetermined thickness using the third insulating spacer 134 and the second silicon oxide layer 133 as a mask to form the storage node electrode 131 of the capacitor. In this case, the storage node electrode 131 is left to have a thickness of at least 200 to 500 Å from the surface of the interlayer insulating film 120. Then, as shown in FIG. 1F, the third insulating spacer and the second silicon oxide film are removed. Thereafter, as shown in FIG. 1G, the dielectric layer 136 and the plate electrode 138 are sequentially formed on the storage node 131 to complete the manufacturing of the cylindrical capacitor.

As described above, in the present invention, the surface area of the cylindrical storage node is increased by epitaxial growth.

Therefore, there is an advantage in that the capacitance of the capacitor is improved with the increase of the surface area of the storage node.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

Providing a semiconductor substrate on which a transistor including a source / drain and a gate is manufactured; Depositing an interlayer insulating film over the entire surface of the substrate, and selectively etching the interlayer insulating film to form respective first openings for exposing the source / drain and the gate; Filling each of the first openings by a selective epitaxial growth method to form a storage node contact plug and a bit line contact plug; Forming a mask covering the storage node contact plug on the resultant, the mask having a second opening for exposing the bit line contact plug; Embedding the second opening to form a bit line; Removing the mask; Forming an silicon layer by successively isotropic and anisotropic epi growth on the resultant interlayer insulating film with the seed of the storage node contact plug as a seed; Partially etching the inside of the silicon layer to form a storage node electrode of the capacitor; and And forming a dielectric layer and a plate electrode sequentially on the storage node electrode. delete delete The method of claim 1, wherein after forming the silicon layer, Forming a silicon oxide film on the resultant formed silicon layer; A blanket dry etching of the silicon oxide layer, and then etching the silicon layer to a predetermined thickness; Forming an insulating spacer having a sidewall shape on an upper surface of the remaining silicon layer and a side surface of the remaining silicon oxide film; Etching the silicon layer using the insulating spacer as a mask to form a storage node electrode of a capacitor; and And removing the insulating spacers and the remaining silicon oxide film. The method of claim 1, wherein the storage node electrode has a thickness of 200 to 500 Å from the surface of the interlayer dielectric layer.