KR20010068611A - Capacitor forming method - Google Patents

Abstract

PURPOSE: A forming method of a capacitor is provided to simplify processes by decreasing polysilicon forming processes into one time, and reduce process period and manufacturing costs and enable high integrity by forming node contacts preventing short-circuit with lower wiring. CONSTITUTION: In the first step, the first interlayer insulating layer(22) is formed on a semiconductor substrate(21), then a second interlayer insulating layer(24) and a conductive layer are sequentially deposited, bit lines(25) are formed by patterning the conductive layer, and then the first nitride layer(26), the third interlayer insulating layer(27) and the second nitride layer(28) are sequentially deposited. In the second step, node contact holes are formed by etching the second nitride layer(28), the third interlayer insulating layer(27), the first nitride layer(26) and the second interlayer insulating layer(24), and then an oxide(29) is deposited. In the third step, polysilicon(30) is formed on the oxide and the second nitride layer and an insulating layer is formed and then the polysilicon is exposed by etch-back. In the fourth step, the residual insulating layer and oxide are removed by wet etching.

Description

Capacitor Formation Method {CAPACITOR FORMING METHOD}

The present invention relates to a method for forming a capacitor, and in particular, to form a highly integrated memory device, it is possible to form a contact finer than the limit resolution of an exposure apparatus without using a polysilicon hard mask and a poly side wall, as well as insulation with a lower wiring. And a capacitor forming method suitable for simplifying the process.

An embodiment of the conventional capacitor forming method will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1C.

First, as shown in FIG. 1A, a first interlayer insulating film 2 is deposited on a semiconductor substrate 1 on which an element is formed, and a poly plug 3 is formed to be connected to a specific portion of the element. The second interlayer insulating film 4 and the conductive film are sequentially deposited, and the conductive film is patterned to form the bit line 5, and then the first nitride film 6 and the third interlayer insulating film 7 are sequentially deposited on the upper surface of the structure. do.

Next, as shown in FIG. 1B, the first polysilicon 8 is formed on the second interlayer insulating film 7 and etched by a photolithography process in accordance with the region where the polyplug 3 is formed.

In addition, a second polysilicon 9 is formed on the structure and etched back to form sidewalls on the etched side of the first polysilicon 8 and then connected to the polyplug 3 with a hard mask. The third interlayer insulating film 7, the first nitride film 6, and the second interlayer insulating film 4 are etched to form contact holes.

Subsequently, as shown in FIG. 1C, the formed contact hole is filled with a conductive material, and the first polysilicon 8 and the second polysilicon 9 are etched back to expose the third interlayer insulating film 7. ), The node contact 10 is formed, the second nitride film 11 is deposited on the upper surface thereof, and the oxide film 12 is formed high on the upper surface of the node contact 10.

Next, as illustrated in FIG. 1D, the oxide layer 12 and the second nitride layer 11 are sequentially etched so that the node contact 10 is exposed to the position where the capacitor is to be formed, and the third polysilicon is formed on the upper surface of the structure. After forming (13), the insulating film 14 is formed high on the upper portion thereof, and etched back so that the third polysilicon 13 is exposed.

Next, as shown in FIG. 1E, the third polysilicon 13 exposed by the above process is etched, and the remaining oxide film 12 and the insulating film 14 are removed by wet etching.

Polysilicon must be deposited four times to form a capacitor lower electrode by the above process.

Conventional capacitor formation method as described above is a patterning method using a DUV (Deep Ultra Violet) exposure source to implement a semiconductor device of 0.2 ~ 0.15㎛ design rule to maintain a uniform size in the implementation of a micro pattern below 0.25㎛ The use of I-line exposure sources and the use of hard masks and sidewalls to eliminate difficult and expensive equipment is a cause of increasing process time and manufacturing costs.

In addition, a method using an oxide film as a sidewall and a self-aligning method using a nitride film have been introduced to prevent a short circuit between the node contact and the lower interconnection, but there is a problem in terms of productivity and manufacturing cost because of the additional process.

The present invention was devised to solve the conventional problems as described above, and the object of the present invention is to simplify the process by reducing the polysilicon formation to four times of the prior art, as well as to simplify the process, rather than the limit resolution of the exposure equipment. The present invention provides a method of forming a capacitor capable of reducing process time and manufacturing cost and forming a highly integrated node by forming a node contact that can prevent a short circuit with a lower wiring.

1 is a cross-sectional view showing a conventional capacitor forming method.

Figure 2 is a cross-sectional view of the procedure of an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

21 semiconductor substrate 22 first interlayer insulating film

23 poly plug 24 second interlayer insulating film

25 bit line 26 first nitride film

27: third interlayer insulating film 28: second nitride film

29: oxide film 30: polysilicon

31: insulating film

A capacitor forming method for achieving the object of the present invention as described above is to deposit a first interlayer insulating film on the semiconductor substrate on which the device is formed, and to form a polyplug to be connected to a specific part of the device, and then sequentially A first step of depositing a two-layer insulating film and a conductive film, patterning the conductive film to form a bit line, and then depositing a first nitride film, a third interlayer insulating film, and a second nitride film on the entire upper surface of the structure; Forming a node contact hole by etching the second nitride film, the third interlayer insulating film, the first nitride film, and the second interlayer insulating film through a photolithography process so that the formed polyplug is exposed, and forming an oxide film thereon. 2 step; A portion of the formed oxide film and the second nitride film are etched and patterned in accordance with the position at which the capacitor is to be formed to expose the polyplug, and then polysilicon is formed on the upper surface thereof, and an insulating film is formed thereon. A third step of etching back to reveal the polysilicon; And a fourth step of removing the remaining insulating film and the oxide film by wet etching.

The method of forming a capacitor according to the present invention as described above will be described in detail with reference to a procedure cross-sectional view shown in FIGS. 2A to 2D as an embodiment.

First, as shown in FIG. 2A, a first interlayer insulating film 22 is deposited on the semiconductor substrate 21 on which the device is formed, and a polyplug 23 is formed to be connected to a specific portion of the device.

The second interlayer insulating film 24 and the conductive film are sequentially deposited on the upper surface of the polyplug 23, the conductive film is patterned to form a bit line 25, and the first nitride film 26 is sequentially formed on the upper surface of the structure. ), The third interlayer insulating film 27 and the second nitride film 28 are deposited.

Next, as shown in FIG. 2B, the second nitride film 28, the third interlayer insulating film 27, the first nitride film 26, and the first nitride film are exposed through a photolithography process so that the formed polyplug 23 is exposed. The interlayer insulating film 24 is etched to form a node contact hole, and an oxide film 29 is deposited on the upper portion.

At this time, since the etching is dull by the first nitride layer 26 in the photolithography process for forming the contact hole, the lower second interlayer insulating layer 24 is patterned to be 0.05 μm small.

In addition, the oxide layer 29 is formed by plasma enhanced chemical vapor deposition, and voids are formed in the previously formed node contact holes due to the limitation of step coverage, which is performed in a subsequent process. This is to facilitate etching because the poly plug 23 is exposed by etching again the node contact hole blocked by).

Next, as shown in FIG. 2C, the polyplug 23 is exposed while etching and patterning a portion of the formed oxide film 29 and the second nitride film 28 according to the position where the capacitor is to be formed.

At this time, after adjusting the etch rate of the oxide film 29 and the second nitride film 28 to pattern the oxide film 29 in accordance with the position where the capacitor lower electrode is to be formed, while suppressing the etching of the exposed second nitride film 28. The oxide layer 29 remaining inside the contact hole is etched to expose the poly plug 23 to form sidewalls of the oxide layer 29 on the side of the node contact hole.

Then, the polysilicon 30 is formed on the upper surface of the structure, the insulating film 31 is formed on the upper portion and then etched back so that the polysilicon 30 is exposed.

Then, as shown in FIG. 2D, the remaining insulating film 31 and the oxide film 29 are removed by wet etching.

Only one polysilicon deposition is required to form the capacitor lower electrode in the process of the embodiment of the present invention described above.

As described above, the capacitor forming method of the present invention enables the formation of fine contact holes using an I-line exposure machine, which is a low-cost device, but also simplifies the process by reducing the number of polysilicon formations up to four times, as well as node contact and By preventing the short circuit with the lower wiring there is an effect that can reduce the process time and manufacturing cost and increase the degree of integration.

Claims (3)

A first interlayer insulating film is deposited on the semiconductor substrate on which the device is formed, a polyplug is formed so as to be connected to a specific portion of the device, and then a second interlayer insulating film and a conductive film are deposited on the upper surface thereof in turn, and the bit line is patterned by patterning the conductive film. Forming a first nitride film, a third interlayer insulating film, and a second nitride film on the upper surface of the structure; Forming a node contact hole by etching the second nitride film, the third interlayer insulating film, the first nitride film, and the second interlayer insulating film through a photolithography process so that the formed polyplug is exposed, and forming an oxide film thereon. 2 step; A portion of the formed oxide film and the second nitride film are etched and patterned in accordance with the position where the capacitor is to be formed to expose the polyplug, and then polysilicon is formed on the upper surface thereof, and an insulating film is formed thereon. A third step of etching back so that the silicon is exposed; And a fourth step of removing the remaining insulating film and the oxide film by wet etching. The method of claim 1, wherein the oxide film is deposited by plasma chemical vapor deposition in the second step, and the void is formed in the previously formed node contact hole due to the step coverage limit of the oxide film. The polyplug of claim 1, wherein after adjusting the etch rate of the oxide film and the second nitride film in the third process to pattern the oxide film according to a position where a capacitor lower electrode is to be formed, the polyplug is suppressed while the etching of the exposed second nitride film is suppressed. And etching the oxide film remaining inside the contact hole so that the oxide film sidewall is formed on the side of the node contact hole.