KR100568395B1 - Method of fabricating semiconductor device using metal contact plug - Google Patents

Method of fabricating semiconductor device using metal contact plug

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Publication number
KR100568395B1
KR100568395B1 KR1020030043084A KR20030043084A KR100568395B1 KR 100568395 B1 KR100568395 B1 KR 100568395B1 KR 1020030043084 A KR1020030043084 A KR 1020030043084A KR 20030043084 A KR20030043084 A KR 20030043084A KR 100568395 B1 KR100568395 B1 KR 100568395B1
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KR
South Korea
Prior art keywords
forming
metal contact
hole
storage node
layer
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KR1020030043084A
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Korean (ko)
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KR20050002038A (en
Inventor
김근태
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주식회사 하이닉스반도체
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Priority to KR1020030043084A priority Critical patent/KR100568395B1/en
Publication of KR20050002038A publication Critical patent/KR20050002038A/en
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Publication of KR100568395B1 publication Critical patent/KR100568395B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

본 발명은 반도체기판상에 절연층을 형성하는 단계와, 제1영역의 상기 절연층을 선택적으로 식각하여 반도체기판의 소정영역을 노출시키는 제1금속콘택홀을 형성하는 단계, 상기 제1금속콘택홀 내부에 금속콘택플러그를 형성하는 단계, 제2영역의 상기 절연층을 선택적으로 식각하여 커패시터 스토리지노드 형성용 홀을 형성하는 단계, 상기 스토리지노드 형성용 홀의 내부에 스토리지노드용 도전층과 유전체막을 형성하는 단계, 상기 스토리지노드 형성용 홀의 내부를 포함하는 상기 유전체막 상에 플레이트전극용 도전층을 형성하는 단계, 기판 전면에 층간절연막을 형성하는 단계, 상기 층간절연막을 선택적으로 제거하여 상기 금속콘택플러그가 드러나는 제2금속콘택홀을 형성하는 단계, 상기 제2금속콘택홀을 포함한 기판 전면에 배선용 금속층을 형성하는 단계를 포함하여 구성되는 반도체소자 제조 방법에 관한 것이다.The present invention provides a method of forming an insulating layer on a semiconductor substrate, selectively etching the insulating layer of a first region, and forming a first metal contact hole exposing a predetermined region of the semiconductor substrate. Forming a metal contact plug in the hole, selectively etching the insulating layer in the second region to form a capacitor storage node forming hole, and forming a storage node conductive layer and a dielectric layer in the storage node forming hole Forming a plate electrode conductive layer on the dielectric film including the inside of the hole for forming the storage node; forming an interlayer insulating film on the entire surface of the substrate; and selectively removing the interlayer insulating film to remove the metal contact. Forming a second metal contact hole in which the plug is exposed; and a wiring metal layer on an entire surface of the substrate including the second metal contact hole Which comprises forming to a semiconductor device manufacturing method.

금속 콘택, 플러그, 텅스텐, 애스펙트비, 커패시터, 콘택홀Metal Contacts, Plugs, Tungsten, Aspect Ratio, Capacitors, Contact Holes

Description

금속 콘택 플러그를 이용하는 반도체소자 제조방법{Method of fabricating semiconductor device using metal contact plug} Method of fabricating semiconductor device using metal contact plug {Method of fabricating semiconductor device using metal contact plug}             

도1a 내지 도1l은 본 발명에 의한 반도체소자의 금속 콘택 플러그 형성방법을 도시한 공정순서도.1A to 1L are process flowcharts showing a metal contact plug forming method of a semiconductor device according to the present invention;

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 식각저지층 2 : PSG1: etch stop layer 2: PSG

3 : PE-TEOS 4 : 금속콘택 형성용 마스크패턴3: PE-TEOS 4: Mask pattern for forming metal contact

5 : 제1금속콘택홀 6,17 : 배리어금속5: first metal contact hole 6,17: barrier metal

7 : 금속콘택 플러그 8 : 스토리지노드용 홀 형성용 마스크패턴7: metal contact plug 8: mask pattern for hole formation for a storage node

10 : 스토리지노드 11 : 유전체막10: storage node 11: dielectric film

12 :감광막 13 : 플레이트전극 형성용 도전층12 photosensitive film 13: conductive layer for forming plate electrode

14 : 플레이트전극 형성용 마스크패턴14: mask pattern for forming plate electrode

15 : 층간절연막 16 : 금속콘택 형성용 마스크패턴15: interlayer insulating film 16: mask pattern for forming a metal contact

18 : 배선용 금속층18: metal layer for wiring

본 발명은 반도체 제조공정에 관한 것으로, 특히 금속 콘택 플러그를 사용하는 반도체소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing process, and more particularly to a method of manufacturing a semiconductor device using a metal contact plug.

반도체 메모리소자의 집적도가 높아짐에 따라 커패시터는 홀 내부의 면적을 이용하는 오목한 형태(concave type)로 개발되고 있다. 오목한 형태의 커패시터의 경우에도 소자가 고집적화됨에 따라 홀의 크기는 계속 작아지고 있으며, 이에 따라 적정한 값의 전하 저장면적을 확보하기 위하여 커패시터의 높이는 계속 증가되고 있다. 이로 인해 애스펙트비도 계속해서 커지고 있는 실정이다. 애스펙트비가 높은 커패시터 스토리지노드용 홀을 사용할 경우에는 토폴로지의 증가로 인해 필연적으로 후속공정인 금속콘택의 높이가 증가되어 금속 콘택홀이 오픈되고 콘택홀 매립을 위한 공정마진 확보가 어렵게 된다.As the degree of integration of semiconductor memory devices increases, capacitors have been developed in a concave type using an area inside a hole. Even in the case of concave capacitors, as the device is highly integrated, the size of the hole continues to decrease, and accordingly, the height of the capacitor continues to increase in order to secure a proper charge storage area. As a result, aspect ratio is continuously increasing. When using a hole for a capacitor storage node having a high aspect ratio, the height of the topology inevitably increases the height of the subsequent metal contact, so that the metal contact hole is opened and it is difficult to secure a process margin for filling the contact hole.

본 발명은 상기 문제점을 해결하기 위한 것으로써, 비트라인 상부에 텅스텐(W)을 사용하여 금속콘택 플러그를 미리 형성한 후, 커패시터를 형성함으로써 커패시터 높이 증가에 따른 금속콘택 공정에서의 콘택홀 형성 및 갭 매립공정의 부담을 최소화하여 안정적이고 재현성있는 금속콘택을 형성하는 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, after forming a metal contact plug using a tungsten (W) on the bit line in advance, by forming a capacitor to form a contact hole in the metal contact process according to the increase in the height of the capacitor and It is an object of the present invention to provide a method for forming a stable and reproducible metal contact by minimizing the burden of the gap filling process.

상기 목적을 달성하기 위한 본 발명은, 제1 및 제2영역으로 정의되는 반도체기판상에 절연층을 형성하는 단계와, 상기 제1영역의 상기 절연층을 선택적으로 식각하여 반도체기판의 소정영역을 노출시키는 제1금속콘택홀을 형성하는 단계와, 상기 제1금속콘택홀이 매립되도록 텅스텐으로 금속콘택 플러그용 도전층을 형성하는 단계와, 상기 제2영역의 상기 금속 콘택 플러그용 도전층을 선택적으로 식각하고, 상기 도전층을 하드마스크로 사용하여 상기 절연층을 식각하여 커패시터 스토리지노드 형성용 홀과 상기 금속콘택홀 내부의 금속콘택플러그를 형성하는 단계와, 상기 스토리지노드 형성용 홀의 내부에 스토리지노드용 도전층과 유전체막을 형성하는 단계와, 상기 스토리지노드 형성용 홀의 내부를 포함하는 상기 유전체막 상에 플레이트전극용 도전층을 형성하는 단계상기 기판 전면에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 제거하여 상기 금속콘택플러그가 드러나는 제2금속콘택홀을 형성하는 단계와, 상기 제2금속콘택홀을 포함한 상기 기판 전면에 배선용 금속층을 형성하는 단계를 포함하는 반도체소자 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming an insulating layer on a semiconductor substrate defined by first and second regions, and selectively etching the insulating layer of the first region to form a predetermined region of the semiconductor substrate. Forming a first metal contact hole for exposing, forming a conductive layer for metal contact plug with tungsten so as to fill the first metal contact hole, and selectively selecting the conductive layer for metal contact plug in the second region Etching the insulating layer using the conductive layer as a hard mask to form a capacitor storage node forming hole and a metal contact plug inside the metal contact hole, and storing the inside of the storage node forming hole. Forming a conductive layer for the node and a dielectric film; and forming a plate electrode on the dielectric film including an inside of the storage node forming hole. Forming a conductive layer on the entire surface of the substrate; selectively removing the interlayer insulating layer to form a second metal contact hole in which the metal contact plug is exposed; and forming the second metal contact hole. It provides a method of manufacturing a semiconductor device comprising the step of forming a metal layer for wiring on the entire surface including the.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도1에 본 발명에 의한 반도체소자 제조방법을 공정순서에 따라 단면도로 나타내었다. 커패시터 형성공정 이전공정은 그 설명을 생략하기로 한다.1 is a cross-sectional view of a method of manufacturing a semiconductor device according to the present invention in accordance with the process sequence. The process before the capacitor forming process will be omitted.

먼저, 도1a를 참조하면, 소정의 하부구조가 형성된 반도체기판상에 절연층으로서 질화막 식각저지층(1)과 PSG(2) 및 PE-TEOS(3)를 차례로 증착한 후, 감광막을 사용하여 반도체기판의 주변회로지역에 금속콘택 플러그 형성용 마스크패턴(4)을 형성한다.First, referring to FIG. 1A, a nitride etch stop layer 1, a PSG 2, and a PE-TEOS 3 are sequentially deposited as an insulating layer on a semiconductor substrate on which a predetermined substructure is formed, and then using a photosensitive film. A mask pattern 4 for forming a metal contact plug is formed in the peripheral circuit region of the semiconductor substrate.

이어서 도1b에 나타낸 바와 같이 상기 마스크패턴을 이용하여 PE-TEOS, PSG 및 질화막을 차례로 식각하고, 그에 따라 노출되는 소정의 하부구조를 식각하여 금속콘택홀(5)을 형성한 다음, 마스크패턴을 제거한다.Subsequently, as shown in FIG. 1B, the PE-TEOS, PSG, and nitride layers are sequentially etched using the mask pattern, and a predetermined substructure exposed thereto is etched to form a metal contact hole 5. Remove

다음에 도1c에 나타낸 바와 같이 상기 금속콘택홀(5)을 포함한 기판 전면에 배리어 금속(6)을 증착하고 이어서 플러그 형성용 도전물질로서 예컨대 텅스텐(7)을 상기 금속콘택홀(5)이 매립되도록 증착한다.Next, as shown in FIG. 1C, a barrier metal 6 is deposited on the entire surface of the substrate including the metal contact hole 5, and then, for example, tungsten 7 is embedded as a conductive material for forming a plug, and the metal contact hole 5 is embedded. To be deposited.

이어서 도1d에 나타낸 바와 같이 감광막을 사용하여 스토리지노드 형성을 위한 마스크패턴(8)을 형성한 후, 이 마스크패턴을 이용하여 도1e에 나타낸 바와 같이 텅스텐을 선택적으로 식각하고 마스크패턴을 제거한 다음, 텅스텐을 하드마스크로 사용하여 그 하부의 PE-TEOS 및 PSG와 질화막을 선택적으로 식각하여 스토리지노드용 홀을 형성한다. 이때, 하드마스크로 사용된 일정두께의 텅스텐은 손실되어, 금속콘택홀 내부에만 금속콘택플러그인 텅스텐(7)이 잔류된다.Subsequently, as shown in FIG. 1D, a mask pattern 8 for forming a storage node is formed by using a photoresist film. Then, by using this mask pattern, tungsten is selectively etched as shown in FIG. 1E and the mask pattern is removed. Tungsten is used as a hard mask to selectively etch the PE-TEOS, PSG and nitride film underneath to form holes for the storage node. At this time, the tungsten having a predetermined thickness used as the hard mask is lost, and the tungsten 7, which is the metal contact plug, remains only inside the metal contact hole.

다음에 도1f에 나타낸 바와 같이 스토리지노드 형성용 도전물질로서 예컨대 폴리실리콘(10)을 증착하고 그위에 유전체막(11)을 증착한다.Next, as shown in FIG. 1F, for example, polysilicon 10 is deposited as a conductive material for forming a storage node, and a dielectric film 11 is deposited thereon.

이어서 도1g에 나타낸 바와 같이 감광막(12)을 상기 스토리지노드용 홀이 매립되도록 도포한 후, 홀 상부의 폴리실리콘과 유전체막을 선택적으로 제거한다.Subsequently, as shown in FIG. 1G, the photosensitive film 12 is coated so that the holes for the storage node are embedded, and then the polysilicon and the dielectric film on the upper portion of the hole are selectively removed.

다음에 도1h에 나타낸 바와 같이 상기 감광막을 제거한 후, 커패시터 플레이트전극 형성용 물질로서 예컨대 폴리실리콘(13)을 기판 전면에 증착한다.Next, as shown in FIG. 1H, the photosensitive film is removed, and then, for example, polysilicon 13 is deposited on the entire surface of the substrate as a material for forming a capacitor plate electrode.

이어서 도1i에 나타낸 바와 같이 감광막을 사용하여 플레이트전극 패터닝을 위한 마스크패턴(14)을 형성한 후, 도1j에 나타낸 바와 같이 상기 마스크패턴(14)을 사용하여 폴리실리콘층(13)을 선택적으로 식각하여 커패시터 플레이트전극을 형성한다.Subsequently, as shown in FIG. 1I, a mask pattern 14 for plate electrode patterning is formed using a photosensitive film, and then, as shown in FIG. 1J, the polysilicon layer 13 is selectively selected using the mask pattern 14 as shown in FIG. Etching forms a capacitor plate electrode.

다음에 도1k에 나타낸 바와 같이 감광막패턴을 제거한 후, 층간절연막(15)을 기판 전면에 형성한 다음, 감광막을 사용하여 금속콘택 형성용 마스크패턴(16)을 형성한다.Next, as shown in Fig. 1K, after removing the photoresist pattern, an interlayer insulating film 15 is formed over the entire surface of the substrate, and then the mask pattern 16 for forming a metal contact is formed using the photoresist.

이어서 도1l에 나타낸 바와 같이 상기 마스크패턴을 이용하여 상기 층간절연막을 선택적으로 제거하여 금속콘택홀을 형성한 후, 감광막패턴을 제거한다. 이어서 금속콘택홀을 포함한 기판 전면에 배리어금속(17)을 증착하고 배선용 금속층으로서 예컨대 텅스텐을 상기 금속콘택홀이 매립되도록 증착한 후, 에치백공정을 진행하여 금속 배선(18)을 완료한다.Subsequently, as shown in FIG. 1L, the interlayer insulating film is selectively removed using the mask pattern to form a metal contact hole, and then the photoresist pattern is removed. Subsequently, the barrier metal 17 is deposited on the entire surface of the substrate including the metal contact hole, and for example, tungsten is deposited as a metal layer for wiring so that the metal contact hole is embedded, and then the etch back process is performed to complete the metal wiring 18.

상술한 본 발명의 공정에 있어서, 금속콘택홀 형성시 이미 증착해 놓은 금속콘택 플러그(7)를 사용하므로 금속콘택홀의 높이 증가에 따른 높은 애스펙트비를 갖는 콘택홀 형성 및 갭 매립공정의 부담을 최소화하여 안정적이고 재현성있는 금속 콘택 형성이 가능하게 된다. In the above-described process of the present invention, the metal contact plugs 7 already deposited are used to form the metal contact holes, thereby minimizing the burden of contact hole formation and gap filling processes having a high aspect ratio as the height of the metal contact holes increases. This enables stable and reproducible metal contact formation.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 비트라인 상부에 금속콘택 플러그를 형성하여 금속콘택홀 깊이를 최소화함으로써 안정적이고 재현성있는 금속콘택 형성을 가능하게 한다. 이에 따라 본 발명은 초고집적 반도체소자의 미세패턴에도 적용될 수 있다.The present invention forms a metal contact plug on the bit line to minimize the depth of the metal contact hole, thereby enabling stable and reproducible metal contact formation. Accordingly, the present invention can be applied to the fine pattern of the ultra-high density semiconductor device.

Claims (2)

제1 및 제2영역으로 정의되는 반도체기판상에 절연층을 형성하는 단계;Forming an insulating layer on the semiconductor substrate defined by the first and second regions; 상기 제1영역의 상기 절연층을 선택적으로 식각하여 반도체기판의 소정영역을 노출시키는 제1금속콘택홀을 형성하는 단계;Selectively etching the insulating layer of the first region to form a first metal contact hole exposing a predetermined region of the semiconductor substrate; 상기 제1금속콘택홀이 매립되도록 텅스텐으로 금속콘택 플러그용 도전층을 형성하는 단계;Forming a conductive layer for a metal contact plug from tungsten to fill the first metal contact hole; 상기 제2영역의 상기 금속 콘택 플러그용 도전층을 선택적으로 식각하고, 상기 도전층을 하드마스크로 사용하여 상기 절연층을 식각하여 커패시터 스토리지노드 형성용 홀과 상기 금속콘택홀 내부의 금속콘택플러그를 형성하는 단계;Selectively etching the conductive layer for the metal contact plug in the second region, and etching the insulating layer using the conductive layer as a hard mask to form a hole for forming a capacitor storage node and a metal contact plug inside the metal contact hole. Forming; 상기 스토리지노드 형성용 홀의 내부에 스토리지노드용 도전층과 유전체막을 형성하는 단계;Forming a storage node conductive layer and a dielectric layer in the storage node forming hole; 상기 스토리지노드 형성용 홀의 내부를 포함하는 상기 유전체막 상에 플레이트전극용 도전층을 형성하는 단계;Forming a conductive layer for a plate electrode on the dielectric layer including the inside of the hole for forming the storage node; 상기 기판 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate; 상기 층간절연막을 선택적으로 제거하여 상기 금속콘택플러그가 드러나는 제2금속콘택홀을 형성하는 단계; 및Selectively removing the interlayer insulating layer to form a second metal contact hole through which the metal contact plug is exposed; And 상기 제2금속콘택홀을 포함한 상기 기판 전면에 배선용 금속층을 형성하는 단계Forming a wiring metal layer on an entire surface of the substrate including the second metal contact hole; 를 포함하는 반도체소자 제조 방법.Semiconductor device manufacturing method comprising a. 삭제delete
KR1020030043084A 2003-06-30 2003-06-30 Method of fabricating semiconductor device using metal contact plug KR100568395B1 (en)

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