KR20000003497A - Electric charge storing electrode forming method of semiconductor memory device - Google Patents

Electric charge storing electrode forming method of semiconductor memory device Download PDF

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Publication number
KR20000003497A
KR20000003497A KR1019980024739A KR19980024739A KR20000003497A KR 20000003497 A KR20000003497 A KR 20000003497A KR 1019980024739 A KR1019980024739 A KR 1019980024739A KR 19980024739 A KR19980024739 A KR 19980024739A KR 20000003497 A KR20000003497 A KR 20000003497A
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South Korea
Prior art keywords
forming
charge storage
storage electrode
insulating film
etching
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KR1019980024739A
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Korean (ko)
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정의삼
김영서
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김영환
현대전자산업 주식회사
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Priority to KR1019980024739A priority Critical patent/KR20000003497A/en
Publication of KR20000003497A publication Critical patent/KR20000003497A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

PURPOSE: An electric charge storing electrode forming method is provided to have the sufficient electric charge storing value while maintaining the existing process as it is. CONSTITUTION: The electric charge storing electrode forming method of a semiconductor memory device comprises the steps of: forming conduction layer patterns having the fine interval on the upper area of a semiconductor substrate(1); forming an insulating film(2) on the conduction layer pattern; forming a photo sensitive film pattern(5) for forming the electric charge storing electrode contact on the insulating film(2); remaining the insulating film(2) on the center of the electric charge storing electrode contact field; eliminating the photo sensitive film pattern(5); forming a conduction layer on the whole surface of the substrate(1) including the electric charge storing electrode contact field; and forming an electric charge storing electrode by patterning the conduction layer as a specific pattern.

Description

반도체 기억소자의 전하저장전극 형성방법Method for forming charge storage electrode of semiconductor memory device

본 발명은 반도체 기억소자의 전하저장전극 형성방법에 관한 것으로, 특히 기존공정을 그대로 유지하면서 충분한 전하저장값을 확보할 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor memory device, and more particularly, to a method for securing a sufficient charge storage value while maintaining an existing process.

종래기술에 의한 반도체 기억소자의 전하저장전극 형성방법을 도 1a 내지 도 1c를 참조하여 다음에 설명한다.A charge storage electrode forming method of a semiconductor memory device according to the prior art will be described next with reference to FIGS. 1A to 1C.

먼저, 도 1a를 참조하면, 실리콘기판(1)상에 1차산화막(2)을 형성하고, 그 상부에 비트라인(3)을 형성한 후, 기판 전면에 2차산화막(4)을 형성한 다음, 전하저장전극 콘택 마스크(5)를 형성한다. 이때, 2차산화막(4) 형성시 하부구조(비트라인)의 간격이 좁을 경우 산화막에 보이드(void)가 발생하기 쉬운데, 이를 해결하기 위해서는 HDP산화막을 적용하는등 새로운 공정을 도입하거나 CMP등의 신규장비가 필요하다.First, referring to FIG. 1A, a primary oxide film 2 is formed on a silicon substrate 1, a bit line 3 is formed thereon, and a secondary oxide film 4 is formed on the entire surface of the substrate. Next, the charge storage electrode contact mask 5 is formed. In this case, when the gap between the lower structures (bit lines) is narrow when forming the secondary oxide film 4, voids are likely to occur in the oxide film. To solve this problem, a new process such as applying an HDP oxide film or introducing a new process such as CMP New equipment is needed.

이어서 도 1b에 나타낸 바와 같이 상기 전하저장전극 콘택 마스크(5)를 이용하여 상기 제2산화막(4) 및 제1산화막(2)을 식각하여 전하저장전극 콘택을 형성한 후, 마스크를 제거하고, 전하저장전극 형성용 폴리실리콘(7)을 증착한 다음, 감광막을 사용하여 전하저장전극 마스크패턴(6)을 형성한다.Subsequently, as shown in FIG. 1B, the second oxide film 4 and the first oxide film 2 are etched using the charge storage electrode contact mask 5 to form a charge storage electrode contact, and then the mask is removed. After the polysilicon 7 for forming the charge storage electrode is deposited, the charge storage electrode mask pattern 6 is formed using a photosensitive film.

다음에 도 1c에 나타낸 바와 같이 상기 마스크패턴(6)을 이용하여 상기 폴리실리콘층(7)을 식각하여 전자저장전극을 형성한 후, 마스크패턴을 제거한다.Next, as shown in FIG. 1C, the polysilicon layer 7 is etched using the mask pattern 6 to form an electron storage electrode, and then the mask pattern is removed.

상술한 종래기술에 의한 전자저장전극 형성방법에 따르면 소자의 고집적화에 따라 요구되는 전하저장값을 만족시키기 어려우며 이를 해결하기 위해서는 실린더 및 핀구조등 다양한 방법을 고려해야 한다.According to the above-described method for forming an electron storage electrode according to the prior art, it is difficult to satisfy the charge storage value required by the high integration of the device, and to solve this, various methods such as a cylinder and a fin structure must be considered.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 고집적 반도체 기억소자에 요구되는 전하저장값을 충족시키기 위하여 산화막을 높게 증착하여 증착시 발생되는 계면의 보이드에 식각시 발생되는 폴리머가 증착되는 원리를 이용하여 산화막 타워를 형성함으로써 충분한 전자저장값을 확보할 수 있는 방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention solves the above problems, and utilizes the principle that the polymer generated during etching is deposited on the void of the interface generated during deposition by depositing a high oxide film to satisfy the charge storage value required for the highly integrated semiconductor memory device. It is an object of the present invention to provide a method for securing a sufficient electron storage value by forming an oxide film tower.

도 1a 내지 도 1c는 종래기술에 의한 반도체 기억소자의 전하저장전극 형성방법을 도시한 공정순서도,1A to 1C are process flowcharts showing a charge storage electrode forming method of a semiconductor memory device according to the prior art;

도 2a 내지 도 2e는 본 발명에 의한 반도체 기억소자의 전하저장전극 형성방법을 도시한 공정순서도,2A to 2E are process flowcharts showing a method of forming a charge storage electrode of a semiconductor memory device according to the present invention;

도 3은 산화막 식각도중 발생한 폴리머에 의해 산화막타워가 형성된 상태를 도시한 단면도.3 is a cross-sectional view illustrating a state in which an oxide film tower is formed by a polymer generated during oxide etching.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체기판 2 : 1차절연막1: semiconductor substrate 2: primary insulating film

3 : 비트라인 4 : 2차절연막3: bit line 4: secondary insulating film

5 : 전하저장전극 콘택형성용 감광막패턴5: photosensitive film pattern for forming a charge storage electrode contact

10 : 절연막타워 11 : 전하저장전극10: insulating film tower 11: charge storage electrode

12 : 전하저장전극 형성용 감광막패턴12: Photosensitive film pattern for forming charge storage electrode

20 : 폴리머20 polymer

상기 목적을 달성하기 위한 본 발명에 따른 반도체 기억소자의 전하저장전극 형성방법은 반도체기판상부에 미세한 간격을 갖는 도전층패턴들을 형성하는 단계와, 상기 도전층패턴상에 절연막을 형성하는 단계, 상기 절연막상에 전하저장전극 콘택형성용 감광막패턴을 형성하는 단계, 상기 감광막패턴을 마스크로 이용하여 상기 절연막을 이방성식각하여 전하저장전극 콘택영역을 형성함과 동시에 상기 전하저장전극 콘택영역 중앙부분에 상기 절연막이 타워형태로 남도록 하는 단계, 상기 감광막패턴을 제거하는 단계, 상기 전하저장전극 콘택영역을 포함한 기판 전면에 도전층을 형성하는 단계, 및 상기 도전층을 소정패턴으로 패터닝하여 전하저장전극을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a charge storage electrode of a semiconductor memory device, the method comprising: forming conductive layer patterns having minute intervals on a semiconductor substrate, and forming an insulating layer on the conductive layer pattern; Forming a photoresist pattern for forming a charge storage electrode contact on the insulating layer; anisotropically etching the insulating layer using the photoresist pattern as a mask to form a charge storage electrode contact region; and at the center of the charge storage electrode contact region Leaving an insulating film in a tower shape, removing the photoresist pattern, forming a conductive layer on the entire surface of the substrate including the charge storage electrode contact region, and patterning the conductive layer in a predetermined pattern to form a charge storage electrode. It comprises a step.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2e에 본 발명에 의한 반도체 기억소자의 전하저장전극 형성방법을 공정순서에 따라 단면도로 나타내었다.2A to 2E illustrate cross-sectional views of a method of forming a charge storage electrode of a semiconductor memory device according to the present invention.

도 2a를 참조하면, 실리콘기판(1)상에 1차절연막(2)을 형성하고, 그 상부에 비트라인(3)을 형성한 후, 기판 전면에 2차절연막(4)을 형성한다. 이어서 2차절연막(4)상에 감광막을 도포하고 패터닝하여 전하저장전극 콘택 마스크(5)를 형성한다. 이때, 2차절연막(4) 형성시 고집적화로 인해 비트라인 패턴간의 간격이 좁을 경우 비트라인 패턴을 따라 절연막의 골이 깊어지게 된다. 상기 2차절연막(4)은 SixOyNz(x,y,z=0-5)로 형성하거나 P 또는 B가 도핑된 산화막을 이용하는 것이 바람직하다.Referring to FIG. 2A, a primary insulating film 2 is formed on a silicon substrate 1, a bit line 3 is formed thereon, and a secondary insulating film 4 is formed on the entire surface of the substrate. Subsequently, a photosensitive film is coated and patterned on the secondary insulating film 4 to form a charge storage electrode contact mask 5. At this time, when the gap between the bit line patterns is narrow due to high integration when forming the secondary insulating film 4, the valley of the insulating film is deepened along the bit line pattern. The secondary insulating film 4 is preferably formed of SixOyNz (x, y, z = 0-5) or an oxide film doped with P or B.

도 2b를 참조하면, 상기 전하저장전극 콘택 마스크(5)를 이용하여 상기 2차절연막(4)의 일부분만 식각하면 비트라인 패턴사이의 절연막의 골이 깊은 영역에 폴리머(20)가 형성된다. 상기 식각공정은 CxHyFz(x,y,z=0-10) 가스를 사용하여 실시하며, 식각장비로서는 TEL사의 DRM챔버를 이용하며, 식각조건은 1500-2000W, 15-35mTorr, C4H8;5-20sccm, CH2F2;0-10sccm, Ar;300-700sccm로 하여 식각을 진행하는 것이 바람직하다.Referring to FIG. 2B, when only a portion of the secondary insulating layer 4 is etched using the charge storage electrode contact mask 5, the polymer 20 is formed in the deep region of the insulating layer between the bit line patterns. The etching process is performed using CxHyFz (x, y, z = 0-10) gas, and the etching equipment uses TEL's DRM chamber, and the etching conditions are 1500-2000W, 15-35mTorr, C 4 H 8 ; Etching is preferably performed at 5-20 sccm, CH 2 F 2 ; 0-10 sccm, Ar; 300-700 sccm.

도 2c를 참조하면, 상기 제2절연막(4) 및 제1절연막(2)을 식각하여 전하저장전극 콘택을 형성한다. 이때, 상기 형성된 폴리머(20)가 식각장벽으로 작용하여 절연막이 완전히 제거되지 않고 콘택영역 중앙에 절연막 타워형태(10)로 남게 된다. 이어서 상기 전하저장전극 마스크를 제거하고, 전하저장전극 형성용 폴리실리콘(11)을 증착한 다음, 감광막을 사용하여 전하저장전극 마스크패턴(12)을 형성한다. 이때, 상기 폴리실리콘(11)은 콘택영역 중앙의 절연막 타워 형태를 따라 증착되므로 전하저장전극 형성시 표면적이 증대되는 효과를 초래하게 되므로 전하저장값의 증대에 기여하게 된다.Referring to FIG. 2C, the second insulating layer 4 and the first insulating layer 2 are etched to form a charge storage electrode contact. At this time, the formed polymer 20 acts as an etch barrier so that the insulating film is not completely removed and remains as an insulating film tower 10 in the center of the contact region. Subsequently, the charge storage electrode mask is removed, the polysilicon 11 for forming the charge storage electrode is deposited, and the charge storage electrode mask pattern 12 is formed using a photosensitive film. At this time, since the polysilicon 11 is deposited along the shape of the insulating film tower in the center of the contact region, the polysilicon 11 contributes to the increase of the charge storage value since the surface area is formed when the charge storage electrode is formed.

다음에 도 2d를 참조하면, 상기 마스크패턴(12)을 이용하여 상기 폴리실리콘층(11)을 식각하여 전하저장전극을 형성한 후, 마스크패턴을 제거한다.2D, the polysilicon layer 11 is etched using the mask pattern 12 to form a charge storage electrode, and then the mask pattern is removed.

이어서 도 2e에 도시된 바와 같이 상기 형성된 전하저장전극(11)의 전하저장값을 증가시키기 위하여 전하저장전극 하부의 2차절연막(4)을 등방성식각에 의해 일정부분 제거한다.Subsequently, as shown in FIG. 2E, in order to increase the charge storage value of the formed charge storage electrode 11, a portion of the secondary insulating layer 4 under the charge storage electrode is removed by isotropic etching.

도 3은 실험데이타로서 비트라인 패턴간 간격이 좁을때 절연막 골이 형성되어 식각도중 발생한 폴리머에 의해 절연막타워(30)가 형성된 상태를 도시한 단면도이다.FIG. 3 is a cross-sectional view illustrating a state in which the insulating film tower is formed by the polymer generated during etching due to the formation of insulating film valleys when the interval between the bit line patterns is narrow as experimental data.

상술한 바와 같이 패턴사이의 간격이 좁아짐에 따라 발생한 절연막타워가 전하저장전극 형성에 있어서 전하저장값을 증가시키는 요인으로 작용함을 알 수 있다.As described above, it can be seen that the insulating layer tower generated as the interval between the patterns is narrowed serves to increase the charge storage value in the formation of the charge storage electrode.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

본 발명에 의하면, 반도체소자의 고집적화에 따라 소자 제조공정시 형성되는 절연막 보이드를 이용함으로써 기존 공정의 변화없이 충분한 전하저장값을 갖는 반도체 기억소자의 전하저장전극을 형성할 수 있다.According to the present invention, it is possible to form the charge storage electrode of the semiconductor memory device having a sufficient charge storage value without changing the existing process by using the insulating film void formed during the device manufacturing process in accordance with the high integration of the semiconductor device.

Claims (7)

반도체기판상부에 미세한 간격을 갖는 도전층패턴들을 형성하는 단계와,Forming conductive layer patterns having minute spacing on the semiconductor substrate; 상기 도전층패턴상에 절연막을 형성하는 단계,Forming an insulating film on the conductive layer pattern; 상기 절연막상에 전하저장전극 콘택형성용 감광막패턴을 형성하는 단계,Forming a photoresist pattern for forming a charge storage electrode contact on the insulating layer; 상기 감광막패턴을 마스크로 이용하여 상기 절연막을 이방성식각하여 전하저장전극 콘택영역을 형성함과 동시에 상기 전하저장전극 콘택영역 중앙부분에 상기 절연막이 남도록 하는 단계,Anisotropically etching the insulating film using the photoresist pattern as a mask to form a charge storage electrode contact region and to leave the insulating film at a central portion of the charge storage electrode contact region; 상기 감광막패턴을 제거하는 단계,Removing the photoresist pattern; 상기 전하저장전극 콘택영역을 포함한 기판 전면에 도전층을 형성하는 단계, 및Forming a conductive layer on an entire surface of the substrate including the charge storage electrode contact region, and 상기 도전층을 소정패턴으로 패터닝하여 전하저장전극을 형성하는 단계Patterning the conductive layer in a predetermined pattern to form a charge storage electrode; 를 포함하는 반도체 기억소자의 전하저장전극 형성방법.Method for forming a charge storage electrode of a semiconductor memory device comprising a. 제1항에 있어서,The method of claim 1, 상기 감광막패턴을 마스크로 이용하여 상기 절연막을 이방성식각하는 단계에서, 상기 절연막을 일정부분 식각했을때 상기 전하저장전극 콘택영역 중앙부에 폴리머가 형성되고, 절연막의 식각이 계속 진행됨에 따라 상기 폴리머가 식각장벽으로 작용하여 식각완료시 폴리머 하부의 절연막부분이 타워형태로 남게 되는 반도체 기억소자의 전하저장전극 형성방법.In the anisotropic etching of the insulating layer using the photoresist pattern as a mask, a polymer is formed in the center of the charge storage electrode contact region when the insulating layer is partially etched, and the polymer is etched as the etching of the insulating layer continues. A method of forming a charge storage electrode of a semiconductor memory device in which an insulating film portion below a polymer is left in a tower shape when the etching is completed to act as a barrier. 제1항에 있어서,The method of claim 1, 상기 전하저장전극을 형성하는 단계후에 상기 절연막을 등방성식각을 통해 일정두께만큼 식각하는 단계가 더 포함되는 반도체 기억소자의 전하저장전극 형성방법.And etching the insulating layer by a predetermined thickness after isotropic etching after forming the charge storage electrode. 제1항에 있어서,The method of claim 1, 상기 도전층패턴이 비트라인 패턴인 반도체 기억소자의 전하저장전극 형성방법.A charge storage electrode forming method of a semiconductor memory device, wherein the conductive layer pattern is a bit line pattern. 제1항에 있어서,The method of claim 1, 상기 절연막을 SixOyNz(x,y,z=0-5)로 형성하거나 P 또는 B가 도핑된 산화막으로 형성하는 반도체 기억소자의 전하저장전극 형성방법.And forming the insulating film as SixOyNz (x, y, z = 0-5) or an oxide film doped with P or B. 제1항에 있어서,The method of claim 1, 상기 절연막의 이방성식각시 식각가스로 CF 계열 가스를 사용하는 반도체 기억소자의 전하저장전극 형성방법.A method of forming a charge storage electrode of a semiconductor memory device using CF-based gas as an etching gas for anisotropic etching of the insulating film. 제6항에 있어서,The method of claim 6, 상기 CF 계열 가스는 C4H8과 CH2F2의 혼합 가스인 반도체 기억소자의 전하저장전극 형성방법.And the CF-based gas is a mixed gas of C 4 H 8 and CH 2 F 2 .
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630666B1 (en) * 2000-08-09 2006-10-02 삼성전자주식회사 Method of manufacturing semiconductor device including metal contact and capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100630666B1 (en) * 2000-08-09 2006-10-02 삼성전자주식회사 Method of manufacturing semiconductor device including metal contact and capacitor

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