KR20010046511A - Capacitor of semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor device and a fabrication method thereof are provided to prevent a poor contact with a lower node by ensuring a margin of a node contact and further to prevent a short between the lower node and a bit line. CONSTITUTION: The capacitor is characterized by a polypad(41a) formed under the lower node(46a). In the method, the polypad(41a) is formed in a contact hole bored through interlayer dielectric layers(34,37) and passivation layers(36,38) to be contacted with a plug(33), and further partly extended over the upper passivation layer(38). Next, the polypad(41a) is covered with another interlayer dielectric layer formed over the upper passivation layer(38), and then a node contact hole is formed to expose the polypad(41a). Thereafter, the lower node(46a) is formed and the interlayer dielectric layer on the upper passivation layer(38) is removed. Then, a dielectric layer(48) and an upper node(49) are formed on the lower node(46a) and the polypad(41a).

Description

CAPACITY OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF {CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor and a manufacturing method thereof.

Referring to the accompanying drawings, a capacitor of a conventional semiconductor device and a method of manufacturing the same will be described.

1 is a structural cross-sectional view showing a capacitor of a conventional semiconductor device, Figures 2a to 2j is a process cross-sectional view showing a method of manufacturing a capacitor of a conventional semiconductor device.

Before describing the capacitor of a conventional semiconductor device, a transistor having a source, a drain, and a gate electrode is formed in the semiconductor substrate 1, although not shown in the drawing.

As shown in FIG. 1, a poly plug 3 is formed on the first interlayer insulating film 2 to be in contact with the source, and a second interlayer insulating film 4 is formed on the entire surface including the poly plug 3. The bit line 5 is formed on one region of the second interlayer insulating film 4 to be in contact with the drain.

The first silicon nitride film 6, the third interlayer insulating film 7, and the second silicon nitride film 11 are sequentially formed on the entire surface including the bit line 5 so that the poly plug 3 is exposed. Contact holes are formed in the second interlayer insulating film 4, the first silicon nitride film 6, the third interlayer insulating film 7, and the second silicon nitride film 11. At this time, the contact hole is formed by recessing the third interlayer insulating film 7 on both sides.

A poly plug 10a is formed to dent into the contact hole, and a cylindrical lower node 15a is formed in contact with the upper portion of the poly plug 10a. A dielectric film 17 and an upper node 18 are formed along the surface of the lower node 15a.

In the method of manufacturing a capacitor of a conventional semiconductor device having the above structure, as shown in FIG. 2A, the first interlayer insulating film 2 is deposited on the semiconductor substrate 1 with an oxide film, and then the first interlayer is exposed so that the source of the transistor is exposed. Contact holes are formed in the insulating film 2.

Thereafter, after depositing polysilicon on the front surface, polyplug is formed in the contact hole by an etch back or chemical mechanical polishing process. Then, a second interlayer insulating film 4 is deposited on the entire surface with an oxide film.

Next, although not shown in the drawing, contact holes are formed in the first and second interlayer insulating films 2 and 4 so that the drain of the transistor is exposed.

Then, after depositing a metal layer on the second interlayer insulating film 4, the bit line 5 is formed by anisotropic etching to contact the drain through the contact hole.

Thereafter, as shown in FIG. 2B, a first silicon nitride film 6 and a third interlayer insulating film 7 are deposited on the entire surface.

Next, as shown in FIG. 2C, after the photosensitive film 8 is applied on the third interlayer insulating film 7, the photosensitive film is exposed and developed to expose the third interlayer insulating film 7 on the upper side of the polyplug 3. Selectively pattern (8).

Subsequently, the contact hole may be exposed by anisotropically etching the third interlayer insulating film 7, the first silicon nitride film 6, and the second interlayer insulating film 4 using the patterned photosensitive film 8 as a mask. 9) form.

Next, as shown in FIG. 2D, the photosensitive film 8 is removed and polysilicon 10 is deposited on the third interlayer insulating film 7 including the contact hole 9.

As shown in FIG. 2E, the polysilicon 10 is etched back to form the polyplug 10a so that the polysilicon 10 remains in the contact hole 9. At this time, the poly plug 10a is formed by recessing the polysilicon 10 into the contact hole.

Next, as illustrated in FIG. 2F, a second silicon nitride film 11 is deposited on the third interlayer insulating film 7 including the polyplug 10a.

After depositing the fourth interlayer insulating film 12 on the second silicon nitride film 11 as shown in FIG. 2G, the photosensitive film 13 is coated on the fourth interlayer insulating film 12, followed by an exposure and developing process. As a result, a wider area is selectively patterned on the polyplug 10a.

Subsequently, the fourth interlayer insulating film 12, the second silicon nitride film 11, and the third interlayer insulating film 7 are anisotropically etched so that the poly plug 10a is exposed using the patterned photosensitive film 13 as a mask. 14). At this time, since the poly plug 10a is formed by recessing in the contact hole, a problem occurs that the second silicon nitride film 11 in contact with the poly plug 10a is not sufficiently etched and remains on the poly plug 10a.

Thereafter, as shown in FIG. 2H, the polysilicon 15 is disposed on the side of the node contact hole 14 and the fourth interlayer insulating layer 12 adjacent thereto so as to remove the photoresist layer 13 and contact the poly plug 10a. Deposit. An oxide film 16 is deposited on the entire surface of the polysilicon 15.

As shown in FIG. 2I, the oxide film 16 is etched back to expose the polysilicon 15 on the fourth interlayer insulating film 12. Subsequently, the polysilicon 15 is etched back to form a cylindrical lower node 15a on the side of the node contact hole 14.

Next, as shown in FIG. 2J, after the oxide film 16 and the fourth interlayer insulating film 12 are removed by wet etching, a dielectric film 17 is formed on the surface of the lower node 15a, and the lower node 15a is formed. An upper node 18 made of polysilicon is formed on the dielectric film 17 including the semiconductor layer 17.

The above-described capacitor of a semiconductor device and a manufacturing method thereof have the following problems.

First, when forming the polyplug, when the nitride layer of the node contact hole is subsequently etched by the recess of the polysilicon, the nitride layer may not be sufficiently etched, which may result in poor contact with the polyplug.

Second, when the node contact hole is overetched to avoid poor contact between the polyplug and the nitride layer, a short bit occurs with the lower bit line.

The present invention has been made to solve the above problems, and in particular, it is possible to prevent margin failure of contact with the lower node by securing a margin of the node contact, and also prevent the lower node from shorting with the bit line. It is an object of the present invention to provide a capacitor of a semiconductor device and a method of manufacturing the same.

1 is a structural cross-sectional view showing a capacitor of a conventional semiconductor device

2A through 2J are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.

3 is a structural cross-sectional view showing a capacitor of the semiconductor device of the present invention.

4A to 4J are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

33: polyplug 35: bit line

41 a: poly pad 38: first insulating film,

46a: lower node 48: dielectric film

49: upper node

The capacitor of the semiconductor device according to the present invention for achieving the above object is a plug having a source, a drain, and a gate electrode on a semiconductor substrate, the plug formed on the first interlayer insulating film to be in contact with the source, the front surface including the plug The second interlayer dielectric layer, the bit line formed on one region of the second interlayer dielectric layer to contact the drain, the first passivation layer, the third interlayer dielectric layer, the second passivation layer, and the plug, which are sequentially formed on the entire surface including the bit line, A contact hole formed in the second interlayer insulating layer, the first passivation layer, the third interlayer insulating layer, and the second passivation layer, a semiconductor pad formed on the contact hole and the second passivation layer adjacent thereto, and formed in contact with an upper portion of the semiconductor pad. A dielectric layer formed along a surface of the first node and the semiconductor pad; And a second node.

In a method of manufacturing a capacitor of a semiconductor device according to the present invention having the above configuration, in a transistor having a source, a drain, and a gate electrode on a semiconductor substrate, a step of forming a plug in a first interlayer insulating film to be in contact with the source includes the plug. Forming a second interlayer insulating film on the entire surface, forming a bit line on one region of the second interlayer insulating film to be in contact with the drain; a first protective film and a third interlayer insulating film on the entire surface including the bit line; Forming a second passivation layer in sequence, forming a contact hole in the second interlayer insulating layer, the first passivation layer, the third interlayer insulating layer, and the second passivation layer to expose the plug; and contacting the contact with the plug. Forming a semiconductor pad over a hole and the second passivation layer adjacent thereto; Forming a fourth interlayer dielectric layer on the second passivation layer, forming a node contact hole in the fourth interlayer dielectric layer so that one region of the semiconductor pad is exposed, and a side surface of the fourth interlayer dielectric layer in the node contact hole Forming a first node on the substrate; removing the fourth interlayer insulating film; and forming a dielectric film and a second node to surround surfaces of the first node and the semiconductor pad.

The present invention is to facilitate the method of forming a node contact when the height of the capacitor is increased in order to obtain the required capacitance as the semiconductor device is highly integrated, the structure and manufacturing method will be described with reference to the accompanying drawings. same.

3 is a structural cross-sectional view illustrating a capacitor of the semiconductor device of the present invention, and FIGS. 4A to 4J are process cross-sectional views illustrating a method of manufacturing a capacitor of the semiconductor device of the present invention.

Before describing the capacitor of the semiconductor device of the present invention, a transistor having a source, a drain, and a gate electrode is formed on the semiconductor substrate 31, although not shown in the drawing.

3, a poly plug 33 is formed on the first interlayer insulating layer 32 to be in contact with the source, and a second interlayer insulating layer 34 is formed on the entire surface including the poly plug 33. The bit line 35 is formed on one region of the second interlayer insulating layer 34 to be in contact with the drain.

A first silicon nitride film 35, a third interlayer insulating film 37, and a second silicon nitride film 38 are sequentially formed on the entire surface including the bit line, and the second interlayer may be exposed to expose the polyplug 33. Contact holes are formed in the insulating film 34, the first silicon nitride film 36, the third interlayer insulating film 37, and the second silicon nitride film 38.

A poly pad 41a is formed on a surface of the contact hole and the second silicon nitride layer 38 adjacent thereto, and the lower node 46a has a cylindrical shape by contacting an upper portion of the poly pad 41a. A dielectric film 48 and an upper node 49 are formed along the surfaces of the lower node 46a and the poly pad 41a.

Although the capacitor manufacturing method of the semiconductor device of the present invention having the above configuration is not shown in the drawing, a transistor having a source, a drain, and a gate electrode is formed.

As shown in FIG. 4A, after the first interlayer insulating film 32 is deposited on the semiconductor substrate 31 with an oxide film, contact holes are formed in the first interlayer insulating film 32 so that the source of the transistor is exposed.

Thereafter, after depositing polysilicon on the front surface, polyplug is formed in the contact hole by an etch back or chemical mechanical polishing process. Then, a second interlayer insulating film 34 is deposited on the entire surface with an oxide film.

Next, although not shown in the drawing, contact holes are formed in the first and second interlayer insulating films 32 and 34 so that the drain of the transistor is exposed. After depositing a metal layer on the second interlayer insulating film 34, the bit line 35 is formed by anisotropic etching to contact the drain through the contact hole.

Thereafter, as shown in FIG. 4B, the first silicon nitride film 36, the third interlayer insulating film 37, and the second silicon nitride film 38 are sequentially deposited on the entire surface. The third interlayer insulating film 37 is formed of an oxide film.

As shown in FIG. 4C, after the photoresist film 39 is coated on the second silicon nitride film 38, an exposure and development process is performed such that the second silicon nitride film 38 is exposed above the one region of the polyplug 33. Then, the photosensitive film 39 is selectively patterned.

The second silicon nitride film 38, the third interlayer insulating film 37, the first silicon nitride film 36, and the second interlayer insulating film 34 are subsequently anisotropically etched using the patterned photosensitive film 39 as a mask to form a polyplug. The contact hole 40 is formed so that the 33 is exposed.

Next, as shown in FIG. 4D, the photoresist film 39 is removed and polysilicon 41 is deposited on the second silicon nitride film 38 including the contact hole 40.

As shown in FIG. 4E, after the photoresist film 42 is applied to the entire surface, the photoresist film 42 is selectively patterned such that the photoresist film 42 remains only in the contact hole 40 and the upper portion having a wider width during the exposure and development processes.

Thereafter, the polysilicon 41 is removed using the patterned photoresist layer 42 as a mask to form a poly pad 41a on the contact hole 40 and the second silicon nitride layer 38 adjacent thereto.

As shown in FIG. 4G, a fourth interlayer insulating film 43 is deposited on the entire surface by an oxide film, and a photosensitive film 44 is coated on the fourth interlayer insulating film 43. As shown in FIG. Thereafter, the photosensitive film 44 is selectively patterned so that the fourth interlayer insulating film 43 on the upper portion of the poly pad 41a is exposed by the exposure and development processes.

Subsequently, the fourth interlayer insulating layer 43 is etched using the patterned photoresist 44 as a mask to form a node contact hole 45 so that the upper portion of the poly pad 41a is exposed.

After removing the photoresist film 44 as shown in FIG. 4H, the polysilicon 46 is deposited on the node contact hole 45 and the fourth interlayer insulating film 43 to be in contact with the poly pad 41a. Then, an oxide film 47 is deposited on the polysilicon 46 thickly.

Thereafter, as illustrated in FIG. 4I, the oxide film 47 is etched back to expose the polysilicon 46 on the fourth interlayer insulating film 43 so that the polysilicon 46 is exposed. The polysilicon 46 is etched back to form a cylindrical lower node 46a on the side of the node contact hole 45.

Next, as shown in FIG. 4J, after the oxide film 47 and the fourth interlayer insulating film 43 are removed by wet etching, the dielectric film 48 is formed on the surfaces of the poly pad 41a and the lower node 46a. An upper node 49 made of polysilicon is formed on the dielectric film 48 including the lower node 46a.

The above-described capacitor of the semiconductor device of the present invention and its manufacturing method have the following effects.

First, since the fourth planar passivation layer is sufficiently overetched when the node contact is formed by forming the poly pad under the node contact, it is possible to prevent a poor contact with the lower node later.

Second, by forming a poly pad under the node contact, even if the fourth planar passivation layer is sufficiently overetched at the time of forming the node contact, the lower node can be prevented from shorting with the bit line later.

Claims (8)

In a transistor having a source, a drain, and a gate electrode on a semiconductor substrate, A plug formed on the first interlayer insulating film to be in contact with the source; A second interlayer insulating film formed on the front surface including the plug, A bit line formed on one region of the second interlayer insulating layer to be in contact with the drain; A first passivation layer, a third interlayer insulating layer, and a second passivation layer sequentially formed on the entire surface including the bit line; A contact hole formed in the second interlayer insulating film, the first passivation film, the third interlayer insulating film, and the second passivation film so that the plug is exposed; A semiconductor pad formed on the contact hole and the second passivation layer adjacent thereto; A first node formed in contact with an upper portion of the semiconductor pad; And a dielectric layer and a second node formed along a surface of the first node and the semiconductor pad. The capacitor of claim 1, wherein the first and second passivation layers are formed of a silicon nitride layer. In a transistor having a source, a drain, and a gate electrode on a semiconductor substrate, Forming a plug in the first interlayer insulating film to be in contact with the source; Forming a second interlayer insulating film on the entire surface including the plug; Forming a bit line on one region of the second interlayer insulating film to be in contact with the drain; Sequentially forming a first passivation layer, a third interlayer insulating layer, and a second passivation layer on the entire surface including the bit line; Forming a contact hole in the second interlayer insulating layer, the first passivation layer, the third interlayer insulating layer, and the second passivation layer so that the plug is exposed; Forming a semiconductor pad over the contact hole and the second passivation layer adjacent to the plug to contact the plug; Forming a fourth interlayer insulating film on the second passivation film including the semiconductor pad; Forming a node contact hole in the fourth interlayer insulating layer so that one region of the semiconductor pad is exposed; Forming a first node on a side of the fourth interlayer insulating film of the node contact hole; Removing the fourth interlayer insulating film, And forming a dielectric film and a second node to surround the surfaces of the first node and the semiconductor pad. 4. The method of claim 3, wherein the first node is formed in a cylindrical shape. The method of claim 4, wherein the cylindrical first node comprises: forming a semiconductor layer on the fourth interlayer insulating layer including the node contact hole to contact the semiconductor pad; Depositing an insulating film over the entire semiconductor layer; Removing the insulating film to expose the semiconductor layer on the fourth interlayer insulating film, Etching the semiconductor layer so as to remain on a side of the fourth interlayer insulating layer in which the node contact hole is formed; And removing said insulating film and said fourth interlayer insulating film at the same time. 4. The method of claim 3, wherein the first and second passivation layers are formed of a nitride film. The method of claim 3, wherein the plug is made of polysilicon. 4. The method of claim 3, wherein the first to fourth interlayer insulating films are formed of an oxide film.