KR100192173B1 - Method of forming a tungsten plug in a semiconductor device - Google Patents
Method of forming a tungsten plug in a semiconductor device Download PDFInfo
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- KR100192173B1 KR100192173B1 KR1019950048308A KR19950048308A KR100192173B1 KR 100192173 B1 KR100192173 B1 KR 100192173B1 KR 1019950048308 A KR1019950048308 A KR 1019950048308A KR 19950048308 A KR19950048308 A KR 19950048308A KR 100192173 B1 KR100192173 B1 KR 100192173B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
본 발명은 텅스텐 플러그 형성시 단차 부위에 잔류하는 텅스텐층을 효과적으로 제거하는 반도체 소자의 텅스텐 플러그 형성방법을 제공하는 것을 목적으로 한다. 이와 같은 목적을 달성하기 위한 본 발명의 콘택홀 형성방법은 콘택홀이 형성된 반도체 소자의 전면에 소정 두께의 텅스텐을 형성하는 단계; 비등방성 과소식각하여 형성된 텅스텐막을 최초 도포시의 두께보다 얇게 형성하는 단계; 얇아진 텅스텐 막 위에 금속배선막과 반사방지막을 순차적으로 형성하는 단계; 감광막 패턴을 도포하여 사진식각법으로 텅스텐 플러그와 전기적으로 접촉하는 3층의 금속패턴만을 남기고 식각하는 단계; 상기 단계의 결과적인 구조의 웨이퍼를 금속층들을 산화시키기 위한 산화용액을 소정시간동안 디핑하는 단계; 3층의 금속배선층에서 중간층인 순수한 금속배선의 상부 표면이 노출될 때까지 비등방성 과도 식각하는 단계를 포함한다.An object of the present invention is to provide a method for forming a tungsten plug of a semiconductor device which effectively removes a tungsten layer remaining at a stepped portion when forming a tungsten plug. Contact hole forming method of the present invention for achieving the above object comprises the steps of forming a tungsten of a predetermined thickness on the front surface of the semiconductor device in which the contact hole is formed; Forming a tungsten film formed by anisotropic over-etching to be thinner than the thickness at the time of initial application; Sequentially forming a metal wiring film and an anti-reflection film on the thinned tungsten film; Applying a photoresist pattern to etch leaving only three metal patterns in electrical contact with the tungsten plug by photolithography; Dipping an oxide solution for oxidizing the metal layers of the wafer of the resultant structure for a predetermined time; Anisotropic over etching is performed until the upper surface of the pure metal wiring, which is the intermediate layer, is exposed in the three metal wiring layers.
Description
제1도는 종래의 실시예에 따른 텅스텐 플러그 형성시의 텅스텐 잔류물의 생성을 보여주는 반도체 소자의 부분 단면도.1 is a partial cross-sectional view of a semiconductor device showing the production of tungsten residue when forming a tungsten plug according to a conventional embodiment.
제2도는 본 발명의 실시예에 따른 반도체 소자의 텅스텐 플러그 형성방법을 설명하기 위한 공정 흐름도.2 is a process flowchart illustrating a tungsten plug forming method of a semiconductor device according to an embodiment of the present invention.
제3도는 본 발명의 실시예에 따른 반도체 소자의 텅스텐 플러그 형성방법을 설명하기 위한 공정 흐름도.3 is a flowchart illustrating a method of forming a tungsten plug in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 20 : 도전막 11, 21 : 반도체 기판10, 20: conductive film 11, 21: semiconductor substrate
12, 22 : 실리콘산화막 13, 23 : 텅스텐 플러그12, 22: silicon oxide film 13, 23: tungsten plug
14 : 텅스텐막 15, 25 : 알루미늄 합금14: tungsten film 15, 25: aluminum alloy
16, 26 : 반사 방지막 17, 24 : 텅스텐 잔류물16, 26: antireflection film 17, 24: tungsten residue
18 : 금속산화막18: metal oxide film
본 발명은 반도체 소자의 형성방법에 관한 것으로, 특히 텅스텐 플러그 형성시 단차(topology) 부위에 잔류하는 텅스텐층을 효과적으로 제거하는 텅스텐 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a tungsten plug which effectively removes a tungsten layer remaining on a topology portion when forming a tungsten plug.
일반적으로 반도체 소자에서 전위를 인가해야 하는 활성영역이나 다층배선의 연결부에는 콘택홀(Contact Hole)이나 비아홀(Via Hole)과 같은 구멍들이 전기적인 연결을 위하여 뚫려진다.In general, holes such as contact holes or via holes are drilled in the connection area of the active region or the multilayer wiring to which the potential is applied in the semiconductor device for electrical connection.
첨부한 도면 제1도는 필드 산화막상에 형성된 도전막에 전기적으로 연결된 텅스텐 플러그를 포함하는 부분의 단면도로서, 상기 텅스텐 플러그는 다음과 같은 과정을 통하여 형성된다.1 is a cross-sectional view of a portion including a tungsten plug electrically connected to a conductive film formed on a field oxide film, the tungsten plug being formed through the following process.
먼저, 필드 산화막(2) 및 도전막(3)을 포함하는 패턴에 형성 되어 있는 실리콘 기판(1)의 전체 구조 상부에 절연을 위한 산화막(4)을 적층한 다음 사진식각법으로 콘택홀을 형성한다. 이어서, 전체 구조 상부에 텅스텐층을 적층한 다음, 비등방성 식각하여 텅스텐 플러그(콘택홀 내부를 매립하는 텅스텐층)(5)를 형성한다.First, an oxide film 4 for insulation is laminated on the entire structure of the silicon substrate 1 formed on the pattern including the field oxide film 2 and the conductive film 3, and then contact holes are formed by photolithography. do. Subsequently, a tungsten layer is laminated on the entire structure, and then anisotropically etched to form a tungsten plug (tungsten layer for embedding the inside of the contact hole) 5.
그러나, 상기와 같이 비등방성 식각을 이용하여 텅스텐층을 식각하는 종래의 방법으로는 산화막(4) 상의 단차가 큰 부위에 텅스텐 잔류물(6)이 남게 되어 배선의 불량을 유발시키는 원인이 되고, 이에 따라 제품의 신뢰성을 저하시키는 문제점을 초래하였다.However, in the conventional method of etching the tungsten layer using anisotropic etching as described above, the tungsten residue 6 remains on the large stepped portion on the oxide film 4, which causes the wiring defect. This caused a problem of lowering the reliability of the product.
남게 되어 배선의 불량을 유발시키는 원인이 되고, 이에 따라 제품의 신뢰성을 저하시키는 문제점을 초래하였다.It remains, causing the wiring to be defective, thereby causing a problem of lowering the reliability of the product.
따라서, 본 발명의 목적은 배선불량을 유발시키는 단차상의 텅스텐 잔류물을 습식 산화법으로 산화시키고, 건식식각법으로 제거시키므로써, 상기한 문제점을 해결할 수 있는 텅스텐 플러그 형성방법을 제공하기 위한 것이다.Accordingly, it is an object of the present invention to provide a tungsten plug forming method which can solve the above problems by oxidizing a stepped tungsten residue causing wet wiring by wet oxidation and removing by dry etching.
이와 같은 목적을 달성하기 위한 본 발명의 텅스텐 플러그 형성방법은 콘택홀이 형성된 반도체 소자의 전면에 소정 두께의 텅스텐을 형성하는 단계; 비등방성 과소식각하여 형성된 텅스텐막을 최초 도포시의 두께보다 얇게 형성하는 단계; 얇아진 텅스텐 막 위에 금속배선막과 반사방지막을 순차적으로 형성하는 단계; 감광막 패턴을 도포하여 사진식각법으로 텅스텐 플러그와 전기적으로 접촉하는 3층의 금속패턴만을 남기고 식각하는 단계; 상기 단계의 결과적인 구조의 웨이퍼를 금속층들을 산화시키기 위한 산화용액에 소정 시간동안 디핑하는 단계; 3층의 금속배선층에서 중간층인 순수한 금속배선의 상부 표면이 노출될 때까지 건식 식각하는 단계를 포함하는 것을 특징으로 한다.The tungsten plug forming method of the present invention for achieving the above object comprises the steps of forming a tungsten having a predetermined thickness on the front surface of the semiconductor element formed with a contact hole; Forming a tungsten film formed by anisotropic over-etching to be thinner than the thickness at the time of initial application; Sequentially forming a metal wiring film and an anti-reflection film on the thinned tungsten film; Applying a photoresist pattern to etch leaving only three metal patterns in electrical contact with the tungsten plug by photolithography; Dipping the wafer of the resultant structure of the step into an oxidizing solution for oxidizing the metal layers for a predetermined time; And dry etching the three layers of the metallization layer until the upper surface of the pure metallization, which is the intermediate layer, is exposed.
상기한 목적을 달성하기 위한 본 발명의 또 다른 텅스텐 플러그 형성방법은 콘택홀이 형성된 반도체 소자의 콘택홀을 포함하는 절연막 전면에 소정 두께의 텅스텐을 형성하는 단계; 형성된 텅스텐막을 절연막이 드러나는 종말점까지 비등방성 식각하는 단계; 노출된 절연막과 텅스텐 플러그 위에 금속배선막과 반사방지막을 순차적으로 형성하는 단계; 감광막 패턴을 도포하여 사진식각법으로 텅스텐 플러그와 전기적으로 접촉하는 2층의 금속패턴만을 남기고 식각하는 단계; 상기 단계의 결과적인 구조의 웨이퍼를 금속층들을 산화시키기 위한 산화용액에 소정시간동안 디핑하는 단계; 2층의 금속배선층에서 하부층인 순수한 금속배선의 상부 표면이 노출될 때까지 건식 과도식각하는 단계를 포함하는 것을 특징으로 한다.Another method of forming a tungsten plug according to the present invention for achieving the above object comprises the steps of forming a tungsten having a predetermined thickness on the entire surface of the insulating film including a contact hole of a semiconductor device in which a contact hole is formed; Anisotropically etching the formed tungsten film to an end point where the insulating film is exposed; Sequentially forming a metal interconnection film and an anti-reflection film on the exposed insulating film and the tungsten plug; Applying a photoresist pattern to etch leaving only two metal patterns in electrical contact with the tungsten plug by photolithography; Dipping the wafer of the resultant structure of the step into an oxidizing solution for oxidizing the metal layers for a predetermined time; And dry overetching the two layers of the metallization layer until the upper surface of the pure metallization, which is the lower layer, is exposed.
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 따른 텅스텐 플러그 형성방법을 설명하면 다음과 같다.Hereinafter, a tungsten plug forming method according to an embodiment of the present invention with reference to the accompanying drawings.
첨부한 도면 제2도는 본 발명의 제1실시예에 따른 텅스텐 플러그 형성방법을 보여주는 공정 흐름도이다.2 is a flowchart illustrating a method of forming a tungsten plug according to a first embodiment of the present invention.
먼저 (a)에 도시한 바와 같이, 반도체 기판에 형성된 필드 산화막위에 도전막 패턴(10)이 형성되고, 이 형성된 도전막 패턴(10)과 금속배선과 콘택홀에 형성된 텅스텐 플러그를 통하여 전기적으로 연결되는 반도체 소자에 있어서, 콘택홀을 포함하는 절연을 위한 실리콘산화막(12) 전면에 5,000 내지 8,000Å 두께의 텅스텐을 도포한다. 이 때 도포되는 텅스텐막의 두께는 콘택홀을 완전히 매립하고 남을 정도의 두께이다. 도포된 텅스텐막을 비등방성(anisotropy) 과소식각하여 형성된 텅스텐막을 최초 도포시의 두께보다 얇은 500 내지 1,000A 정도의 두께만을 남겨 두고 제거한다. 이 때, 콘택홀에는 텅스텐 플러그(13)가 이미 형성된 상태이다.First, as shown in (a), the conductive film pattern 10 is formed on the field oxide film formed on the semiconductor substrate, and is electrically connected to the formed conductive film pattern 10 through the tungsten plug formed in the metal wiring and the contact hole. In the semiconductor device, tungsten having a thickness of 5,000 to 8,000 Å is coated on the entire surface of the silicon oxide film 12 for insulation including the contact hole. The thickness of the tungsten film applied at this time is such that the contact hole is completely filled. The tungsten film formed by anisotropy underetching of the applied tungsten film is removed leaving only a thickness of about 500 to 1,000 A, which is thinner than the thickness of the initial coating. At this time, the tungsten plug 13 is already formed in the contact hole.
이 후, (b)에 도시한 바와 같이, 얇아진 텅스텐 막(14) 위에 알루미늄(Al) 합금의 금속배선막(15)과 TiN의 반사방지막(16)을 순차적으로 적층한다.Thereafter, as shown in (b), the metal wiring film 15 of aluminum (Al) alloy and the anti-reflection film 16 of TiN are sequentially stacked on the thinned tungsten film 14.
반사 방지막(16) 위에 감광막 마스크 패턴을 형성하고, 상기 감광막을 식각 장벽막으로 하여 감광막이 없는 부분의 반사방지막(16), 금속배선막(15), 텅스텐막(14)을 제거한다.A photoresist mask pattern is formed on the antireflection film 16, and the antireflection film 16, the metal wiring film 15, and the tungsten film 14 in the portion without the photoresist film are removed using the photoresist film as an etch barrier film.
이 때의 공정으로 노출된 절연막의 단차 부위에는 텅스텐 잔류물(17)이 (c)도면과 같이 남게 된다.At the step, the tungsten residue 17 remains in the stepped portion of the insulating film exposed as shown in the drawing (c).
상기 텅스텐 잔류물(17)을 제거하기 위하여 텅스텐 잔류물(17)과 3층 금속배선의 노출 부위를 산화시켜 (e)와 같은 금속산화층(18)을 형성시킨다.In order to remove the tungsten residue 17, the exposed portion of the tungsten residue 17 and the three-layer metal wiring is oxidized to form a metal oxide layer 18 such as (e).
산화시의 조건은 과산화수소(H2O2)와 초순수(H2O)가 1 : 1로 혼합된 화학용액을 약 50 내지 100℃로 가열한 다음에, 상기 화학용액에 (c)도면 상태의 웨이퍼를 담근다. 이로 인하여 텅스텐 잔류물(17)과 3층의 금속배선층의 둘레에는 소정 두께의 금속산화층(18)이 약 100 내지 1,000Å정도 성장하게 된다. 상기 금속산화층의 두께는 화학용액에 담그는 시간 (dipping time)에 따라 변화되는데, 상기한 산화층 두께를 얻기 위한 적정 시간은 5 내지 10분 내외로 한다.The oxidation condition is that the chemical solution mixed with hydrogen peroxide (H 2 O 2 ) and ultrapure water (H 2 O) in 1: 1 is heated to about 50 to 100 ° C., and then the chemical solution Dip the wafer. As a result, the metal oxide layer 18 having a predetermined thickness grows about 100 to 1,000 Å around the tungsten residue 17 and the three metal wiring layers. The thickness of the metal oxide layer is changed depending on the dipping time in the chemical solution, the appropriate time for obtaining the oxide layer thickness is about 5 to 10 minutes.
다음으로, 3층의 금속배선층에서 중간층인 순수한 금속배선(15)의 상부 표면이 노출될 때까지 비등방성 식각한다. 비등방성 식각을 위하여 NF3개스를 반응개스로서 공급하는 건식 플라즈마 식각을 이용하고, 식각 정도는 중간층의 금속배선막인 알루미늄 합금막(15)이 노출되도록 과도식각을 충분히 실시해야 한다.Next, anisotropic etching is performed until the upper surface of the pure metal wiring 15, which is an intermediate layer, is exposed in the three metal wiring layers. For the anisotropic etching, dry plasma etching is used to supply NF 3 gas as the reaction gas, and the etching degree should be sufficiently etched so that the aluminum alloy film 15, which is the metal wiring film of the intermediate layer, is exposed.
상기 식각공정으로 단차 부위에 존재하던 텅스텐 잔류물은 깨끗하게 제거되고, 아울러 금속배선의 측면에는 금속산화층(18)이 잔류하게 되므로, 금속배선의 부식을 예방하는데 도움을 주게 된다.The tungsten residue in the stepped portion is removed by the etching process, and the metal oxide layer 18 remains on the side of the metal wiring, thereby helping to prevent corrosion of the metal wiring.
상기 제1실시예에서는 텅스텐막을 두껍게 도포한 후, 비등방성 과소 식각하여 얇게 만든 다음, 후속공정을 진행하였지만, 제2실시예에서는 비등방성 과소식각을 하지 않고, 텅스텐막이 증착된 상태에서 알루미늄 합금의 금속배선막과 TiN의 반사방지막을 적층하는 후속공정을 바로 진행하여도 동일한 효과를 동일한 효과를 얻을 수 있다.In the first embodiment, the tungsten film was thickly coated and then anisotropic underetched to be thin, and then a subsequent process was performed. In the second embodiment, the aluminum alloy was deposited without the anisotropic underetching and the tungsten film was deposited. The same effect can be obtained by directly proceeding the subsequent process of laminating the metal wiring film and the anti-reflection film of TiN.
첨부한 도면 제3도는 본 발명의 제3실시예에 따른 텅스텐 플러그 형성방법을 보여주는 공정흐름도이다.3 is a flowchart illustrating a method of forming a tungsten plug according to a third embodiment of the present invention.
먼저, (a)에 도시된 바와 같이, 반도체 기판(21)에 형성된 필드 산화막위에 도전막 패턴이 형성되고, 형성된 도전막 패턴 위에 금속배선과의 절연을 위한 산화막이 형성되며, 산화막의 소정 부위에는 상기 도전막과 후속 공정에서 형성될 금속배선을 전기적으로 연결하기 위한 콘택홀이 형성되어 있는 반도체 소자에 있어서, 금속배선을 형성하기 위한 첫 번째 공정으로, 콘택홀을 포함하는 절연을 이한 실리콘산화막(12) 전면에 5,000 내지 8,000Å 두께의 텅스텐을 도포한다. 도포된 텅스텐막을 종말점(end-point) 식각하여 콘택홀에 매립된 텅스텐 플러그를 제외한 산화막 상의 텅스텐 막을 제거한다.First, as shown in (a), a conductive film pattern is formed on the field oxide film formed on the semiconductor substrate 21, and an oxide film for insulation with metal wiring is formed on the formed conductive film pattern, and a predetermined portion of the oxide film In a semiconductor device in which a contact hole for electrically connecting the conductive film and a metal wiring to be formed in a subsequent process is formed, the first process for forming the metal wiring includes a silicon oxide film having an insulation including a contact hole ( 12) Apply tungsten with a thickness of 5,000 to 8,000 mm3 on the entire surface. The applied tungsten film is etched end-point to remove the tungsten film on the oxide film except for the tungsten plug embedded in the contact hole.
식각을 위하여 공급되는 개스는 적정비율로 혼합된 SF6, O2, Ar이다. 식각 공정 후에도 산화막(22)의 단차 부위에는 텅스텐 잔류물(24)이 남게 된다.The gas supplied for etching is SF 6 , O 2 , Ar mixed at an appropriate ratio. Even after the etching process, the tungsten residue 24 remains in the stepped portion of the oxide film 22.
이 후, (b)에 도시한 바와 같이, 텅스텐 플러그를 포함하는 산화막(22)위에 알루미늄(Al)로 합금의 금속배선막(25)과 TiN의 반사방지막(26)을 순차적으로 적층한다.Subsequently, as shown in (b), the metal wiring film 25 of the alloy and the anti-reflection film 26 of TiN are sequentially stacked on the oxide film 22 including the tungsten plug with aluminum (Al).
반사 방지막(26) 위에 감광막 마스크 패턴(미도시)을 형성하고, 상기 감광막을 식각 장벽막으로 하여 감광막이 없는 부분의 반사방지막(26), 금속배선막(25)을 제거한다.A photoresist mask pattern (not shown) is formed on the antireflection film 26, and the antireflection film 26 and the metal wiring film 25 in the portion without the photoresist film are removed using the photoresist film as an etch barrier film.
상기 공정 후에도 노출된 절연막의 단차 부위에는 텅스텐 잔류물(24)이 (c)도면과 같이 게속 남아 있게 된다.Even after the above step, the tungsten residue 24 remains at the stepped portion of the exposed insulating film as shown in (c).
상기 텅스텐 잔류물(24)을 제거하기 위하여 텅스텐 잔류물(24)과 3층 금속배선의 노출 부위를 산화시켜 (d)와 같은 금속산화층(27)을 형성시킨다.In order to remove the tungsten residue 24, the exposed portion of the tungsten residue 24 and the three-layer metal wiring is oxidized to form a metal oxide layer 27 as shown in (d).
산화시의 조건은 과산화수소(H2O2)와 초순수(H2O)가 1 : 1로 혼합된 화학용액을 약 50 내지 100℃로 가열한 다음에, 상기 화학용액에 (c)도면 상태의 웨이퍼를 담근다. 이로 인하여 텅스텐 잔류물(24)과 2층의 금속배선층의 둘레에는 소정 두께의 금속산화층(27)이 약 100 내지 1,000Å정도 성장하게 된다. 상기 금속산화층의 두께는 화학용액에 담그는 시간 (dipping time)에 따라 변화되는데, 상기한 산화층 두께를 얻기 위한 적정 시간은 5 내지 10분 내외로 한다.The oxidation condition is that the chemical solution mixed with hydrogen peroxide (H 2 O 2 ) and ultrapure water (H 2 O) at 1: 1 is heated to about 50 to 100 ° C., and then the wafer in (c) Soak. As a result, the metal oxide layer 27 having a predetermined thickness grows about 100 to 1,000 Å around the tungsten residue 24 and the two-layer metal wiring layer. The thickness of the metal oxide layer is changed depending on the dipping time in the chemical solution, the appropriate time for obtaining the oxide layer thickness is about 5 to 10 minutes.
다음으로, 2층의 금속배선층에서 중간층인 순수한 금속배선(25)의 상부표면이 노출될 때까지 비등방성 식각한다. 비등방성 식각을 위하여 NF3개스를 반응개스로서 공급하는 건식 플라즈마 식각을 이용하고, 식각 정도는 중간층의 금속배선막인 알루미늄 합금막(25)이 노출되도록 과도식각을 충분히 실시해야 한다.Next, anisotropic etching is performed on the two metal wiring layers until the upper surface of the pure metal wiring 25 as an intermediate layer is exposed. For anisotropic etching, dry plasma etching using NF 3 gas as a reaction gas is used, and the etching degree should be sufficiently etched so that the aluminum alloy film 25, which is the metallization film of the intermediate layer, is exposed.
상기 식각공정으로 단차 부위에 존재하던 텅스텐 잔류물은 깨끗하게 제거되고, 아울러 금속배선의 측면에는 금속산화층(27)이 잔류하게 되므로, 금속 배선의 부식을 예방하는데 도움을 주게 된다.As a result of the etching process, the tungsten residue present in the stepped portion is removed cleanly, and the metal oxide layer 27 remains on the side of the metal wiring, thereby helping to prevent corrosion of the metal wiring.
이상에서 설명한 바와 같이, 본 발명의 텅스텐 플러그 형성방법은 플러그 형성시 절연막의 단차 부위에 남게 되는 텅스텐 잔류물을 효과적으로 제거하면서 이와 아울러 TiN의 반사 방지막도 동시에 제거하므로써, 이후의 금속배선 형성시에 TiN막으로 인하여 접촉저항이 높아지는 문제점을 제거할 수 있다. 따라서, 본 발명은 반도체 장치의 제조에 있어서, 수율 및 신뢰성을 획기적으로 개선하는 효과를 제공한다.As described above, the tungsten plug forming method of the present invention effectively removes the tungsten residue remaining on the stepped portion of the insulating film when the plug is formed, and simultaneously removes the anti-reflective film of TiN, thereby forming TiN during the subsequent metal wiring formation. The film eliminates the problem of high contact resistance. Accordingly, the present invention provides an effect of significantly improving yield and reliability in the manufacture of semiconductor devices.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (11)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048308A KR100192173B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming a tungsten plug in a semiconductor device |
| GB9623662A GB2307341B (en) | 1995-11-15 | 1996-11-13 | Method of forming a tungsten plug of a semiconductor device |
| TW085113975A TW342530B (en) | 1995-11-15 | 1996-11-14 | Process for forming a semiconductor tungsten plug |
| JP8302706A JP2745216B2 (en) | 1995-11-15 | 1996-11-14 | Method for forming tungsten plug in semiconductor device |
| US08/747,794 US5930670A (en) | 1995-11-15 | 1996-11-14 | Method of forming a tungsten plug of a semiconductor device |
| CN96123321A CN1096113C (en) | 1995-11-15 | 1996-11-15 | Method of forming tungsten plug of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048308A KR100192173B1 (en) | 1995-12-11 | 1995-12-11 | Method of forming a tungsten plug in a semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970053521A KR970053521A (en) | 1997-07-31 |
| KR100192173B1 true KR100192173B1 (en) | 1999-06-15 |
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| KR1019950048308A KR100192173B1 (en) | 1995-11-15 | 1995-12-11 | Method of forming a tungsten plug in a semiconductor device |
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| KR19990057826A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Metal wiring formation method of semiconductor device |
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