JP2576245B2 - Manufacturing method of semiconductor pressure sensor - Google Patents

Manufacturing method of semiconductor pressure sensor

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Publication number
JP2576245B2
JP2576245B2 JP393590A JP393590A JP2576245B2 JP 2576245 B2 JP2576245 B2 JP 2576245B2 JP 393590 A JP393590 A JP 393590A JP 393590 A JP393590 A JP 393590A JP 2576245 B2 JP2576245 B2 JP 2576245B2
Authority
JP
Japan
Prior art keywords
layer
etching
pressure sensor
film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP393590A
Other languages
Japanese (ja)
Other versions
JPH03209778A (en
Inventor
健友 上條
繁美 野原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP393590A priority Critical patent/JP2576245B2/en
Publication of JPH03209778A publication Critical patent/JPH03209778A/en
Application granted granted Critical
Publication of JP2576245B2 publication Critical patent/JP2576245B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measuring Fluid Pressure (AREA)
  • Pressure Sensors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ゲージ抵抗に設けられるダイアフラム部形
成のために、半導体基体にエッチングにより凹加工する
半導体圧力センサの製造方法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure sensor in which a semiconductor substrate is recessed by etching to form a diaphragm provided on a gauge resistor.

〔従来の技術〕[Conventional technology]

半導体圧力センサは、圧力が加わったことによるダイ
アフラム部の変形によって生ずるゲージ抵抗の変化によ
って圧力を検出するので、ダイアフラム部の厚さが所定
の厚さになるように凹加工をしなければならない。その
ためには電解エッチングを行い、p層とn層の界面での
エッチング特性の変化を利用する、いわゆるストップエ
ッチングが行われる。しかし、凹部全体を電解エッチン
グで加工するには時間がかかるためにドライエッチング
方により粗加工をする。この凹加工は1枚のウエハに多
数同時に行い、そのあとで各圧力センサチップに分割す
る。
Since the semiconductor pressure sensor detects pressure by a change in gauge resistance caused by deformation of the diaphragm due to the application of pressure, it must be recessed so that the thickness of the diaphragm becomes a predetermined thickness. For this purpose, electrolytic etching is performed, and so-called stop etching, which utilizes a change in etching characteristics at the interface between the p-layer and the n-layer, is performed. However, it takes a long time to process the entire concave portion by electrolytic etching. Therefore, rough processing is performed by dry etching. This concave processing is performed simultaneously on a large number of wafers, and then the wafer is divided into pressure sensor chips.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

ドライエッチング法で凹形状形成の粗加工をする際、
Alマスクを用いる。第2図はドライエッチング後の状態
を示し、シリコン基板にはn+層1の一面側にp層2およ
びn層3が形成されている。その上を酸化膜4を介して
Si3N4膜5が被覆し、表面を保護している。他面側に
は、Al蒸着膜からなるマスク6が被着しており、このマ
スクを用いてのドライエッチングにより凹部71が形成さ
れている。しかし、この場合、図のようにAlマスクのば
り61が基板の側面に張り出し、n層3に接触することが
ある。あるいは、図のようにn層3からn+層1につき抜
けるような不純物、あるいは歪21が存在することがあ
る。このようなばり61あるいは欠陥21が存在すると、次
に第3図に示すようにAlマスクを除去してレジスト8で
保護し、n+層1にエッチング液に浸漬された陰極に対し
て正の直流電圧を印加して電解エッチングを行う際、も
れ電流22が流れ、電解エッチングで形成される凹部72が
n+層1とp層の界面でとまらないノンストップ現象が生
じ、残ったダイアフラム部の厚さは所期の値より寸法
d、すなわちノンストップエッチ量だけ小さくなってし
まう問題があった。
When roughing concave shape by dry etching method,
An Al mask is used. FIG. 2 shows a state after dry etching, in which a p layer 2 and an n layer 3 are formed on one surface side of an n + layer 1 on a silicon substrate. Above it via the oxide film 4
The Si 3 N 4 film 5 covers and protects the surface. On the other surface side, a mask 6 made of an Al vapor-deposited film is adhered, and a concave portion 71 is formed by dry etching using this mask. However, in this case, the burrs 61 of the Al mask may protrude to the side surfaces of the substrate as shown in FIG. Alternatively, there may be an impurity or a strain 21 that escapes from the n layer 3 to the n + layer 1 as shown in the figure. If such burr 61 or defect 21 is present, protected by a resist 8 and then removed Al mask as shown in FIG. 3, n + layer 1 to the etchant positive relative immersed cathode When a DC voltage is applied to perform electrolytic etching, a leakage current 22 flows, and a concave portion 72 formed by electrolytic etching is formed.
A non-stop phenomenon that does not stop at the interface between the n + layer 1 and the p layer occurs, and there is a problem that the thickness of the remaining diaphragm portion becomes smaller than the expected value by the dimension d, that is, the non-stop etch amount.

本発明の目的は、上述の問題を解決し、エッチングさ
れるべきn層と隣接p層との間のもれ電流によりpn界面
で電解エッチングが停止されないことを防止する半導体
圧力センサの製造方法を提供することにある。
An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a semiconductor pressure sensor that prevents electrolytic etching from being stopped at a pn interface due to leakage current between an n-layer to be etched and an adjacent p-layer. To provide.

〔課題を解決するための手段〕[Means for solving the problem]

上記の目的を達成するために、本発明は、半導体基板
の一面側にあるn層の表面から隣接するp層との界面ま
で電解エッチングして所定の厚さのダイアフラム部を残
す凹部を形成する工程を含む半導体圧力センサの製造方
法において、前記の電解エッチング工程の前にn層およ
びp層に接触する電極を用いて両層の間のpn接合に逆電
圧を印加することにより両層の間のもれ電流を測定し、
そのもれ電流の値が所定の値より小さい場合にのみ電解
エッチングを行うものとする。
In order to achieve the above object, according to the present invention, a concave portion is formed by electrolytic etching from the surface of an n layer on one surface side of a semiconductor substrate to an interface with an adjacent p layer to leave a diaphragm portion having a predetermined thickness. In the method for manufacturing a semiconductor pressure sensor including a step, a reverse voltage is applied to a pn junction between the two layers by using an electrode in contact with the n-layer and the p-layer before the electrolytic etching step, so that a Measure the leakage current,
Electrolytic etching is performed only when the value of the leakage current is smaller than a predetermined value.

〔作用〕[Action]

電解エッチング工程の前に、エッチングを停止させる
べきpn接合の逆電圧印加時のもれ電流を測定することに
よりAlマスクのばりあるいは接合を貫通する欠陥等に基
づくもれ電流の多い半導体基体を除外することができ、
ストップエッチング時のノンストップの発生が阻止され
る。
Before the electrolytic etching process, the semiconductor substrate with a large leakage current due to the flash of the Al mask or a defect penetrating the junction is measured by measuring the leakage current when the reverse voltage is applied to the pn junction to stop the etching. Can be
The occurrence of non-stop during stop etching is prevented.

〔実施例〕〔Example〕

第1図(a)〜(h)は本発明の一実施例におけるノ
ンストップ発生阻止工程を示し、第2図,第3図と共通
の部分には同一の符号が付されている。第1図(a)に
示すシリコン基板には、第2図の場合と同様にn+層1、
p層2,n層3が形成されているが、n層3にはダイアフ
ラム部に設けられるゲージ抵抗と外周部に集積される付
属回路との分離のためのp+分離拡散層9が存在する。n+
層1の表面を覆うSiO2膜4と露出するp+層9の上にAl膜
10を蒸着する。このAl膜10をレジスト膜81を用いてパタ
ーニングし、p+層9の上にAl電極11を残す(図b)。次
に、Si3N4膜5を全面に被着したのち、レジスト膜82を
用いてAl電極11上のSi3N4膜5を除去する(図c)。一
方、反対面側のSiO2膜4およびSi3N4膜5をレジスト膜8
3を用いてパターニングを行い、n+層1を露出させる
(図d)。次に、ドライエッチングのマスクと電極との
ためにこの面にもAl膜10の蒸着を行う(図e)。ここ
で、レジスト膜84を用いてのAl膜10のパターニングを行
い、凹部を加工すべき部分のAl膜は除去するが、p+分離
層9に対向する部分にはAl電極12を残しておく(図
f)。次いで、第2図と同様にドライエッチングを行
い、n+層1とp層2との界面付近まで粗加工を行い、凹
部71を形成する(図g)。このあと、図式的に示したよ
うに、電極11,12を用いてn+層1とp層2の間に逆電圧V
Rをかけてもれ電流IRを測定する。このIRと、電解エッ
チングの際、n+層1とp層2の界面を超えてエッチング
される深さ、すなわち第3図に示したノンストップエッ
チ量dとの間には第4図に示すような関係がある。ダイ
アフラム部の厚さの許容範囲の規格からノンストップエ
ッチ量の許容範囲d0が決まり、それに対するもれ電流I
R0を事前に求めることができる。第1図(g)における
測定により得られたIRが、Al膜のばりあるいはpn接合を
貫通する欠陥のために大きい場合は、そのシリコン基板
は次の工程に進めない。良品のシリコン基板に次の工程
で表面側に保護板13を当て、裏面側のSi3N4膜5を保護
膜85で覆って電解エッチングを行えば、ほぼn+層1とp
層2との界面でとまるストップエッチングを行うことが
でき、凹部72が形成される(図h)。
FIGS. 1 (a) to 1 (h) show a non-stop generation preventing step in one embodiment of the present invention, and the same reference numerals are given to the parts common to FIGS. 2 and 3. FIG. The silicon substrate shown in FIG. 1 (a), n + layer 1 as in the case of Figure 2,
The p layer 2 and the n layer 3 are formed, and the n layer 3 has ap + isolation diffusion layer 9 for separating a gauge resistor provided in the diaphragm portion from an attached circuit integrated in the outer peripheral portion. . n +
Al film on the SiO 2 film 4 covering the surface of the layer 1 and the exposed p + layer 9
10 is deposited. This Al film 10 is patterned using a resist film 81, leaving an Al electrode 11 on the p + layer 9 (FIG. B). Next, after depositing the Si 3 N 4 film 5 on the entire surface, the Si 3 N 4 film 5 on the Al electrode 11 is removed using the resist film 82 (FIG. C). On the other hand, the opposite SiO 2 film 4 and Si 3 N 4 film 5 are
Patterning is performed using 3 to expose the n + layer 1 (FIG. D). Next, an Al film 10 is deposited on this surface for a dry etching mask and an electrode (FIG. E). Here, patterning of the Al film 10 using the resist film 84 is performed to remove the Al film in the portion where the concave portion is to be processed, but leave the Al electrode 12 in the portion facing the p + separation layer 9. (Figure f). Next, dry etching is performed in the same manner as in FIG. 2, and rough processing is performed up to the vicinity of the interface between the n + layer 1 and the p layer 2 to form a concave portion 71 (FIG. G). Thereafter, as schematically shown, a reverse voltage V is applied between the n + layer 1 and the p layer 2 using the electrodes 11 and 12.
Over the R to measure the current I R leakage. FIG. 4 shows the relationship between this I R and the depth of etching beyond the interface between the n + layer 1 and the p layer 2 during electrolytic etching, ie, the non-stop etching amount d shown in FIG. There is a relationship as shown. The allowable range d 0 of the nonstop etch amount is determined from the standard of the allowable range of the thickness of the diaphragm, and the leakage current I
R0 can be determined in advance. I R obtained by the measurement in FIG. 1 (g) is greater due to defects penetrating the burr or pn junction of the Al film, the silicon substrate is not advanced to the next step. Applying a protective plate 13 on the surface side non-defective silicon substrate in the next step, by performing electrolytic etching to cover the the Si 3 N 4 film 5 on the back surface side protective film 85, approximately n + layer 1 and p
Stop etching that stops at the interface with the layer 2 can be performed, and the concave portion 72 is formed (FIG. H).

〔発明の効果〕〔The invention's effect〕

本発明によれば、電解エッチング前に半導体基体内の
pn接合に逆電圧を印加してもれ電流を測定し、もれ電流
の大きい半導体基体には電解エッチングを施さないこと
により、電解エッチングによる圧力センサダイアフラム
部形成のための凹加工時にもれ電流の影響でエッチング
深さがpn接合を超えることが避けられ、所定の厚さのダ
イアフラム部をもつ圧力センサチップを得るストップエ
ッチングが効率よくできる効果が得られた。
According to the present invention, before electrolytic etching,
The leakage current is measured even when a reverse voltage is applied to the pn junction, and the leakage current is measured during the concave processing for forming the pressure sensor diaphragm by electrolytic etching by not subjecting the semiconductor substrate with large leakage current to electrolytic etching. As a result, the etching depth was prevented from exceeding the pn junction, and the effect of efficiently performing stop etching for obtaining a pressure sensor chip having a diaphragm portion having a predetermined thickness was obtained.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例の凹加工工程を(a)〜
(h)の順に示す断面図、第2図は凹加工のためのドラ
イエッチング工程を示す断面図、第3図は従来の凹加工
のための電解エッチング工程を示す断面図、第4図はpn
接合のもれ電流とノンストップエッチ量との関係線図で
ある。 1:n+層、2:p層、9:p+分離層、11,12:Al電極。
FIG. 1 shows the concave processing step of one embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a dry etching step for concave processing, FIG. 3 is a cross-sectional view showing a conventional electrolytic etching step for concave processing, and FIG.
FIG. 4 is a relationship diagram between a leakage current of a junction and a non-stop etching amount. 1: n + layer, 2: p layer, 9: p + separation layer, 11, 12: Al electrode.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基体の一面側にあるn層の表面から
隣接するp層との界面まで電解エッチングして所定の厚
さのダイアフラム部を残す凹部を形成する工程を含む半
導体圧力センサの製造方法において、前記の電解エッチ
ング工程の前にn層およびp層に接触する電極を用いて
両層の間のpn接合に逆電圧を印加することにより両層間
のもれ電流を測定し、そのもれ電流の値が所定の値以下
の場合にのみ電解エッチングを行うことを特徴とする半
導体圧力センサの製造方法。
1. A method of manufacturing a semiconductor pressure sensor, comprising the step of electrolytically etching a surface of an n-layer on one surface side of a semiconductor substrate to an interface with an adjacent p-layer to form a concave portion leaving a diaphragm portion having a predetermined thickness. In the method, prior to the electrolytic etching step, a leakage current between the two layers is measured by applying a reverse voltage to a pn junction between the two layers using electrodes in contact with the n-layer and the p-layer, A method of manufacturing a semiconductor pressure sensor, wherein the electrolytic etching is performed only when the current value is equal to or less than a predetermined value.
JP393590A 1990-01-11 1990-01-11 Manufacturing method of semiconductor pressure sensor Expired - Lifetime JP2576245B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP393590A JP2576245B2 (en) 1990-01-11 1990-01-11 Manufacturing method of semiconductor pressure sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP393590A JP2576245B2 (en) 1990-01-11 1990-01-11 Manufacturing method of semiconductor pressure sensor

Publications (2)

Publication Number Publication Date
JPH03209778A JPH03209778A (en) 1991-09-12
JP2576245B2 true JP2576245B2 (en) 1997-01-29

Family

ID=11570995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP393590A Expired - Lifetime JP2576245B2 (en) 1990-01-11 1990-01-11 Manufacturing method of semiconductor pressure sensor

Country Status (1)

Country Link
JP (1) JP2576245B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020618A (en) * 1994-03-30 2000-02-01 Denso Corporation Semiconductor device in which thin silicon portions are formed by electrochemical stop etching method
US5677248A (en) * 1994-03-30 1997-10-14 Nippondenso Co., Ltd. Method of etching semiconductor wafers

Also Published As

Publication number Publication date
JPH03209778A (en) 1991-09-12

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