JP3348518B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for performing electrochemical stop etching on a semiconductor substrate which forms a thin portion on a semiconductor such as Si, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, an electrochemical stop etching technique for automatically stopping etching when the thickness of a thin Si portion reaches a predetermined thickness has been used for forming a thin Si portion (diaphragm, etc.) on a semiconductor wafer. ing. In the electrochemical stop etching, a voltage is supplied from the outside, and the thickness of the Si thin portion is adjusted to a desired value by controlling the voltage value. Therefore, this method requires that a voltage be externally supplied to the wafer.

The wafer structure of a conventional semiconductor device used in such an electrochemical stop etching technique will be described below. A case where a diaphragm is formed as a Si thin portion obtained by electrochemical stop etching will be described as an example.

FIG. 2A is a schematic plan view of a semiconductor wafer 20. A plurality of product chip patterns having a diaphragm (not shown) having a predetermined thickness are obtained from a p-type wafer having an n-epitaxial layer formed on the surface. 21 (hereinafter, referred to as chip patterns) are provided on the wafer surface with the scribes 22 interposed therebetween, and a high-concentration n ⁺ region 24 (hereinafter, also referred to as a low-resistance layer 24) Described below) is provided.

[0005] A cross-sectional view of such a semiconductor wafer 20 between chip patterns 21, for example, CC ′ shown in FIG.
The cross-sectional view has a configuration as shown in FIG. The n epitaxial layer 51 is left in the scribe region 22 between the chip patterns 21, and the low resistance layer 52 is provided like the outer peripheral portion 23 of the wafer. Further, an Al wiring 53 for etching is formed directly on the low resistance layer 52. By supplying a positive voltage to the etching Al wiring 53 from the outside, a predetermined portion of each chip pattern 21 is etched to form a diaphragm (not shown).

This is because the relationship between the applied voltage (Vd) and the thickness of the diaphragm, which is derived from the equation of the extension of the depletion layer of the pn junction and the voltage applied to the junction, is obtained by the following equation.

Since it is determined from the equation: t _dia = K (Vd) ^1/2 (K: constant), etching is performed by applying a supply voltage for obtaining a desired diaphragm thickness. When the electrochemical equilibrium is reached, the progress of the etching stops, and a predetermined diaphragm thickness is automatically obtained. Therefore, there is a name of electrochemical stop etching.

The reason why the low resistance layer 52 is diffused in the scribe region 22 is that the etching Al wiring 53 is used.
Even if the wire is broken due to a photo defect or a scratch, the voltage is reliably applied to the n epitaxial layer (not shown) which is an etching region of the diaphragm region (not shown) in the chip pattern 21 by utilizing the low resistance layer 52 at the time of etching. This is for the purpose of being applied. Note that a field oxide film covering the entire scribe area is not formed in the scribe area 22.
This is to prevent the life of a blade (not shown) from being shortened at the time of dicing and cutting in a later step.

With the above-described wafer structure, the same voltage as the external voltage is supplied to the n-epitaxial layer of the diaphragm forming portion of all product patterns. Using the semiconductor wafer 20 having this configuration, the electrochemical stop etching is performed by means as shown in FIG. The non-etched surface of the semiconductor wafer 20 is covered with a protective film
Fixed to In that state, the semiconductor wafer 20
KO so that at least the part to be etched is completely immersed
It is immersed in an etching solution 41 such as H 2. Then, the low resistance layer 24 or the etching Al wiring 53 around the wafer is formed.
Is directly connected to the Pt (platinum) electrode 42, and a positive voltage is supplied to the n epitaxial layer in the diaphragm region in the chip pattern 21. At the same time, a negative voltage or 0 V is supplied to another Pt electrode 43 inserted in the etching solution 41. Thus, a diaphragm is formed on each chip pattern 21 of the semiconductor wafer 20 with a thickness determined by the above equation.

[0009]

As described above, in the conventional semiconductor device, the scribe region 22 between each chip is not provided.
In addition, a high concentration n ⁺ region 24 (low resistance layer) is provided on the wafer outer peripheral portion 23, and an aluminum wiring 53 is provided on the low resistance layer. This is to reduce the difference between the externally supplied voltage value and the voltage value of each chip portion during etching, and to reduce the variation in the finished diaphragm thickness. However, it is not always the case that only a chip of the same pattern (main pattern) is formed in the wafer. For example, as shown in FIG. 2A, a photo alignment recognition pattern 25 (all alignment key, hereinafter AA key) is formed in the wafer. Various TEG (test element group) patterns (not shown) for taking out and testing a part of the main pattern, and electrode patterns (not shown) at the time of anodic bonding for bonding the glass pedestal. A pattern is formed. Since these sub-patterns do not always have the same chip size and the same chip outer peripheral structure as the main chip pattern, the chip arrangement shown in FIGS. 2B and 3C and FIGS. 3A and 3B may be formed. .

2 (b) and 2 (c), the width of the scribe area 22 near the AA key pattern 25, which is usually about 200 to 300 μm, is reduced by the isolation portion 28 of the AA key pattern, Is a state in which the high-concentration n ⁺ region 24 protrudes into the isolation region 28. 3 (a) and 3 (b), the n epitaxial layer 31 in the AA key pattern 30 is used.
Is continued without being separated from a part of the n-epitaxial layer 32 in the scribe region, and the high concentration n of the layers diffused in the AA key pattern 30 for each photolithography process.
^{The case where the +} region 33 overlaps with any of the isolation regions 34 of the AA key pattern is shown.

As described above, in any case, the low resistance layer 24 and the etching aluminum wiring 27 formed on the scribe region 22 and the AA key patterns 25 and 30 are formed.
And the isolation (isolation regions) 28 and 34 in the various TEG patterns and electrode patterns overlap, the withstand voltage of the overlapped portion is about 5V. That is, the low resistance layer 24 in the scribe region 22 and the isolations 28 and 34
Since the withstand voltage between the electrodes becomes 5 V, electrochemical stop etching cannot be performed at a voltage of 5 V or more, and when etching is performed at a voltage higher than this, for example, 7 V, a leak current from the etching Al wiring 27 to the p-type substrate 20 side. (Arrows shown in FIGS. 2 and 3, but the path is not as shown). When such a leak current occurs, the p-type substrate potential in the leak portion increases in a distributed manner, so that in the chip pattern in the vicinity of the leak portion, the target etching voltage is reached quickly and the progress of the etching is stopped quickly,
There has been a problem that the diaphragm becomes thicker than a desired diaphragm thickness, and the chip becomes a defective product.

As a background of the occurrence of such a problem, conventionally, etching such as electrochemical stop etching has not been performed, and recently, in order to perform etching with higher precision, electrochemical stop etching has been performed. In this electrochemical stop etching technology,
This is because a high voltage has been applied to obtain a predetermined film thickness, and a problem has occurred in a portion which has not been a problem in the related art.

Accordingly, an object of the present invention is to propose a semiconductor device and a method of manufacturing the same, which suppress the occurrence of the non-uniform etching variation as described above in electrochemical stop etching.

[0014]

In order to solve the above-mentioned problems, the configuration of the present invention comprises a sub-pattern (A) other than the main pattern.
In contrast to the A key pattern and the TEG pattern, the sub-pattern is surrounded by an isolation region, and the periphery of the isolation region is surrounded by a semiconductor layer (high-concentration second conductivity type low resistance layer) formed by introducing impurities. )). Further, it is characterized by being manufactured in such a structure.

[0015]

By surrounding the periphery of a sub-pattern such as an AA key pattern with an isolation region, no matter what AA key pattern (sub-pattern) is formed, the presence of the isolation region around the sub-pattern causes a scribe region. That is, the voltage supply region during the electrochemical stop etching and the p-type substrate do not become short-circuited, and therefore, no leakage current flows even if any desired etching voltage is applied during the etching. Without etching, uniform etching is performed on each chip pattern.

[0016]

According to the first aspect of the present invention, in the case of a p-type substrate, an isolation region is provided around a sub-pattern formed on the p-type substrate, and an n-epitaxial layer is always provided around the isolation region. Then, since it is a configuration that becomes an n ⁺ low resistance layer, in semiconductor processing using electrochemical stop etching, a voltage is supplied at the time of electrochemical stop etching between the n ⁺ low resistance layer and the isolation. Is maintained, and the etching variation due to the extra leak current is suppressed. Therefore, when a predetermined thickness of the semiconductor is formed, such as when a diaphragm is formed, a uniform product can be obtained with high accuracy, and the utilization efficiency of the semiconductor wafer is improved. This applies to the structure of an epitaxial wafer such as an npn substrate or a pnp substrate.

According to the present invention, the sub-pattern may be an automatic alignment pattern for automatically performing photomask alignment, an electrode pattern at the time of anodic bonding, or various TEG patterns for testing a chip pattern. Therefore, any pattern has an effect of suppressing the etching variation by the configuration of the present invention.

According to the manufacturing method of the third aspect, a semiconductor device having the above configuration can be formed, and a chip which has been rejected in the past can be made into a product with good yield without waste, thereby reducing the manufacturing cost. It is also a factor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments. FIG. 1 shows a p-type wafer structure according to the present invention. FIG. 1 (a) shows a cross section taken along the line AA 'of FIG. 1 (b). As an example, FIG. 1 shows an AA key pattern 10 as a sub-pattern provided while a product pattern 2 is formed on a p-type substrate 1, and an isolation 6 is formed around the AA key pattern 10. A semiconductor layer formed by impurity introduction is not formed around the isolation 6.
If the size of the AA key pattern 10 is larger than the product pattern 2, the configuration of the present invention is provided for a plurality of product pattern areas.

The width of the semiconductor layer without impurity introduction (FIG. 1B)
W) is determined by the breakdown voltage between the isolation 6 around the AA key 10 and the low resistance layer 5 (n ⁺ region). This withstand voltage needs to be equal to or higher than the external supply voltage value at the time of etching, and depends on the impurity concentration of the p-type substrate 1 and the n-type epitaxial layer 4. For example, a value of W is 10 μm and a withstand voltage of 80 V is obtained.

A procedure for forming the structure shown in FIG. 1 will be described. The manufacturing process utilizes a process formed by a conventionally well-known semiconductor manufacturing process, and a feature of the present invention lies in a process of forming the above-described configuration. (1) Form a chip pattern on one side of an n-epitaxial / p-type Si wafer using an AA key pattern for photo alignment, and form an electrode pattern for anodic bonding or various TEG patterns as sub-patterns as necessary I do.
In this case, an isolation area is secured around a sub-pattern such as an AA key pattern. (2) The periphery of the sub-pattern is patterned to form an isolation region. (3) An n ⁺ region serving as a low resistance layer is formed in a predetermined portion of the n epitaxial layer in the scribe region, while leaving a predetermined width from the edge of the n epitaxial layer into which impurities are not introduced. (4) An Al wiring for etching is patterned and formed on the low resistance layer (this step can be omitted). (5) A predetermined portion of the wafer is etched by electrochemical stop etching to obtain a desired shape. (6) Thereafter, a step of separating and commercializing each chip according to a known semiconductor device manufacturing process is performed.

In the structure shown in FIG. 1, the scribe area 3
Does not overlap with the isolation 6 in the AA key pattern 10. Therefore, it is possible to obtain a desired diaphragm thickness uniformly for each chip pattern in the wafer surface without causing a leakage current to flow during electrochemical stop etching, and without making the potential to the substrate non-uniform. .

(Second Embodiment) In addition to the AA key pattern,
Similarly, for various TEG patterns and anodic bonding electrode patterns, these patterns are surrounded by isolation, and a semiconductor layer (n ⁺ low resistance layer or p ⁺ layer) formed by introducing impurities around the isolation is in contact with the TEG pattern. It can be a structure that does not. The present invention can be applied to all semiconductor device formation using electrochemical stop etching.

As described above, the structure of the present invention can be applied not only to the formation of a diaphragm but also to the manufacture of all semiconductor devices for which electrochemical stop etching is performed. Configuration.

The term "impurity introduction" as used herein means, in the case of an n-epitaxial / p-type substrate, the introduction of an impurity for converting the surface of an n-epitaxial layer into an n ⁺ low-resistance layer or a p ⁺ layer. It does not refer to impurities contained in the layer. The sub-patterns include all patterns other than the target product pattern in addition to the patterns described in the second aspect.

[Brief description of the drawings]

FIG. 1 is a schematic structural explanatory view of a wafer in which the present invention is applied to an AA key pattern, (b) is an enlarged plan view of a main part, and (a) is a cross-sectional view taken along line AA ′ of (b). It is.

2A and 2B are explanatory diagrams of a leak current generated in a conventional wafer pattern, wherein FIG. 2A is a plan view of a semiconductor wafer, FIG. 2B is an enlarged plan view of a main part, and FIG. FIG.

3A and 3B are explanatory diagrams of a leak current generated in a conventional wafer pattern, wherein FIG. 3A is an enlarged plan view of a main part, and FIG.
It is D 'sectional drawing.

FIG. 4 is an explanatory diagram of electrochemical stop etching.

FIG. 5 is an explanatory diagram showing a schematic structure of a scribe region for performing electrochemical stop etching.

[Explanation of symbols]

Reference Signs List 1 p-type Si substrate (semiconductor wafer) 2 product pattern (chip pattern) 3 scribe region 4 n epitaxial layer 5 n ⁺ low-resistance layer 6 isolation region 10 AA key pattern (sub-pattern) W n ⁺ from end of low-resistance layer Width of n-epitaxial layer to end of isolation region 20 semiconductor wafer 21 product pattern (chip pattern) 22 scribe 23 wafer outer periphery 24 n ⁺ region (low-resistance layer) 25 AA key pattern (sub-pattern) 26 n-epitaxial layer 27 Al wiring for etching 28 Isolation area of AA key pattern 30 AA key pattern 31 n epitaxial layer in AA key pattern 32 n epitaxial layer in scribe area 33 High concentration n ⁺ area 34 Isolation area of AA key pattern 40 ceramic plate 41 KOH solution 42 Pt (platinum) electrode 43 Other Pt (platinum) electrode 44 Resin 51 n epitaxial layer 52 n ⁺ region (low resistance layer) 53 Al wiring for etching 54 Isolation region of AA key pattern

────────────────────────────────────────────────── ─── Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/306-21/308

Claims (3)

(57) [Claims] 1. A chip pattern of a plurality of main circuits formed on a side of a second conductivity type epitaxial layer by photolithography on a first conductivity type substrate having a second conductivity type epitaxial layer provided on a surface thereof; A scribe region formed on the substrate around the periphery of the chip pattern, a second conductivity type epitaxial layer left in the scribe region, and a high concentration second layer provided in the second conductivity type epitaxial layer. In a semiconductor device having a conduction-type low-resistance layer, instead of forming the chip pattern, an isolation region surrounding a pattern region where a sub-pattern used for another purpose is formed, and a periphery of the isolation region Surrounding the second scribe region and a second conductivity type epitaxial layer continuous with the second conductivity type epitaxial layer in the scribe region; The width of the second conductivity type epitaxial layer from the end of the high concentration second conductivity type low resistance layer included in the region of the second conductivity type epitaxial layer to the end of the isolation region, the electrochemical stop etching during the A semiconductor device having a withstand voltage that can withstand a voltage applied between the high-concentration second conductivity type low-resistance layer and the substrate, and having a withstand voltage determined by the impurity concentration of each layer and the substrate. . 2. The method according to claim 1, wherein the sub-pattern is an automatic alignment pattern for automatically performing photomask alignment, an electrode pattern at the time of anodic bonding, or various TEG patterns for testing a chip pattern. An apparatus according to claim 1. 3. A main circuit is formed on at least one surface of a first conductivity type substrate having a second conductivity type epitaxial layer provided on a surface to form a plurality of chip patterns.
A scribe region formed on the substrate surrounding the outer periphery of the chip pattern; a second conductivity type epitaxial layer of the scribe region; and a high concentration second conductivity type low layer provided in the second conductivity type epitaxial layer. In the method of manufacturing a semiconductor device provided with a resistive layer, instead of forming the chip pattern, surrounding a pattern region where a sub-pattern used for another purpose is formed with an isolation region, Surrounding is surrounded by the second conductivity type epitaxial layer of the scribe region, the width of the second conductivity type epitaxial layer from the end of the high concentration second conductivity type low resistance layer included in the second conductivity type epitaxial layer A withstand voltage that can withstand a voltage applied between the second conductivity type low resistance layer and the substrate, and an impurity concentration of each of the layers and the substrate. Therefore a method of manufacturing a semiconductor device which is characterized in that the width having a determined breakdown voltage.