JPH065583A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device which is capable of satisfactory electrochemical etching without using a high concentration diffusion layer which serves as an electrode for special electrochemical etching. CONSTITUTION:An n type epitaxial layer 36 is formed on a p type single crystal silicon wafer 35 and a p<+> diffusion layer 37, which serves as a piezoresistance layer, is formed in a specified area of the epitaxial layer inside a chip while a p<+> diffusion layer 38 is formed in a scribing line on the epitaxial layer 36 as well. With the p<+> diffusion layer 38 as an electrode, a specified area of the single crystal silicon wafer 35 is removed by electrochemical etching where a specified area of the epitaxial layer 36 is adapted to remain so that a thin wall section may be formed. Furthermore, the wafer on the scribing line is cut so as to produce chips.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art Conventionally, electrochemical etching has been studied for the purpose of etching a thin portion (diaphragm portion) of a diaphragm type pressure sensor or acceleration sensor thinly and with high accuracy. As an example, Japanese Patent Laid-Open No. Sho 6
1-30039 is mentioned. In order to supply a uniform voltage within the wafer surface during electrochemical etching, an n ⁺ type diffusion layer is formed on an n type epitaxial layer formed on a p type single crystal silicon substrate to form an electrode. The diaphragm is formed by removing the silicon substrate by etching and leaving the epitaxial layer.

[0003]

However, in the process of manufacturing the sensor element, it is necessary to form a high-concentration diffusion layer which is an electrode for electrochemical etching which is unrelated to the element.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing good electrochemical etching without using a high-concentration diffusion layer which becomes a special electrode for electrochemical etching.

[0005]

A first aspect of the present invention is a method for manufacturing a semiconductor device having a high-concentration diffusion layer of the first conductivity type in a chip, which is a single-crystal semiconductor substrate of the first conductivity type. A first conductivity type epitaxial layer on which a second conductivity type epitaxial layer is formed.
And a step of forming the high-concentration diffusion layer of the first conductivity type in a predetermined region of the epitaxial layer in a chip,
A second step of forming a high-concentration diffusion layer of the first conductivity type on the scribe line in the epitaxial layer, and a predetermined region of the single crystal semiconductor substrate by electrochemical etching using the high-concentration diffusion layer on the scribe line as an electrode. A gist of a method of manufacturing a semiconductor device is characterized by including a third step of removing a predetermined region of the epitaxial layer, and a fourth step of cutting the scribe line to form a chip.

Further, it is preferable that the second step includes formation of a high-concentration diffusion layer for preventing leakage of the first conductivity type reaching the single crystal semiconductor substrate in the outer peripheral portion of the chip formation region in the epitaxial layer.

A second invention is a method for manufacturing a semiconductor device having a high-concentration diffusion layer in a chip and having metal wiring for wiring to the high-concentration diffusion layer. A first step of forming a second conductivity type epitaxial layer on a conductivity type single crystal semiconductor substrate; a second step of forming the high concentration diffusion layer in a predetermined region of the epitaxial layer in a chip; A third step of arranging a metal wiring for the high-concentration diffusion layer in the chip, and directly joining a metal electrode for etching on a scribe line in the epitaxial layer to form a Schottky junction;
A fourth step of removing a predetermined region of the single crystal semiconductor substrate by electrochemical etching while leaving a predetermined region of the epitaxial layer while applying a forward voltage of a Schottky junction by the etching metal electrode, and a scribe line. The gist is a method of manufacturing a semiconductor device including a fifth step of cutting into chips.

[0008]

In the first invention, the second conductivity type epitaxial layer is formed on the first conductivity type single crystal semiconductor substrate by the first step, and the second conductivity type epitaxial layer is formed in a predetermined region in the chip by the second step. The first-conductivity-type high-concentration diffusion layer is formed, and the first-conductivity-type high-concentration diffusion layer is formed on the scribe line in the epitaxial layer. At this time, the high-concentration diffusion layer of the first conductivity type in the chip and the high-concentration diffusion layer of the first conductivity type on the scribe line can be simultaneously formed. Then, in the third step, a predetermined region of the single crystal semiconductor substrate is removed by electrochemical etching using the high-concentration diffusion layer on the scribe line as an electrode, leaving a predetermined region of the epitaxial layer. Further, in the fourth step, the scribe line is cut into chips.

Further, in the second step, a high-concentration diffusion layer for preventing leakage of the first conductivity type reaching the single crystal semiconductor substrate is formed on the outer peripheral portion of the chip formation region in the epitaxial layer, so that during electrochemical etching. Leakage is prevented.

According to a second aspect of the present invention, an epitaxial layer of the second conductivity type is formed on the single crystal semiconductor substrate of the first conductivity type by the first step, and the epitaxial layer is formed in a predetermined region in the chip by the second step. A high concentration diffusion layer is formed. Then, in the third step, the metal wiring for the high-concentration diffusion layer in the chip is arranged and the etching metal electrode is directly joined to the scribe line in the epitaxial layer to form a Schottky junction. At this time, the metal wiring and the etching metal electrode can be arranged at the same time. Further, in the fourth step, a predetermined region of the single crystal semiconductor substrate is removed by electrochemical etching while applying a forward voltage of the Schottky junction by the etching metal electrode, leaving a predetermined region of the epitaxial layer, and in the fifth step. The scribe line is cut into chips.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a perspective view of a semiconductor acceleration sensor. 2 is a plan view of the semiconductor acceleration sensor,
FIG. 3 shows an AA cross section of FIG. This sensor is used in the ABS system of an automobile.

As shown in FIG. 1, a square plate-shaped silicon chip 2 is placed on a square plate-shaped base 1 made of Pyrex glass. As shown in FIG. 2, the silicon chip 2 has a rectangular frame-shaped first surface whose rear surface is joined to the pedestal 1.
The support part 3 is provided, and the first support part 3 is formed by using the four sides of the silicon chip 2. Four through holes 4a, 4b, 4c, 4d are formed in the first support portion 3 of the silicon chip 2 so as to vertically penetrate therethrough, and the four thin movable portions 5, 6, 7, 8 are thick. It has a structure in which the quadrangular weight parts 9 are connected. Further, in the first support portion 3 of the silicon chip 2, the through hole 1 that penetrates vertically is formed.
0 is formed so as to surround the through holes 4a, 4b, 4c, 4d. The through-hole 10 defines a thick U-shaped second support portion 11 and a thick connecting portion 12.

That is, the second supporting portion 11 is extended with respect to the thick first supporting portion 3 joined to the pedestal 1, and the second supporting portion 11 is provided.
Has a structure in which thin movable parts 5 to 8 are extended. In addition, the through hole 10 allows the first support portion 3 and the second support portion 1 to be formed.
1 has a structure in which it is connected by a connecting portion 12. Further, the second support portion 11 and the weight portion 9 are connected by the movable portions 5 to 8 as described above. The thickness of each of the movable parts 5 to 8 is about 5 μm, and two piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1 are provided in pairs.
6a and 16b are formed. Further, as shown in FIG. 3, a recess 17 is formed in the center of the upper surface of the pedestal 1 so as not to come into contact when the weight 9 is displaced due to acceleration.

FIG. 4 shows a wiring pattern made of aluminum on the surface of the silicon chip 2. In this embodiment, a wiring 18 for grounding, a wiring 19 for applying a power supply voltage, and an output wiring 20 for extracting a potential difference according to acceleration,
And 21 are formed. Also, one more for these wiring
A set of four wires is prepared. That is, the wiring 22 for grounding, the wiring 23 for applying the power supply voltage, and the wirings 24, 25 for outputting for extracting the potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the wiring 19 for applying the power supply voltage, and the wiring 18 for grounding is arranged on the impurity diffusion layer 26 via the silicon oxide film in a crossing state. . Similarly,
The wiring 23 for applying the power supply voltage is connected to the wiring 19 for applying the power supply voltage via the impurity diffusion layer 27, the wiring 22 for grounding is connected to the wiring 18 for grounding via the impurity diffusion layer 28, and The wiring 24 for output is the impurity diffusion layer 2
It is connected to the output wiring 20 via 9. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wiring 1
Wiring using 8 to 21 is performed.

Then, as shown in FIG. 5, each piezoresistive layer 13a, 13b, 14a, 14b, 15a, 15b, 1
The 6a and 16b are electrically connected so as to form a Wheatstone bridge circuit. Here, the terminal 31 is a grounding terminal, the terminal 32 is a power supply voltage applying terminal, and the terminals 33 and 34 are output terminals for extracting a potential difference according to acceleration.

Next, a method of manufacturing the sensor will be described. Figure 6
~ Fig. 11 shows the manufacturing process of the sensor. First, as shown in FIG. 6, a p-type single crystal silicon wafer 35 is prepared,
As shown in FIG. 7, an n-type epitaxial layer 3 is formed on the surface thereof.
6 is formed. Then, as shown in FIG. 8, the p ⁺ diffusion layer 37 is formed in the piezoresistive layer forming region of the epitaxial layer 36, the p ⁺ diffusion layer 38 is formed on the scribe line, and the outer peripheral portion of the chip forming region of the epitaxial layer 36 is formed. The p ⁺ diffusion layers 39 reaching the single crystal silicon substrate 35 are simultaneously formed by heat treatment in an oxygen atmosphere.

Then, as shown in FIG. 9, the p ⁺ diffusion layer 3 is formed.
The aluminum 40 is arranged on the aluminum plate 8 and the pad is extended from a part of the aluminum 40. Subsequently, a plasma nitride film (P-SiN) 41 is formed on the back surface of the single crystal silicon wafer 35, and predetermined patterning is performed by photoetching. Then, a current is supplied to the pad of aluminum 40 to perform electrochemical etching using the p ⁺ diffusion layer 38 as an electrode. That is, when a positive voltage is applied to the p ⁺ diffusion layer 38, a diode structure formed between the p ⁺ diffusion layer 38 and the epitaxial layer 36 becomes forward. Therefore, p
^A current flows from the ⁺ diffusion layer 38 to the epitaxial layer 36, and a potential can be supplied to the epitaxial layer 36.

At this time, p ⁺ is formed on the outer peripheral portion of the chip formation region.
Since the diffusion layer 39 (see FIG. 6) is formed, there is no PN junction portion (indicated by B in FIG. 9) that is reverse biased to the outer peripheral portion of the wafer, that is, the PN junction portion that comes into contact with air, and Leakage is eliminated at the time of chemical etching, a uniform voltage is supplied to the entire surface of the wafer, and a thin film portion having a uniform thickness can be formed.

By such an electrochemical etching, a predetermined region of the single crystal silicon wafer 35 is removed and the groove 42 is formed.
Is formed, a predetermined region of the epitaxial layer 36 remains, and thin movable portions 5, 6, 7, 8 (see FIG. 2) are formed.

Then, as shown in FIG. 10, a predetermined region of the epitaxial layer 36 is removed to communicate with the groove 42.
As a result, the through holes 4a, 4b, 4c, 4d, 10 (see FIG.
(See) is formed. After that, the silicon wafer 35 is anodically bonded onto the pedestal 1 made of Pyrex glass.
Finally, as shown in FIG. 11, the scribe line is diced and cut, and the silicon wafer 35 and the pedestal 1 are cut into a predetermined size as shown in FIG.

As described above, in this embodiment, the n-type epitaxial layer 36 is formed on the p-type single crystal silicon wafer 35 (first conductivity type single crystal semiconductor substrate) (first step), and the inside of the chip is formed. A p ⁺ diffusion layer 37 (first conductivity type high-concentration diffusion layer) to be a piezoresistive layer is formed in a predetermined region of the epitaxial layer 36 in FIG.
A p ⁺ diffusion layer 38 (first-conductivity-type high-concentration diffusion layer) is formed on the scribe line (second step), and the p ⁺ diffusion layer 38 on the scribe line is used as an electrode by electrochemical etching. A predetermined area of the wafer 35 is removed, and a predetermined area of the epitaxial layer 36 is left (the third area).
Process), and the scribe line was cut into chips (fourth process).

In the second step, the p ⁺ diffusion layer 37 in the chip and the p ⁺ diffusion layer 38 on the scribe line can be simultaneously formed. That is, since the p ⁺ diffusion layer 38 that serves as an electrode during electrochemical etching is formed at the same time as the p ⁺ diffusion layer 37, it is possible to form an electrode for electrochemical etching without increasing the number of diffusions. Further, since the p ⁺ diffusion layer 38 is arranged in the region serving as the scribe cut portion, the area inside the chip does not increase due to the arrangement of the p ⁺ diffusion layer 38.

Further, in the second step, by forming the p ⁺ diffusion layer 39 reaching the single crystal silicon wafer 35 on the outer peripheral portion of the chip formation region in the epitaxial layer 36, leakage during electrochemical etching is prevented. . That is, since the p ⁺ diffusion layer 39 is formed on the outer peripheral portion of the chip formation region, the PN reverse biased to the outer peripheral portion of the wafer.
Junction (shown as B in FIG. 9), ie PN in contact with air
The junction does not exist, leakage does not occur during electrochemical etching, a uniform voltage is supplied to the entire surface of the wafer, and a thin film section having a uniform thickness can be formed. Although the PN junction portion formed by the formation of the p ⁺ diffusion layer 39 is exposed on the surface of the epitaxial layer 36, it is not exposed on the surface of the epitaxial layer 36 by the diffusion treatment of the p ⁺ diffusion layer 39 (heat treatment in an oxygen atmosphere). This means that there is no PN junction where a silicon oxide film is formed and which contacts air.

In this way, it is possible to suppress variations in thickness due to leakage at the PN junction during electrochemical etching with a smaller number of steps. The leak preventing p ⁺ diffusion layer 39 may be formed as follows. First, as shown in FIG. 12, p is previously formed on the surface of the single crystal silicon wafer 35.
^{The +} diffusion region 43 is formed and then epitaxially grown to form the epitaxial layer 3 as shown in FIG.
6, the p ⁺ diffusion layer 44 is formed by heat treatment in an oxygen atmosphere. By this heat treatment, the p ⁺ diffusion region 43 of the single crystal silicon wafer 35 extends into the epitaxial layer 36 and p ⁺
It overlaps the diffusion layer 44. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.

14 to 18 show the manufacturing process of the sensor. First, as shown in FIG. 14, an n-type epitaxial layer 46 is formed on a p-type single crystal silicon wafer 45.

Then, as shown in FIG. 15, ap ⁺ diffusion layer 47 is formed in the piezoresistive layer forming region of the epitaxial layer 46. Thereafter, aluminum for wiring to the p ⁺ diffusion layer 47 shown in FIG. 4 is formed, and an aluminum electrode 48 is formed on the scribe line. That is, the aluminum electrode 48 is directly joined to the epitaxial layer 46 to form a Schottky junction. At this time, since the epitaxial layer 46 has a low carrier concentration, it becomes a Schottky junction instead of an ohmic junction, and a forward current of the Schottky diode can flow.

Further, as shown in FIG. 16, a plasma nitride film (P-SiN) is formed on the back surface of the single crystal silicon wafer 45.
49 is formed and a predetermined patterning is performed by photoetching. Then, electrochemical etching is performed using the aluminum electrode 48 on the scribe line as an electrode. That is, a positive voltage is applied to the aluminum electrode 48 to apply a forward voltage of the Schottky junction by the aluminum electrode 48, and electrochemical etching is performed to remove a predetermined region of the single crystal silicon wafer 45 to form the groove 50. In addition, a predetermined region of the epitaxial layer 46 is left.

After that, as shown in FIG. 17, a predetermined region of the epitaxial layer 46 is removed to communicate with the groove 50.
Then, the silicon wafer 45 is anodically bonded onto the pedestal 1 made of Pyrex glass. Finally, as shown in FIG. 18, the scribe line is cut and the silicon wafer 45 and the pedestal 1 are made into chips.

As described above, in this embodiment, the n-type epitaxial layer 46 is formed on the p-type single crystal silicon wafer 45 (first conductivity type single crystal semiconductor substrate) (first step),
A p ⁺ diffusion layer 47 (high concentration diffusion layer) to be a piezoresistive layer is formed in a predetermined region of the epitaxial layer 46 in the chip (second step), and aluminum wiring for the p ⁺ diffusion layer 47 is arranged in the chip. At the same time, the aluminum electrode 48 (metal electrode for etching) is directly joined to the scribe line in the epitaxial layer 46 to form the Schottky junction (third step), and the forward voltage of the Schottky junction by the aluminum electrode 48 is applied. A predetermined region of the single crystal silicon wafer 45 was removed by electrochemical etching, leaving a predetermined region of the epitaxial layer 46 (fourth step), and the scribe line was cut into chips (fifth step).

In the third step, the aluminum wiring and the aluminum electrode 48 can be arranged at the same time.
As a result, the aluminum electrode 48 can be directly formed at the time of forming the wiring aluminum on the p ⁺ diffusion layer 47 for forming the strain gauge without performing diffusion for forming the electrode.

The present invention is not limited to the above-mentioned embodiments, but the conductivity type may be reversed with respect to the above-mentioned embodiments.

[0033]

As described above in detail, according to the present invention,
It exerts an excellent effect that good electrochemical etching can be performed without using a high-concentration diffusion layer serving as a special electrode for electrochemical etching.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plane surface of a semiconductor acceleration sensor.

3 is a cross-sectional view taken along the line AA of FIG.

FIG. 4 is a plan view of a silicon chip showing a wiring pattern.

FIG. 5 is a diagram showing connection of resistance layers.

FIG. 6 is a plan view of a silicon wafer.

FIG. 7 is a diagram showing a manufacturing process of the sensor according to the first embodiment.

FIG. 8 is a diagram showing a manufacturing process of the sensor.

FIG. 9 is a diagram showing a manufacturing process of the sensor.

FIG. 10 is a diagram showing a manufacturing process of the sensor.

FIG. 11 is a diagram showing a manufacturing process of the sensor.

FIG. 12 is a cross-sectional view showing an application example of the first embodiment.

FIG. 13 is a cross-sectional view showing an application example of the first embodiment.

FIG. 14 is a diagram showing a manufacturing process of the sensor according to the second embodiment.

FIG. 15 is a diagram showing a manufacturing process of the sensor.

FIG. 16 is a diagram showing a manufacturing process of the sensor.

FIG. 17 is a diagram showing a manufacturing process of the sensor.

FIG. 18 is a diagram showing a manufacturing process of the sensor.

[Explanation of symbols]

35 p-type single crystal silicon wafer as a first conductivity type single crystal semiconductor substrate 36 epitaxial layer 37 p ⁺ diffusion layer as a first conductivity type high concentration diffusion layer 38 as a first conductivity type high concentration diffusion layer p ⁺ diffusion layer 39 p ⁺ diffusion layer 45 p type single crystal silicon wafer as a first conductivity type single crystal semiconductor substrate 46 epitaxial layer 47 p ⁺ diffusion layer as a high concentration diffusion layer 48 as a metal electrode for etching Aluminum electrode

Claims (3)

[Claims] 1. A method for manufacturing a semiconductor device having a high-concentration diffusion layer of the first conductivity type in a chip, comprising: an epitaxial layer of the second conductivity type on a single crystal semiconductor substrate of the first conductivity type. Forming a first conductive type high-concentration diffusion layer in a predetermined region of the epitaxial layer in a chip, and forming a first conductive-type high-concentration diffusion layer on a scribe line in the epitaxial layer. And a second step of forming a high concentration diffusion layer on the scribe line as an electrode,
A third step of removing a predetermined region of the single crystal semiconductor substrate by electrochemical etching to leave a predetermined region of the epitaxial layer, and a fourth step of cutting the scribe line into chips. Of manufacturing a semiconductor device. 2. The second step includes the step of forming a high-concentration diffusion layer for preventing leakage of the first conductivity type reaching the single crystal semiconductor substrate, in the outer peripheral portion of the chip formation region in the epitaxial layer. Of manufacturing a semiconductor device of. 3. A chip having a high-concentration diffusion layer, and
A method for manufacturing a semiconductor device having a metal wiring for wiring to the high-concentration diffusion layer, comprising forming a second conductivity type epitaxial layer on a first conductivity type single crystal semiconductor substrate. A second step of forming the high-concentration diffusion layer in a predetermined region of the epitaxial layer in a chip, arranging metal wiring for the high-concentration diffusion layer in the chip, and a scribe line in the epitaxial layer A third step of directly joining the etching metal electrode to form a Schottky junction, and a predetermined region of the single crystal semiconductor substrate by electrochemical etching while applying a forward voltage of the Schottky junction by the etching metal electrode. And a fourth step of leaving a predetermined region of the epitaxial layer, and a fifth step of cutting the scribe line into chips. Method of manufacturing a semiconductor device is characterized in that a degree.