JP3156681B2 - Semiconductor strain sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor acceleration sensor or a semiconductor pressure sensor (hereinafter, referred to as a semiconductor strain sensor).

[0002]

2. Description of the Related Art FIG. 8 shows an example of a conventional integrated semiconductor strain sensor. This sensor has an N-type epitaxial layer 10
1 and a P-type polished substrate 106 having junction-separated N-type epitaxial layer regions 103, 104, and 105. The N-type epitaxial layer region 103 has a P ⁺ piezoresistive region. 107 are formed, and bipolar transistors are formed in the N-type epitaxial layer regions 104 and 105.

[0005] In order to form a thin strain-generating portion A including the epitaxial layer region 103, a concave groove 108 is formed immediately below the epitaxial layer region 103. Groove 1
08 is formed by applying a voltage between an electrode facing the substrate 102 and the P-type polishing substrate 106 in an etching solution and performing electrochemical etching.

In this integrated semiconductor strain sensor, the epitaxial layer 10 is formed by using a bonded substrate technique.
1 is provided by stopping the anisotropic etching at the junction interface of the epitaxial layer 101,
This is for accurately controlling the thickness of the thin strain generating portion A, that is, the depth of the concave groove 108.

[0005]

However, the above-mentioned conventional integrated semiconductor strain sensor is extremely disadvantageous in cost due to its complicated structure. Further, at the time of electrochemical etching, it is necessary to make an electrode contact on the surface of the P-type polishing substrate 106 on the side where the active element is formed, which causes a problem that the structure is further complicated.

In order to solve the above-mentioned problem, as shown in FIG.
It is also conceivable to form the thin-walled strain-generating portions A and the concave grooves 108 by directly forming the layers 03, 104, and 105 and stopping the anisotropic etching at the junction interface of the epitaxial layer region 103. However, in this case, since the bottom surface 103a of the epitaxial layer region 103 is exposed, the bottom surface 103a of the epitaxial layer region 103 is contaminated, and the PN junction interface between the epitaxial layer region 103 and the P-type substrate 102 is contaminated. Resulting in. As a result, a potential change occurs in the epitaxial layer region 103, and this potential change causes a potential change in the piezoresistive region 107 through the junction depletion layer capacitance, thereby lowering the SN ratio of the sensor.

In the above-described semiconductor strain sensor, there is a case where it is desired to change the thickness of the thin strain generating portion without changing the planar shape of the thin strain generating portion. For that purpose, conventionally, it was necessary to change the thickness from the bottom surface of the epitaxial layer for stopping the anisotropic etching to the surface on the piezoresistive region side. For example, in the conventional example of FIG. 8, it is necessary to change the thickness of the substrate 106 or the epitaxial layer 101, and in the conventional example of FIG. 9, it is necessary to change the thickness of the epitaxial layer 101.

However, such a change in the thickness of the substrate 106 or the epitaxial layer 101 requires a significant process change. Considering the semiconductor manufacturing process, it would be very convenient in terms of manufacturing steps if it was possible to manufacture a plurality of types of semiconductor strain sensors having thin-walled strain-generating portions having different thicknesses by the same semiconductor manufacturing process.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor strain sensor which has a simple structure and does not cause the above-described contamination of the epitaxial layer region (surface layer region).

[0010]

In order to achieve the above object, according to the first aspect of the present invention, a semiconductor substrate of a second conductivity type and a predetermined thickness are formed on a surface portion of the semiconductor substrate on a first main surface side. A first conductive type surface layer region having a second conductive type piezoresistive region formed on the surface portion thereof; and a thin strain strain including the surface layer region formed by electrochemical etching from the second principal surface side of the semiconductor substrate. In the semiconductor strain sensor comprising a portion, the thin strain generating portion is formed of the semiconductor substrate having a predetermined thickness, covers a bottom surface of the surface layer region, and forms a coating region exposed on the second main surface side. Yes, and the covered area
The thickness of the surface layer and the half
It is formed between the conductive substrate and extends toward the semiconductor substrate.
It is characterized by being larger than the width of the junction depletion layer .

[0011]

According to the second aspect of the present invention, a semiconductor substrate of the second conductivity type and a surface layer region of the first conductivity type formed at a predetermined thickness on the first main surface side of the semiconductor substrate and having a piezoresistive region. And a semiconductor strain sensor comprising a thin strain generating portion formed by electrochemical etching from the second main surface side of the semiconductor substrate and including the surface layer region, wherein the thin strain generating portion includes the surface layer region and the surface layer region. It consists of the semiconductor substrate of a predetermined thickness covering the bottom surface, and the thickness of this covering region is
When the maximum rated voltage is applied, the surface region and the semiconductor substrate
A junction depletion layer formed between the semiconductor substrate and extending to the semiconductor substrate side
It is characterized by being larger than the width .

[0013]

According to the third aspect of the present invention, a semiconductor substrate having two regions of opposite conductivity types, a thin strain generating portion formed by electrochemical etching from one surface of one of the semiconductor substrates, In the strain generating portion, in a semiconductor strain sensor including a pressure-sensitive element formed on the other semiconductor substrate, the thin strain generating portion is configured to include two conductive type regions of the semiconductor substrate , semiconductor
The thickness of the substrate is the thickness of the semiconductor substrate when the maximum rated voltage is applied.
The other semiconductor substrate formed between two conductivity type regions.
The width is larger than the width of the junction depletion layer extending to the side .

[0015]

Since the present invention has the above-described configuration, the thin strain generating portion covers the bottom surface of the surface layer region (semiconductor substrate) having the piezoresistive region (pressure-sensitive element region). This covering region protects the surface layer region and the PN junction interface between the surface layer region and the semiconductor substrate from contamination.

Therefore, the semiconductor strain sensor of the present invention reduces the contamination of the surface layer region without employing a complicated structure such as a bonded substrate technique, and reduces the SN of the sensor output.
The ratio can be prevented from lowering.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor acceleration sensor according to the present invention will be described below with reference to the drawings.

In FIG. 1, a silicon chip 1 is bonded on a perforated pedestal 11 made of Pyrex glass.
The pedestal 11 is joined on the stem 12. Reference numeral 13 denotes a metal can, which is welded to the periphery of the stem 12 to form an airtight reference pressure chamber S inside.

The inner ends of the terminal pins 14 fixed to the holes of the stem 12 by seal glass are individually connected to respective bonding pads (not shown) on the silicon chip 1 by wires 15. Groove 1 on the back of silicon chip 1
a is formed, and a measured pressure introducing hole 11a is formed in the concave groove 1a through the pedestal 11 and the stem 12, respectively.
The pressure to be measured is introduced through 12a.

The groove 1a is formed by anisotropic etching described later, and the thin portion of the silicon chip 1 which is in contact with the groove 1a is hereinafter referred to as a thin strain generating portion A. This silicon chip 1 includes a Wheatstone bridge circuit composed of two pairs of piezoresistive regions (two shown in FIG. 2), and a bipolar integrated circuit constituting an amplifier circuit for amplifying the output signal and a temperature compensation circuit. Is formed.

FIG. 2 showing a cross section of the silicon chip 1
The structure of the semiconductor strain sensor according to the present embodiment will be described with reference to FIG. However, FIG. 2 is a cross-sectional view of a portion of the piezoresistive region R, and FIG. In FIG. 2, a pair of piezoresistive regions R are actually formed on the surface of the thin-walled strain-generating portion A around the thin-walled strain-generating portion A. FIG. 2 shows only the piezoresistive regions R and R in the peripheral portion of the thin strain generating portion A.

The silicon chip 1 has a crystal axis of (110)
A plurality of N ⁻ epitaxial layer regions 31 and 32 separated from each other by a P ⁺ separation region 3 are provided on the surface of the semiconductor substrate 2. , 33 are formed. The epitaxial layer region 31 constitutes the surface region according to the present invention, and the epitaxial layer regions 32 and 33 constitute the active region according to the present invention.

On the surface of the epitaxial layer region 31,
The above-described two pairs of piezoresistive regions R are formed, and bipolar transistors T1 and T2 are individually formed in the epitaxial layer regions 32 and 33, respectively. Each of these bipolar transistors constitutes a first stage transistor of the differential amplifier. Of course, other epitaxial layer regions (not shown) which are insulated from each other by the P ⁺ isolation region 3 are formed on the surface of the silicon chip 1, and resistors and other transistors are formed in these epitaxial layer regions. Have been.

Between the bottom surface 31a of the epitaxial layer region 31 and the bottom surface of the concave groove 1a, a covering region 4 of a predetermined thickness made of the semiconductor substrate 2 is formed.
And the epitaxial layer region 31 covered by the covering region 4 constitutes the thin strain generating portion A according to the present invention.
In addition, reference numeral 5 denotes an aluminum wire connecting one end of the piezoresistive region R and one end of each of the bipolar transistors T1 and T2, and is formed on the silicon oxide film 6. Aluminum wire 6
Are connected to the piezoresistive region R through the opening of the silicon oxide film 6.
And other contact portions. Reference numeral 7 denotes a passivation film made of a plasma silicon nitride film, and reference numeral 7a denotes an opening for wire bonding.

[0026] the N ^- the surface of the epitaxial layer region 31, as shown in FIG. 3, N ⁺ contact region 81 is formed, N ⁺ aluminum wire 82 having one end connected to the contact region 81 is a chip peripheral area It is extended above.
Further, a passivation film 7 is formed on the chip peripheral region.
The aluminum wire 82 exposed from the opening 7b is used as an electrode during electrochemical etching. In addition,
After the electrochemical etching and before the wafer scribe, the opening 7b may be covered and protected with an insulating film such as polyimide.

The thin-walled strain-generating portion A is distorted by the pressure difference applied to the thin-walled strain-causing portion A, and the piezoresistive region R changes.

Hereinafter, a manufacturing process of this sensor will be described with reference to FIG.

First, a P substrate 2 is prepared, an N ⁺ buried region 71 is diffused, an N-type epitaxial layer is epitaxially grown, and each piezoresistive region R and a transistor T1,
T2 and other elements are formed. That is, using a normal bipolar integrated circuit manufacturing process, the piezoresistive regions R,
P ⁺ isolation region 3, NPN transistors T1 and T2 and respective resistors are formed, and thereafter, a silicon oxide film 6, a contact opening thereof, an aluminum wire 5, a P-SiN passivation film 7, 8 and a wire bonding An opening 6a and an opening 6b for electrochemical etching are sequentially formed.

Next, the plasma nitride film (P-SiN) 8 on the surface of the region where the groove 1a is to be formed is selectively opened.

Next, the wafer 40 is electrochemically etched.

FIGS. 4 and 5 show this electrochemical etching step.
This will be described with reference to FIG.

First, a hot plate (200
C., not shown), a resin wax W is placed on this support substrate 46 to soften it, and a platinum ribbon 5 is further placed thereon.
The main surface of the wafer 40 on the side where the piezoresistive region is formed is placed on and bonded to the wafer 9 with the power supply electrode (not shown) and the platinum ribbon 59 in contact with each other. Then, the supporting substrate 46
Then, the resin wax W is cured by lowering the wafer 40 from the hot plate. The tip of the platinum ribbon 59 is formed in a wavy shape,
In the cured state of the resin wax W, the platinum ribbon 59
Is pressed by its own elasticity to the aluminum contact portion of the opening 6b or the above-described power supply electrode (not shown), and good electrical contact is obtained. Note that the resin wax W covers the side surface of the wafer 40.

In this state, the wafer 40 and the supporting substrate 46 are suspended in the etching bath 61 and immersed in an etching solution (for example, a 33 wt% KOH solution, 82 ° C.). A platinum electrode plate 62 is hung down facing the main surface of the wafer 40 on which the piezoresistive region is not formed, and a predetermined etching voltage (here) is applied between the platinum ribbon 59 and the platinum electrode plate 62 with the wafer 40 side being positive. In this case, 10 V) is applied to perform electrochemical etching. In this way, an electric field for reverse biasing the junction between the two is formed from the platinum ribbon 59 through the epitaxial layer region 31 to the P-type substrate 2, and the substrate 2 is subjected to electrochemical etching (anisotropic etching). A concave groove 1a is formed in the substrate 2. When the etching reaches the vicinity of the junction between the substrate 2 and the epitaxial layer region 31, an anodic oxide film (not shown) is formed, and the etching rate is remarkably reduced, so that the etching is stopped near this junction.

Next, the support substrate 46 is placed on a hot plate to soften the resin wax W, the wafer 40 is separated from the support substrate 46, and the separated wafer 40 is immersed in an organic solvent (for example, trichloroethane). The wax 40 is dissolved and washed, and the wafer 40 is taken out. Next, a plasma nitride film (P
-SiN) 8 and then dicing the wafer 40 into chips. This chip is bonded on the pedestal 11 by an electrostatic bonding method, and wire bonding is performed.

In this embodiment, the impurity concentration of the substrate 2 is set to 1 ×
10 ¹⁵ atoms / cm ³ , the impurity concentration of the epitaxial layer region 31 is 2 × 10 ¹⁵ atoms / cm ³ , and the maximum rated voltage (maximum allowable voltage) applied between the epitaxial layer region 31 and the substrate 2 is: The depletion layer formed by applying the maximum rated voltage does not reach the surface of the covering region 4. For this reason, even when the device is used at the maximum rated voltage, the leakage current does not flow through the epitaxial layer region 31, and the potential fluctuation of the epitaxial layer region 31 due to the thermal noise current or the popcorn noise current affects the piezo resistance region R through the junction capacitance. There is almost no.

In this case, the width of the portion of the junction depletion layer extending toward the substrate 2 (depletion layer width on the substrate 2 side) wp is determined by the following equation for single crystal silicon. wp ² = 2KεVt / (qNa (1 + Na / Nd)) where K is the relative permittivity of silicon, ε is the vacuum permittivity, Vt
Is the sum of the applied voltage Vc and the barrier voltage at the time of 0 bias, q is the electron charge amount, Na is the impurity concentration of the P-type substrate 2, and Nd is the impurity concentration of the epitaxial layer region 31.

According to an experiment described later, the thickness of the thin strain generating portion A after the etching is equal to the thickness of the epitaxial layer region 31.
It is known that it is equal to the sum of the depletion layer width wp on the substrate 2 side. Therefore, the thin-walled strain-generating portion A having a desired thickness can be accurately obtained only by adjusting the applied voltage without changing the semiconductor manufacturing process, and the surface of the epitaxial layer region 31 is protected from contamination and minute scratches. It is possible to obtain a coating region 4 of sufficient thickness to protect. Naturally, the thickness t of the covering region 4 is substantially equal to the width wp of the depletion layer.

FIG. 6 shows a change in the thickness of the thin strain generating portions 5 to 8 when the thickness of the epitaxial layer region 31 is 6 μm and the applied voltage Vc is changed in the above embodiment. Also,
The sum of the depletion layer width wp on the substrate 2 side and the thickness of the epitaxial layer region 31 is shown as a characteristic line. From FIG. 6, it can be seen that the thickness of the thin-walled strain generating portions 5 to 8 is equal to wp + t. (Experimental Example 2) In the above embodiment, the thickness of the epitaxial layer region 31 was 6 μm, the applied voltage Vc was 2 V, and the epitaxial layer
The impurity concentration of the region 31 is set to 7 × 10 ¹⁵ atoms / cm ³ ,
FIG. 7 shows a change in the thickness of the thin strain generating portion A when the impurity concentration of the substrate 2 is changed. The sum of the depletion layer width wp on the substrate 2 side and the thickness of the epitaxial layer region 31 is shown as a characteristic line.

FIG. 7 shows that the thickness of the thin strain generating portion A is equal to the thickness of the epitaxial layer region 31 and the width wp of the depletion layer. However, even if the electrochemical etching reaches the end of the junction depletion layer, if the applied voltage is 0.6 V or less, the anodic oxide film is not formed well on the etching surface, and the etching does not stop. It is necessary to apply a voltage higher than the minimum voltage.

Further, in the above embodiments, the description has been given of a single crystal silicon substrate. However, it is obvious that the present invention can be applied to other semiconductor materials. Also, it is obvious that the present invention can be applied to an acceleration sensor as a semiconductor strain sensor. In the sensor of the present embodiment described above, an N ⁺ contact region is formed on the surface of the epitaxial layer region 31 and power is supplied to this N ⁺ contact region through the aluminum wire 82. Alternatively, the current may be supplied to the epitaxial layer region 31 through a polysilicon line). Also,
An N ⁺ buried region may be formed on the bottom surface 31a of the epitaxial layer region 31.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor pressure sensor according to one embodiment of the present invention.

FIG. 2 is a sectional view of a chip of the sensor of FIG. 1;

FIG. 3 is a sectional view of a chip of the sensor of FIG. 1;

FIG. 4 is a sectional view showing an electrochemical etching step.

FIG. 5 is a front view showing the periphery of the wafer of FIG. 4;

FIG. 6 is a characteristic diagram showing a relationship between an applied voltage and a thickness of a thin strain generating portion in the etching of FIG.

FIG. 7 is a characteristic diagram showing a relationship between an impurity concentration of a substrate and a thickness of a thin strain generating portion in the etching of FIG.

FIG. 8 is a sectional view of a chip of a semiconductor pressure sensor according to a conventional example.

FIG. 9 is a cross-sectional view of a chip of a semiconductor pressure sensor according to a conventional example.

[Explanation of symbols]

 Reference Signs List 2 semiconductor substrate 4 covering region 31 epitaxial layer region (surface layer region) 32, 33 epitaxial layer region (active region) A thin-walled strain-generating portion R piezoresistive region T1, T2 transistor (active element)

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mineichi Sakai 1-1-1, Showa-cho, Kariya-shi, Aichi Pref. DENSO Corporation (56) References JP-A-63-65679 (JP, A) 183190 (JP, A) JP-A-59-13377 (JP, A) JP-A-4-179181 (JP, A) JP-A-4-219936 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 29/84 G01L 9/04 101 H01L 21/3063

Claims (3)

(57) [Claims] A first conductive type semiconductor substrate; a first conductive type piezoresistive region formed on a surface of the semiconductor substrate on a first main surface side at a predetermined thickness and having a second conductive type piezoresistive region on the surface;
In a semiconductor strain sensor comprising: a conductive type surface layer region; and a thin strain generating portion formed by electrochemical etching from the second main surface side of the semiconductor substrate and including the surface region, wherein the thin strain generating portion has a predetermined thickness. together consist of the of the semiconductor substrate, covering the bottom surface of the surface layer region, and have a coverage area that is exposed to the second main surface, the thickness of the coating region
When the maximum rated voltage is applied, the surface layer and the semiconductor
A bond formed between the substrate and the semiconductor substrate and extending to the semiconductor substrate side
A semiconductor strain sensor having a width larger than a width of a depletion layer . 2. A semiconductor substrate of a second conductivity type having a predetermined thickness formed on a first main surface side of the semiconductor substrate.
A first conductivity type surface layer having an erosion resistance region, and electrochemical etching from a second main surface side of the semiconductor substrate.
And a thin strain generating portion including the surface layer region formed by
In the semiconductor strain sensor, the thin-walled strain-generating portion forms the surface layer region and a bottom surface of the surface layer region.
The semiconductor substrate having a predetermined thickness to be coated;
The thickness of the region is the same as the surface region when the maximum rated voltage is applied.
Formed between the semiconductor substrate and the semiconductor substrate.
A semiconductor strain sensor having a width greater than the width of the junction depletion layer . 3. It has two regions of opposite conductivity type respectively.
A semiconductor substrate, and electrochemical etching from one surface side of the semiconductor substrate
Formed on the other semiconductor substrate at the thin strained portion formed by
And a pressure-sensitive element, wherein the thin strain-generating portion includes two conductive-type regions of the semiconductor substrate.
The thickness of the one semiconductor substrate is set to a maximum value.
Between the two conductivity type regions of the semiconductor substrate when a rated voltage is applied
A junction depletion layer formed and extending to the other semiconductor substrate side
A semiconductor strain sensor having a width larger than a width of the semiconductor strain sensor.