JP3225622B2 - Thin semiconductor dynamic sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensor for converting a dynamic quantity into an electric quantity through a strain amount, such as a semiconductor acceleration sensor or a semiconductor pressure sensor (hereinafter referred to as a semiconductor dynamic sensor).

[0002]

2. Description of the Related Art A conventional semiconductor dynamic sensor has a strain-generating portion of a first conductivity type at least one end of which is supported by a semiconductor substrate of a second conductivity type, and is formed on one surface of the strain-generating portion to respond to a change in stress. And a piezoresistive region of the second conductivity type, the resistance of which changes in the resistance value.

[0003]

In order to increase the sensitivity of the above-described semiconductor dynamic sensor, for example, a semiconductor acceleration sensor, conventionally, the thickness of a strain-generating portion generally formed to have a thickness of 30 to 40 μm is reduced to 10 μm. Is most effective. However, according to experiments performed by the present inventor, it was found that such thinning of the strain-causing portion caused fluctuations in the output voltage of the bridge and a significant increase in noise voltage, making it impractical.

According to the analysis and the experimental results, it has been found that the cause is that the tip of the junction depletion layer reaches the back surface of the thin strained portion. That is, on the back surface of the strain generating part,
A planar depletion layer or a second conductivity type channel (hereinafter referred to as a back channel) is formed, and a large number of recombination centers, levels, traps, and the like are formed due to contamination. Further, the end of the semiconductor substrate of the same conductivity type as the piezoresistive region is located on the same straight line as the back surface of the strain-induced portion by the electrochemical etching method.

As a result, when the junction depletion layer reaches the back surface of the strained portion, the reverse bias current (hereinafter, referred to as leakage current) between the piezoresistive region and the strained portion increases, and the back channel and the above-described channel. A leak current flows between the piezoresistive region and the substrate through the junction depletion layer, and a leak current flows between the substrate and the piezoresistive region by direct punch-through without passing through the back channel.

When the thickness of the strain generating portions 5 to 8 is large as in the prior art, the depletion layer cannot reach the back surface of the strain generating portion in a normal operating voltage range. It was not necessary to consider the size of the junction depletion layer between the resistance region and the strain generating portion. In the case where the strain-generating portion of the second conductivity type is formed on the substrate of the first conductivity type, there is no positive short circuit between the substrate and the strain-generating portion.
It can be considered that a short circuit occurs due to a parasitic resistance at the end face of the N junction or the like.

Therefore, the leak current flows from the piezoresistive region through the substrate to the strain generating portion. Note that the strain-generating portion is normally connected to one end of the piezoresistive region, and even when not connected, one end of the piezoresistive region has a zero bias barrier potential. The leak current is added to the signal current flowing through the piezoresistive region and output.

This leak current contains a large amount of thermal noise (proportional to the square root of R), fluctuation noise, 1 / f noise and popcorn noise, and has a large fluctuation due to an unstable current path, and is largely influenced by temperature changes. The fluctuation rate is also large, causing a level fluctuation of the sensor output voltage and a decrease in the S / N ratio. In addition,
Such leakage current can be reduced by reducing the voltage applied to both ends of the piezoresistive region, that is, between the one end of the piezoresistive region and the thin strain generating portion. Changes cause inconsistency with the power supply voltage of the peripheral circuit, so that a new power supply device or a circuit change is required, which causes a problem that the consistency with the signal processing circuit in the subsequent stage is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems that occur when the strain-generating portion is thinned, and maintains good matching with peripheral circuits, and suppresses fluctuations in output voltage and reduction in S / N ratio. It is an object of the present invention to provide a thin semiconductor dynamic sensor that suppresses the thickness and improves the sensor sensitivity by reducing the thickness of the strain generating portion.

[0010]

According to a first aspect of the present invention, there is provided a thin semiconductor dynamic sensor, wherein at least one end thereof is supported by a semiconductor substrate and has a thickness of 15 μm or less and is made of a first conductive type single crystal semiconductor; A piezoresistive region formed on the surface of the thin-walled strain-generating portion and formed of a second conductivity type semiconductor having an impurity concentration of at least one digit higher than that of the thin-walled strain-generating portion; In a semiconductor dynamic sensor that detects a change in resistance value of the piezoresistive region by applying a predetermined rated voltage between the thin-strained portion and another input terminal of the piezoresistive region, the thin-strained portion is , K is the relative permittivity of the thin strain generating portion and the piezoresistive region portion, ε is the vacuum permittivity, Vc is the rated voltage, and Vo is 0 between the thin strain generating portion and the piezoresistive region at 0 bias. Barrier voltage, q
Is the charge amount of electrons, and W is the thickness d of the thin strain-generating portion, and the depth of the piezoresistive region is 2Kε (Vc + Vo) /
It is characterized by having an impurity concentration higher than q (wd) ² .

According to a second aspect of the present invention, there is provided a thin semiconductor dynamic sensor, wherein at least one end is supported by a semiconductor substrate and a thin strain generating portion made of a first conductivity type single crystal semiconductor is formed on a surface portion of the thin strain generating portion. A piezoresistive region portion made of a conductive semiconductor, and applying a predetermined rated voltage between one input terminal of the piezoresistive region portion and the other input terminal of the thin strain generating portion and the piezoresistive region portion. In the semiconductor dynamic sensor for detecting a change in the resistance value of the piezoresistive region, a high-concentration first- conductivity-type depletion-layer stopper region is provided on the back surface of the thin-walled strain generating portion.

Note that the piezoresistive region portion is composed of one or a plurality of piezoresistive regions connected to each other. The application of a predetermined rated voltage between one input end of the piezoresistive region and between the thin-walled strain generating portion and the other input end of the piezoresistive region is performed by applying a rated voltage to both input ends of the piezoresistive region. This includes the case where the potential of the thin strain generating portion is fixed via the zero bias barrier potential of the PN junction between one input end of the resistance region and the thin strain generating portion.

[0013]

According to the first aspect of the present invention, the thickness of the thin strain generating portion is reduced to 10 μm or less, and the impurity concentration N of the thin strain generating portion is set to 2Kε (Vc + Vo) / q (wd).
² or more. As a result, the rated voltage V of this sensor
In c, the junction depletion layer between the piezoresistive region and the thin strained portion cannot reach the back surface of the thin strained portion, and as a result,
The above-described leakage current becomes extremely small. For this reason, for example, the output voltage fluctuation and the S / N ratio depending on the magnitude of the leakage current are maintained while maintaining good matching with peripheral circuits such as a power supply device. In a state where the reduction is suppressed, the sensor sensitivity can be improved by reducing the thickness of the strain generating portion.

In the second invention, a high-concentration second conductivity type depletion layer stopper region is provided on the back surface of the thin strain generating portion. As a result, the junction depletion layer between the piezoresistive region and the thin strain-generating portion is shielded by the high-concentration first conductivity type depletion layer stopper region on the back surface of the thin strain-generating portion. Cannot be reached, so that the leakage current detailed above is very small. Therefore, it is possible to improve the sensor sensitivity by reducing the thickness of the strain generating portion in a state where the fluctuation of the output voltage and the decrease of the S / N ratio depending on the magnitude of the leak current are suppressed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor acceleration sensor to which the present invention is applied will be described below with reference to the drawings. FIG. 1 is a perspective view of the semiconductor acceleration sensor, FIG. 2 is a plan view of the semiconductor acceleration sensor, and FIG. 3 is a cross-sectional view taken along line AA of FIG.
This sensor is used for an ABS system of a vehicle.

A square plate-shaped silicon chip 2 is bonded on a square plate-shaped pedestal 1 made of Pyrex glass. The silicon chip 2 has a rectangular frame-shaped first support portion 3 whose back main surface is joined to the pedestal 1, and the first support portion 3 is formed using four sides of the silicon chip 2. An upper isolation groove 4 is provided inside the first support portion 3 of the silicon chip 2.
a, 4b, 4c, 4d and a lower separation groove 10 are recessed, and the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10 communicate with each other to form a through groove penetrating the chip 2. . A C-shaped upper separation groove 4d and a lower separation groove 10 below the upper separation groove 4d formed in the first support portion 3 having a rectangular frame shape.
Thick second support portion 11 and thick connecting portion 1
2 is defined and formed, and the second support portion 11 is connected to the first support portion 3 by the connection portion 12. Further, the second support portion 1
A thin, thin, strained portion 5, 6, 7, 8 extends from the inner surface of 1 and a thick, square weight portion 9 is connected to the tip of the thin, strained portion 5, 6, 7, 8. Have been.

That is, the second supporting portion 11 is connected to the thick first supporting portion 3 joined to the pedestal 1 via the connecting portion 12,
The weight portion 9 from the second support portion 11 via the thin strain portions 5 to 8
Are supported at both ends. The lower separation groove 10 is formed below the upper separation grooves 4a, 4b, 4c, 4d and the thin strain generating portions 5 to 8, and communicates with the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10. , A through groove penetrating the chip 2.

The two piezoresistive regions 13a, 13b, 14a, 14b, 15
a, 15b, 16a and 16b are formed. Further, as shown in FIG. 3, a concave portion 17 is formed at the center of the upper surface of the pedestal 1 so that when the acceleration 9 is applied and the weight portion 9 is displaced, no contact is made. FIG. 2 shows an aluminum wiring pattern on the surface of the silicon chip 2.

A wiring 18 for grounding, a wiring 19 for applying the power supply voltage Vcc, and wirings 20 and 21 for output for extracting a potential difference according to acceleration are laid. or,
Another set of four wirings is prepared for these wirings. That is, the ground wiring 22, the power supply voltage applying wiring 23, and the output wirings 24 and 25 for extracting a potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the power supply voltage application wiring 19, and the ground wiring 18 crosses the impurity diffusion layer 26 via a silicon oxide film. Similarly, the power supply voltage application wiring 23 is connected to the power supply voltage application wiring 19 via the impurity diffusion layer 27, and the ground wiring 22 is connected to the ground wiring 18 via the impurity diffusion layer 28. Further, the output wiring 24 is connected to the output wiring 20 via the impurity diffusion layer 29. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the connection using the wirings 18 to 21 is made.

Each piezoresistive region 13a, 13b, 14
a, 14b, 15a, 15b, 16a, and 16b constitute a Wheatstone bridge circuit as shown in FIG. 4; a terminal 31 is a ground terminal; a terminal 32 is a power supply voltage application terminal; 33 and 34 are output terminals for extracting a potential difference according to the acceleration. Next, a method for manufacturing this sensor will be described with reference to FIGS. 5 to 9 show the AA cross section of FIG.

First, as shown in FIG.
0) p-type substrate (second conductivity type semiconductor portion in the present invention)
A wafer (semiconductor member according to the present invention) 40 having an n-type epitaxial layer (semiconductor portion of the first conductivity type according to the present invention) 42 on a 41 is prepared, and the piezoresistive regions 13a, 13
b, 14a, 14b, 15a, 15b, 16a, 16b
The p ⁺ diffusion layer 43 is formed, and the upper isolation grooves 4a, 4b, 4 are formed as electrode contacts during electrochemical etching.
An n ⁺ diffusion layer 44 is formed on the surface of the region where c and 4d are to be etched, and a ground n ⁺ diffusion layer (not shown) for grounding the epitaxial layer 42 is not etched on the epitaxial layer 42. It is formed on the surface of the region.

Thereafter, a silicon oxide film (not shown) formed on the epitaxial layer 42 is selectively opened, and aluminum wirings 18 to 25 (see FIG. 2, not shown in FIGS. 5 to 8) are formed thereon. . Also, the aluminum wirings 18 to 25 are p ⁺
A contact is made with a predetermined position of the diffusion layer 43, and thereafter, a passivation insulating film (not shown) made of a silicon oxide film or the like is deposited, and the passivation insulating film is selectively opened to form a contact hole for wire bonding. Then, the passivation insulating film is opened and n
⁺ An energizing aluminum contact portion (not shown) for contacting diffusion layer 44 is provided.

Next, a plasma nitride film (P-Si) is formed on the back surface of the wafer 40, that is, on the surface of the substrate 41 (the back main surface in the present invention) except for the region to be etched of the lower isolation groove 10.
N) 45 is formed and the plasma nitride film 45 is photo-patterned using a resist film (not shown) not shown. Next, a resist film (resist film according to the present invention) 49 is spin-coated on the front main surface of the wafer 40, that is, the surface of the epitaxial layer 42 which is to be etched in the upper isolation grooves 4a, 4b, 4c, and 4d. Photo-patterning. The upper separation grooves 4a, 4b, 4c,
The silicon oxide film and the passivation insulating film on the region to be etched 4d have been removed in advance, and the above-mentioned current-carrying aluminum contact portions are exposed on the surface of the epitaxial layer 42 exposed by the photo-patterning of the resist film 49. I have. The resist film 49 is made of PIQ
(Polyimide) film.

Next, as shown in FIG. 6, the lower isolation groove 10 is formed by performing electrochemical etching of the wafer 40. Hereinafter, this electrochemical etching will be described in detail.
First, a hot plate (200 ° C., not shown) is joined to the back surface of the support substrate 46, the resin wax W is placed on the support substrate 46 to soften it, and a platinum ribbon (not shown) is further placed thereon.
After that, the front main surface of the wafer 40 is placed and bonded, and then the support substrate 46 and the wafer 40 are lowered from the hot plate to cure the resin wax W. The tip of the platinum ribbon is formed in a wavy shape, and in the cured state of the resin wax W, the tip of the platinum ribbon is pressed against the aluminum contact by its own elasticity, and good electrical contact is made with the aluminum contact. . Note that the resin wax W is
0 side surfaces.

In this state, the wafer 40 and the supporting substrate 46 are suspended in an etching bath (not shown) and immersed in an etching solution (for example, a 33 wt% KOH solution, 82 ° C.). A platinum electrode plate (not shown) is suspended facing the back main surface of the wafer 40, and a predetermined voltage (here, 2V) is applied between the platinum ribbon and the platinum electrode plate with the wafer 40 side being positive.
Is applied to perform electrochemical etching. By doing so, the platinum ribbon is converted to the aluminum contact portion and the n ⁺ diffusion layer 4.
4. An electric field is formed in the P-type substrate 41 through the epitaxial layer 42 to reverse bias the junction between the two,
The substrate 41 is subjected to electrochemical etching (anisotropic etching), and the lower isolation groove 10 is formed in the substrate 41. When the etching reaches the vicinity of the junction between the substrate 41 and the epitaxial layer 42, an anodic oxide film (not shown) is formed, and the etching rate is remarkably reduced, so that the etching is stopped near this junction.

Next, as shown in FIG. 7, after the nitride film 45 is removed with hydrofluoric acid, the support substrate 46 is placed on a hot plate to soften the resin wax W, and the wafer 40 is separated from the support substrate 46. The wafer 40 thus obtained is immersed in an organic solvent (for example, trichloroethane), the resin wax W is dissolved and washed, the wafer 40 is taken out, and then a resist 50 is applied to the entire back main surface of the wafer 40.

Since the resist 50 is not used for photo-patterning, it is only necessary to allow the resist solution to flow down. As in the case of resist application for photo-patterning (for example, the second resist film 49), a spinning device is used. It is not necessary to vacuum chuck the wafer 40 on the spinning table. Next, as shown in FIG. 8, the epitaxial layer 42 is dry-etched from the opening of the second resist film 49 to form upper isolation grooves 4a, 4b, 4c and 4d.

Next, as shown in FIG. 9, the resist film 49 is removed by oxygen ashing, and the resist 50 is removed to complete the upper separation grooves 4a, 4b, 4c, 4d. The through grooves are formed by communicating the lower separation grooves 10 with 4c and 4d. Subsequently, the wafer 40 is bonded on the pedestal 1, and finally is diced into chips.

The design of a high-sensitivity sensor capable of reducing leakage current, which is a main part of the present embodiment, will be described below in order with reference to FIG. (Determination of Thickness of Thin Wall Strained Sections 5 to 8) In this embodiment, the bridge sensitivity of the sensor is set to 0.7 mV / G. From this target bridge sensitivity, the thickness T of the thin strain parts 5 to 8 is determined based on the relationship between the bridge sensitivity and the thickness of the thin strain parts 5 to 8 shown in FIG. Here, it is understood that T may be set to 5.3 μm. (Determination of Bridge Input Voltage) In this embodiment, the piezoresistive regions 13a, 13b, 14a, 14b, 15a, 15
The bridge input voltage Vcc applied between the high-order input terminal and the low-order input terminal of the bridge formed by connecting b, 16a, and 16b as shown in FIG. 4 is 12 V, and the low-order input terminal of the bridge is grounded.

This is to realize simplification of the power supply device, simplification of wiring, and compatibility with the signal processing circuit device at the subsequent stage using the same power supply voltage. In this state, the thin strain generating portions 5 to 8 constitute a junction diode with the piezoresistive region, that is, the P ⁺ region 43, so that the potential of the thin strain generating portions 5 to 8 is a value higher than the barrier potential between the two (about 0. 7V), but in this specification, it is assumed that the potentials of the thin strain generating portions 5 to 8 are approximately equal to the highest potential of the P ⁺ region 43.

It should be noted that the substrate 41 and the thin strain generating portions 5 to 8 are connected to each other.
The substrate 41 is in a resistance connection state at the
Equivalent to the axial layer 42 (thin strain parts 5 to 8)
Can be In addition, the surface of the epitaxial layer 42
To n⁺Forming a region, this n⁺The area is aluminum wiring 19,
23 may be connected. This n⁺The area is n⁺Region 44 and
It can be formed by the same process. This way, Epita
By suppressing the potential fluctuation of the axial layer 42,
Output signal voltage can be suppressed. Of course, above
n ⁺The power supply voltage, that is, the aluminum wirings 19 and 23
It is possible to give different DC potentials, but in this case
Has an input terminal for fixing the potential of the epitaxial layer 42 and
Only requires a new power supply, which only complicates the equipment configuration
That's not a good idea. That is, the high input terminal 3 of the bridge
2 and the epitaxial layer 42 at the same potential (or
It is easiest to fix to the same potential. (Determination of Impurity Concentration of Substrate 41)
According to the ching, an experimental characteristic diagram of FIGS.
From the epitaxial layer 42 and the substrate 41
It may be considered to stop at the end of the junction depletion layer on the substrate 41 side.
Therefore, in this embodiment, the impurity concentration of the substrate 41 is set to 3 × 1
0¹⁷Atom / cm^ThreeSet to.

That is, when used as a sensor, P
⁺ Region 43 and the epitaxial layer 42 (thin strain generating portions 5 to 5)
8), when the junction depletion layer reaches the back surface of the thin strain parts 5 to 8, the above-described leakage current increases. Therefore, the thickness of the epitaxial layer 42 needs to be as large as possible. The thickness of the strain generating portions 5 to 8 needs to be much thinner than before.

Therefore, in order to make the stop position of the electrochemical etching as close as possible to the junction between the epitaxial layer 42 and the substrate 41, it is necessary to reduce the portion of the junction depletion layer extending to the substrate 41 side.
Must be as high as possible. On the other hand, according to the experiment, when the impurity concentration of the substrate 41 is 2 × 10 ¹⁸ atoms / cm ³ , the etching rate is reduced, and
1 is known to be difficult to etch. On the other hand, when the applied voltage is 0.6 V or less, the etching rate increases, and it becomes difficult to stop the etching.

Therefore, the impurity concentration of the substrate 41 is set to 1
When the density is at least 10 ¹⁶ atoms / cm ³ and at most 2 10 ¹⁸ atoms / cm ^{3, and} more preferably 1 to 8 × 10 ¹⁷ atoms / cm ³ , a synergistic effect of increasing sensitivity and suppressing leakage current will be obtained. be able to. (Determination of the Thickness of the Epitaxial Layer 42) The thickness we of the epitaxial layer 42 is obtained by calculating the thickness of the thin strain generating portions 5 to 8 by T =
Assuming that the thickness of the unetched portion (remaining P-type region) of the substrate 41 is 5.3 μm and the thickness of the remaining portion is wb, T-wb is obtained. wb is determined as follows.

The impurity concentration of the substrate 41 is set to Nb (3 × 10 ¹⁷
Atoms / cm ³ ), the impurity concentration N of the epitaxial layer 42
e, the width wb of the portion of the junction depletion layer extending toward the substrate 41 between the substrate 41 and the epitaxial layer 42 is expressed as: wb ² = 2Kε (Vc + Vo) / (qNb (1 + Nb /
Ne)). Here, K is the relative dielectric constant of silicon, ε is the vacuum dielectric constant, Vc is the applied voltage in electrochemical etching, and Vo is the epitaxial layer 42 at zero bias.
Voltage between the substrate and the substrate 41, q is the amount of electron charge,
An assumed value is used for Nb. (Determination of Impurity Concentration and Depth of P ⁺ Region 43) Piezoresistive regions P ^- 13a, 13b, 14a, 14b, 15a,
The depth d of the P ⁺ regions 43 constituting the layers 15b, 16a, and 16b can be determined in advance, and is assumed to be 1.0 μm here. The impurity concentration of the P ⁺ region 43 is higher than that of the n-type epitaxial layer by one digit or more. This prevents the junction depletion layer between the P ⁺ region 43 and the n-type epitaxial layer 42 from extending into the P ⁺ region 43, and
This is for the purpose of, for example, reducing the change in the resistance value of the P ⁺ region 43 due to the fluctuation in the potential. Further, the impurity concentration of the P ⁺ region 43 is too high, the resistance value becomes smaller, can not be ignored electric resistance such as aluminum wiring, there is adverse effects is not negligible temperature rise due to the current increase, whereas, the P ⁺ region If the impurity concentration of 43 is too low, the resistance noise of each piezoresistor increases, and the ratio of the signal current to the leakage current increases, resulting in an increase in the S / N ratio. From these, here, the impurity concentration of the P ⁺ region 43 is:
1 × 10 ²⁰ atoms / cm ³ .

Therefore, it is assumed here that the junction depletion layer between P ⁺ region 43 and epitaxial layer 42 all extends to epitaxial layer 42 side. Effective thickness w of the epitaxial layer 42 immediately below the (epitaxial layer 42 determine the impurity concentration of) P ⁺ region 43 is obtained by subtracting the depth d of the P ⁺ region 43 in the thickness we of the epitaxial layer 42.

When the junction depletion layer DL between the P ⁺ region 43 and the epitaxial layer 42 reaches the back surfaces of the thin strain parts 5 to 8, the leakage current and the noise voltage are greatly increased as described above. In order to prevent this, the width wdl of the junction depletion layer DL needs to be smaller than w = we−d = T−wb−d. The width wdl of the junction depletion layer DL can be calculated by the following equation.

Wdl ² = 2Kε (Vcc + Vo) / (qNe (1 + Ne / Np)) = 2Kε (Vcc + Vo) / (qNe) Therefore, Ne = 2Kε (Vcc + Vo) / (q × w)
dl ² ) where Np is the impurity concentration of the P ⁺ region 43 and Ne is the impurity concentration of the N-type epitaxial layer 42. For safety, wdl is set to a value smaller by 1 μm than the effective thickness w of the beam thickness.

In the above calculation, if Ne assumed at the stage of (determination of the thickness of the epitaxial layer 42) is significantly different from Ne obtained here, the assumed value of Ne is corrected again to calculate. You have to start over. Hereinafter, an example of the data calculated in this manner is described below. Applied voltage V
cc is 12 V, the impurity concentration of the substrate 41 is about 3 × 10 ¹⁷ atoms / cm ³ , and the impurity concentration of the epitaxial layer 42 is about 7
× 10 ¹⁵ atoms / cm ³ , the impurity concentration of the P ⁺ region 43 is about 1 × 10 ²⁰ atoms / cm ³ , the thickness T of the thin strain generating portions 5 to 8 is about 5.3 μm, and the depth of the P ⁺ region 43 Is about 1.0 μm, and the junction depletion layer Wdl is about 1.5 μm.

Next, the above-described increase in leakage current is confirmed.
The experimental results are shown in FIG. 14 and FIG.
Based on the schematic sectional view of FIG. 16 and the simplified equivalent circuit diagram of FIG.
A description will be given below. However, the measurement was performed on the sample shown in FIG.
Was. In this apparatus, the impurity concentration of the substrate 41 is about 3 × 10¹⁷
Atom / cm^Three, The impurity concentration of the epitaxial layer 42 is about
7 × 10^FifteenAtom / cm^Three, P⁺The impurity concentration of the region 43 is
About 1 × 10²⁰Atom / cm ^ThreeAnd the thickness T of the thin-walled strain-generating portion 5 is
Approximately 2.5 μm, which is approximately equal to the thickness of the
P⁺The depth of the region 43 is about 1.0 μm. Epitaxial layer
42 for grounding⁺An area was provided.

A variable Vcc is provided between this and P ⁺ region 43.
Was applied and the leakage current was examined. FIG. 14 showing the result
From that Vcc at which the tip of the junction depletion layer approaches the back surface is 11
The leak current a starts to increase remarkably from the point a exceeding V,
At 30 V breakdown of the PN junction occurs. Incidentally, the width (calculated value) of the junction depletion layer between the P ⁺ region 43 and the epitaxial layer 42 on the epitaxial layer 42 side at Vcc = 11 V in the above specifications is about 1.5 μm.

Next, the relationship between the leakage current and the variation in the bridge output voltage was examined using three samples A, B, and C. The result is shown in FIG. However, details of samples A, B, and C are as follows. Specifications are the same as above. However, the thickness of the thin strain generating portion is 3.5 μm for A and B for B
Is 3.0 μm and C is 2.5 μm. From FIG. 15, it can be seen that when the leak current starts to increase sharply, the variation in the output voltage of the bridge sharply increases.

When the junction depletion layer reaches the back surface of the thin strain generating portion 5, the N ⁺ region 44, the epitaxial layer 42, the substrate 4
1. It was found that the leakage current increased and the bridge output voltage varied due to the flow of current in the order of the back channel, the junction depletion layer, and the P ⁺ region 43. Of course, the noise voltage also increases. (Experimental Example 1) In the electrochemical etching shown in FIG. 6, the thickness t of the epitaxial layer 42 was 6 μm, and the applied voltage Vc
FIG. 11 shows a change in the thickness of the thin-walled strain generating portions 5 to 8 when the thickness is changed.
Shown in The sum of the depletion layer width wp on the substrate 41 side and the thickness t of the epitaxial layer 42 is shown as a characteristic line.

From FIG. 11, the thickness of the thin strain parts 5 to 8 is wp
It can be seen that it coincides with + t. (Experimental Example 2) In the electrochemical etching shown in FIG. 6, the thickness t of the epitaxial layer 42 was 6 μm, and the applied voltage Vc
Is 2V, and the impurity concentration of the epitaxial layer 42 is 7 × 10
FIG. 12 shows a change in the thickness of the thin strain generating portions 5 to 8 when the impurity concentration of the substrate 41 is changed to ¹⁵ atoms / cm ³ . The depletion layer width wp on the substrate 41 side and the epitaxial layer 42
Is shown as a characteristic line.

From FIG. 12, the thickness of the thin strain parts 5 to 8 is wp
It can be seen that it coincides with + t. From the above experimental results, in order to make the thickness T of the thin strain parts 5 to 8 the designed thickness, T = t
It can be seen that + wp is sufficient. (Embodiment 2) Another embodiment will be described with reference to FIG.

In this embodiment, the n-type epitaxial layer 42
A thin n ⁺ epitaxial layer (depletion layer stopper region) 70 is formed between the substrate and the p-type substrate 41. In this manner, the junction depletion layer between P ⁺ region 43 and epitaxial layer 42 is blocked by n ⁺ epitaxial layer 70 and cannot reach back surface 72 of thin strain-causing portion 5, resulting in a leak current Increase and noise voltage increase can be suppressed.

This n⁺The epitaxial layer 70
In the initial stage of the taxi layer 42, the impurity doping amount is increased.
Can be formed. Also, P⁺Surface of substrate 41
To P ⁺N-type impurity whose diffusion rate is faster than that of the substrate 41
In the epitaxial process of the epitaxial layer 42.
It may be formed by autodoping in the above. Note that n⁺
Impurity of epitaxial layer (depletion layer stopper region) 70
The concentration is 5 × 10¹⁶Atom / cm^ThreeAbove, preferably 1 ×
10¹⁷~ 1 × 10²⁰Atom / cm^ThreeIt is said.

[Brief description of the drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plan view of the semiconductor acceleration sensor.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a bridge circuit diagram of the sensor.

FIG. 5 is a sectional view showing a manufacturing process of the sensor of FIG. 1;

FIG. 6 is a sectional view showing a manufacturing process of the sensor of FIG. 1;

FIG. 7 is a sectional view showing a manufacturing process of the sensor of FIG. 1;

FIG. 8 is a sectional view illustrating a manufacturing process of the sensor of FIG. 1;

FIG. 9 is a sectional view showing a manufacturing process of the sensor of FIG. 1;

FIG. 10 is a schematic sectional view of a sensor.

11 is a characteristic diagram showing the relationship between the thickness of a thin strain generating portion (beam) of the sensor of FIG. 1 and bridge sensitivity.

FIG. 12 is a characteristic diagram showing a relationship between an applied voltage in electrochemical etching and a thickness of a thin strain generating portion.

FIG. 13 is a characteristic diagram showing a relationship between an impurity concentration of a substrate and a thickness of a thin strain generating portion in an electrochemical etching method.

FIG. 14 is a characteristic diagram showing a relationship between an applied voltage and a leak current.

FIG. 15 is a characteristic diagram showing a relationship between a leak current and a bridge output voltage.

FIG. 16 is a schematic sectional view showing a path of a leak current.

FIG. 17 is a sectional view showing Example 2.

[Explanation of symbols]

41 semiconductor substrate 5-8 thin-walled strain generating portion 13a, 13b, 14a, 14b, 15a, 15b, 1
6a, 16b Piezoresistive region (piezoresistive region) 43 P ⁺ region (piezoresistive region) 70 n ⁺ layer (depletion layer stopper region)

Continuation of the front page (56) References JP-A-60-253279 (JP, A) JP-A-2-116174 (JP, A) JP-A-56-104475 (JP, A) JP-A-50-65180 (JP, A) JP-A-61-91967 (JP, A) JP-A-62-54477 (JP, A) JP-A-58-78470 (JP, A) JP-A-4-196176 (JP, A) 61-111583 (JP, A) JP-A-63-76483 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01P 15/12 G01L 1/18 G01L 9/04 H01L 29 / 84

Claims (6)

(57) [Claims] 1. A thin strain-generating portion made of a first-conductivity-type single-crystal semiconductor having a thickness of 15 μm or less supported at least at one end by a semiconductor substrate; and a thin strain-generating portion formed on a surface portion of the thin strain-generating portion. Of 1
A piezoresistive region portion made of a second conductivity type semiconductor having an impurity concentration of an order of magnitude higher than that of the piezoresistive region portion. A thin semiconductor dynamic sensor that detects a change in the resistance value of the piezoresistive region by applying a predetermined rated voltage between the thin piezoresistive region and the piezoresistive region. Relative dielectric constant, ε is a vacuum dielectric constant, Vc is the rated voltage, Vo is a barrier voltage between the thin strain generating portion and the piezoresistive region at 0 bias, q is an electron charge, W
Wherein the thickness d of the thin strain generating portion is the depth of the piezoresistive region, and the impurity concentration is higher than 2Kε (Vc + Vo) / q (wd) ^2. Sensor. 2. A thin strain-generating portion made of a first-conductivity-type single-crystal semiconductor, at least one end of which is supported by a semiconductor substrate; and a piezoresistive-region portion formed on a surface of the thin-walled strain-generating portion and made of a second conductivity-type semiconductor. A predetermined rated voltage is applied between one input terminal of the piezoresistive region and the other input terminal of the thin strain generating portion and the other input end of the piezoresistive region to change the resistance value of the piezoresistive region. in thin semiconductor dynamic sensor for detecting, thin semiconductor dynamic sensor, characterized in that a depletion layer stopper region of the first conductivity type high-concentration on the rear surface portion of the thin strain generating part is disposed. 3. The semiconductor substrate according to claim 1, wherein said semiconductor substrate has an impurity concentration of 1 × 10.
¹⁶ Atom / cm ^Three More than 2 × 10 ¹⁸ Atom / cm ^Three The following
The thin semiconductor dynamic sensor according to claim 1. 4. The depletion layer stopper region has an impurity concentration of
5 × 10 ¹⁶ Atom / cm ^Three 3. The thin film according to claim 2,
Semiconductor dynamic sensor. 5. The method according to claim 1, wherein the piezoresistive region portions are one or more.
And a plurality of piezoresistors connected to the piezoresistor.
One input end of the resistance region, the thin strain generating portion, and the piezo resistor.
Applying a predetermined rated voltage between the other input terminals of the resistance area
Applies a rated voltage to both input terminals of the piezoresistive area.
And one input end of the piezoresistive region section and the thin strain generating section.
Through the PN junction of the PN junction with the
Claims including fixing the potential of the distorted portion.
Item 5. A thin semiconductor dynamic sensor according to any one of Items 1 to 4. 6. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a substrate of a second conductivity type.
The method according to any one of claims 1 to 5, wherein
Thin semiconductor dynamic sensor.