JP2800235B2 - Semiconductor pressure sensor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor pressure sensor, and more particularly to a semiconductor pressure sensor having a small electric influence.

[Conventional technology]

Conventionally, utilizing the fact that the resistance value changes due to the piezo resistance effect by applying mechanical stress, a part of the single crystal silicon substrate is made thinner to form a diaphragm, and the pressure applied to the diaphragm 2. Description of the Related Art A semiconductor pressure sensor that measures a pressure by deforming a strain gauge and detecting a change in resistance value by a piezoresistance effect is widely known.
In particular, in the semiconductor pressure sensor described in JP-A-61-239675, a buried insulator layer is provided between a semiconductor substrate on which a piezoresistive layer is formed and a semiconductor layer serving as a support portion of the semiconductor pressure sensor. In addition, a method of suppressing a bimetal operation caused by a thin diaphragm portion and another insulating layer formed on the surface thereof is adopted.

[Problems to be solved by the invention]

However, in the above-mentioned semiconductor pressure sensor, since the thickness of the buried insulator layer sandwiched between the semiconductor substrate and the semiconductor layer is very thin, about 1-2 μm, dicing for dividing the wafer into chips is performed. When the semiconductor substrate and the semiconductor layer come into contact with each other, even after the product becomes a normal product, if the water droplets or dust adhere to the vicinity of the outer peripheral side surface of the buried insulator layer, or the semiconductor substrate and the semiconductor layer may be disturbed due to noise or the like. If a voltage higher than the creeping discharge start voltage is applied during this time, the semiconductor substrate and the semiconductor layer conduct, and an external potential is led to the semiconductor substrate. As a result, the semiconductor pressure sensor drive power supply and various circuits are integrated. This causes a problem in that an interaction is caused between the circuit of the one-chip pressure sensor and a malfunction or a change in output.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor pressure sensor capable of reliably performing electrical insulation between a semiconductor pressure sensor support and a semiconductor substrate.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, there is provided a semiconductor having a first semiconductor region, a second semiconductor region, and a first insulator layer embedded between the first and second semiconductor regions. A substrate; a concave portion formed on the second semiconductor region side from a main surface of the second semiconductor region of the semiconductor substrate; and a strain detecting portion formed on the first semiconductor region side corresponding to the concave portion. A circuit element formed in a region different from the recess on the first semiconductor region side; and a rectangular ring shape surrounding the distortion detecting section and the circuit element at the same time, wherein the first insulating A trench extending from the first semiconductor region in the thickness direction of the semiconductor substrate so as to penetrate the body layer and reach the inside of the second semiconductor region; and a thermal oxidation formed on the entire inner surface of the trench. Through the film and the thermal oxide film And a polycrystalline silicon formed so as to be buried in the entire inside of the trench. The dicing cut is performed so that the portion in which the polycrystalline silicon is buried is exposed to the outside over the entire side surface side of the semiconductor substrate. And formed into a chip state.

〔Example〕

 Hereinafter, the present invention will be described with reference to embodiments shown in the drawings.

1 (a) to 1 (g) are cross-sectional views showing a first embodiment of the present invention. In FIG. 1A, 1 is a smooth single-crystal N-type silicon semiconductor substrate having a (100) plane, and 2 is an oxide film (0.2-1 μm thick) formed by wet oxidation at 1000 ° C. SiO ₂ )
It is. Reference numeral 3 denotes a single crystal P-type silicon semiconductor substrate having a (100) plane having a specific resistance of 100 to 20 Ω · cm, and this substrate is bonded by direct wafer bonding (for example, nitrogen) as shown in FIG. Alternatively, bonding is performed at 1100 ° C. for 1 hour in an oxidizing atmosphere. Next, as shown in FIG. 1 (c), after polishing the P-type silicon semiconductor substrate 3 by lapping, a mirror polished surface is finished to a thickness of 5 to 100 μm. Subsequently, an N ^* buried layer 4 is formed by ion implantation, and an N-type epitaxial layer 5 of 5 to 15 μm is formed thereon.

Subsequently, as shown in FIG. 1D, so-called trench etching is performed over the N-type epitaxial layer 5, the P-type silicon semiconductor substrate 3, the oxide film (SiO ₂ ) 2, and the silicon semiconductor substrate 1. Next, an oxide film (SiO ₂ ) 6 is formed to a thickness of 0.2 to 1 μm on the surface and in the trench by thermal oxidation, and subsequently, poly (polycrystalline) Si 7 is embedded in the trench, and the surface is smoothed by polishing the surface. Do.

Next, as shown in FIG. 1 (e), a normal bipolar IC
Depending on the process, elements such as an isolation layer 8, a bipolar transistor 9, a diode 10, and a P-type piezoresistive layer 1
1. An oxide film 12 is formed. Then, as shown in FIG. 1 (f), a contact hole is made in the oxide film 12, and an Al oxide layer 13 and a passivation film 14 are formed. Here, the device formation region is insulated from the substrate by the oxide films 2 and 6. Further, a region serving as a diaphragm of the pressure sensor is removed with an etching solution such as KOH to form a concave portion 15. It goes without saying that the etching may be performed until the oxide film 2 is reached. Next, dicing is performed on a portion indicated by a dotted line in the drawing with a dicing saw to obtain a chip state as shown in FIG. 1 (g). In addition, in order to stabilize the characteristics of the pressure sensor, anodic bonding may be performed with Pyrex glass (product name) having substantially the same thermal expansion coefficient as that of the Si wafer, and a pedestal portion may be formed in a wafer state and then diced into a chip state. .

According to this embodiment, in the semiconductor pressure sensor shown in FIG. 1 (g), the substrate 3 on which the device including the piezoresistive layer 11 is formed is insulated and separated from the substrate 1 by the oxide film 2 and the oxide film 6. Therefore, it is possible to prevent water droplets and dust from directly adhering to the substrate at the side surface 2a of the insulator layer 2, and the two substrates 1 and 3 do not conduct. Although an oxide film is used for the insulator layer 6, the electric field concentration is reduced by using a material having a smaller dielectric constant than the oxide film. As another structure, an oxide film is used for the insulator layer 6, and instead of the oxide film 2, a material having a high dielectric constant such as a nitrogen oxide film (large dielectric constant), an oxide film, or a nitrided oxide film is used. By using an insulator having a three-layer structure, an electric field is reduced and electric characteristics are improved. Even when the sensor is affected by noise or the like, the electric influence from the substrate 1 to the substrate 3 can be reduced.

Specifically, the semiconductor pressure sensor shown in FIG. 1 (g) is installed and used in a device 100 having a structure as shown in FIG. 2, and this device 100 detects an intake air pressure. Therefore, when mounted directly on the surge tank 200 or the like of an automobile, foreign particles such as moisture and dust entering the surge tank 200 also enter the device 100 as shown by the arrow in the figure, and this is When dew condensation reaches the substrate 1 of the semiconductor pressure sensor, it is affected by an unstable body earth level. However, according to the semiconductor pressure sensor of the above embodiment, since the potential of the substrate 1 does not affect the potential of the substrate 3, highly accurate pressure detection can be performed even in such a case.

In FIG. 2, reference numeral 101 denotes a housing in which the pressure sensing unit 102 is housed. The pressure sensing unit 102 includes a glass pedestal 105 and a semiconductor pressure sensor 106 shown in FIG. 1 (g) in a can package in which a stem 103 and a cap 104 are welded, and an electric signal from the semiconductor pressure sensor 106 is externally provided. A wire 107 and a hermetically sealed lead 108 are led out of the semiconductor pressure sensor 106 to guide the lead. The electric signal led to the lead 108 is further led to an external device via the lead 109. Reference numeral 110 denotes an O-ring for sealing.
Reference numeral 11 denotes a pressure introduction pipe whose tip is bent inward in order to prevent foreign particles entering from the pressure introduction port 112 from being guided to the semiconductor pressure sensor 106 as much as possible. Reference numeral 113 denotes a through condenser.

Further, according to the present embodiment, in addition to the above-described effects, the following effects are also obtained. That is, in this embodiment, since the oxide film 6 is formed on the surface of the hole (trench) formed by the trench etching and then the hole is filled with PolySi7, the formation of the Al wiring layer 13 after the formation of the oxide film 6 is performed. During the process or the like, a process such as a resist can be stably flowed without a substance such as a resist entering the hole. Further, for example, when the hole (trench) is formed mechanically, the oxide film 6 is formed by a thermal oxidation method in the present embodiment, although the side surface of the oxide film is damaged and the electrical characteristics are deteriorated as it is. Therefore, the plastically flowed component can be made into an insulator (oxide), and the electrical insulation of the substrates 1 and 3 can be more reliably achieved.

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which the hole is not filled with PolySi7 in the process of FIG. 1D of the first embodiment, and the figure shows a state corresponding to FIG. 1F. The process of forming the oxide film 6 formed on the side surface of the oxide film 2 can be a trench etching process in the middle of a wafer process, a process of forming the oxide film 6, and a process of forming a final process for cutting chips. During such, for example, an oxygen atmosphere after the scribe line at the time of chip cutting, or in an oxygen atmosphere and SiH _4, TEOS (tetraethoxysilane) atmosphere scribe line portion by irradiating a laser beam (laser CVD) or the like, SiO ₂ A film or the like can be formed and densified. Also, after cutting into chips, the front and back surfaces of each chip are covered with a jig or the like, only the side surfaces are exposed, and plasma spraying of the insulating film, laser CVD or insulating frit glass SOG etc. An insulating layer may be formed on the entire side surface by coating, densification, resin coating, or the like.

Next, a third embodiment of the present invention will be described with reference to FIG. In the second embodiment, the holes are formed from the substrate 3 side surface, but they may be formed from the substrate 1 side surface as in this embodiment.

As described above, the present invention has been described with reference to the first to third embodiments. However, the present invention is not limited thereto, and can be variously modified without departing from the gist thereof. The insulator layer may be another insulator such as a nitride film other than an oxide film, and the conductivity type of each semiconductor substrate may be another conductivity type. The crystal plane of the semiconductor substrate is (10
It goes without saying that a (110) plane or the like can be used in addition to the (0) plane.

〔The invention's effect〕

According to the present invention, a trench is formed extending from the first semiconductor region in the thickness direction of the semiconductor substrate so as to penetrate the first insulating first layer and reach the inside of the second semiconductor region. Oxidation is formed, polycrystalline silicon is buried in the whole trench through a thermal oxide film, and the trench is formed in a rectangular ring shape that simultaneously surrounds the strain sensing portion and the circuit element. The semiconductor substrate is diced and formed into a chip state so that the portion in which is embedded is exposed to the outside over the entire periphery of the side surface of the semiconductor substrate, so that the strain detecting portion, the circuit element, and the second semiconductor region are efficiently removed completely. Can be insulated and separated.

[Brief description of the drawings]

1 (a) to 1 (g) are cross-sectional views showing a manufacturing process of a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing an example in which the first embodiment is specifically installed in an apparatus, and FIG. FIG. 4 is a sectional view for explaining a second embodiment of the present invention, and FIG. 4 is a sectional view for explaining a third embodiment of the present invention. 1 ... Silicon semiconductor substrate, 2 ... Oxide film, 3 ... Silicon semiconductor substrate, 6 ... Oxide film, 7 ... PolySi.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-54477 (JP, A) JP-A-63-90148 (JP, A) JP-A-63-245939 (JP, A) 109244 (JP, A) JP-A-2-237166 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/84 G01L 9/04 101 H01L 21/762 H01L 21/763

Claims (1)

(57) [Claims] A semiconductor substrate having a first semiconductor region, a second semiconductor region, and a first insulator layer buried between the first and second semiconductor regions; A concave portion formed on the second semiconductor region side from the main surface of the second semiconductor region; a strain detecting portion formed on the first semiconductor region side corresponding to the concave portion; and the first semiconductor region A circuit element formed on the side and in a region different from the recess; a rectangular return shape surrounding the distortion detecting section and the circuit element at the same time, the second element penetrating the first insulator layer;
A trench extending from the first semiconductor region in the thickness direction of the semiconductor substrate so as to reach the inside of the semiconductor region, a thermal oxide film formed over the entire inner surface of the trench, and the thermal oxide film And a polycrystalline silicon formed so as to be buried in the whole inside of the trench through the semiconductor substrate, wherein the portion in which the polycrystalline silicon is buried is exposed to the outside over the entire side surface side periphery of the semiconductor substrate. A semiconductor pressure sensor formed by dicing and cutting into a chip state.