JPS6254477A - Manufacture of semiconductor pressure sensor - Google Patents

Manufacture of semiconductor pressure sensor

Info

Publication number
JPS6254477A
JPS6254477A JP19437585A JP19437585A JPS6254477A JP S6254477 A JPS6254477 A JP S6254477A JP 19437585 A JP19437585 A JP 19437585A JP 19437585 A JP19437585 A JP 19437585A JP S6254477 A JPS6254477 A JP S6254477A
Authority
JP
Japan
Prior art keywords
pressure
layer
silicon
forming
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19437585A
Other languages
Japanese (ja)
Inventor
Tetsuo Fujii
哲夫 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP19437585A priority Critical patent/JPS6254477A/en
Publication of JPS6254477A publication Critical patent/JPS6254477A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable the use at a high temperature by forming an electrical insulator portion which electrically isolates the surroundings of the pressure-sensitive element region, and etching from the opposite principal surface of the semiconductor substrate to the insulator portion to form a pressure-receiving portion. CONSTITUTION:N<+> ions are driven into one principal surface of a silicon substrate 1, and N<+> ions are driven also into the other principal surface in the portion except a region 4 in which the pressure-receiving portion is to be formed; this is heat-treated in a N2 atmosphere, forming silicon nitride layers 2, 3. A P-type monocrystalline silicon layer 5 is grown on the upper surface of the second stop layer 2, and N<+> ions are driven, forming a nitride silicon layer 6. A silicon oxide film 7 is formed, the surroundings of each element portion are surrounded with the silicon oxide film 7 and the silicon nitride layer 6, an insulating film 9 is formed on the substrate surface, and a contact hole portion 9A is opened to form a wiring layer 10. Then, the monocrystalline silicon substrate 1 is etched with an alkaline liquid, etching is performed to the second stop layer 2 in the region 4 in which the pressure-receiving portion is to be formed, until etching automatically terminates. With this, the leakage current is prevented, enabling the use in a high-temperature atmosphere.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、量産に適し、かつ高温雰囲気中での使用が可
能な半導体圧力センサの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor pressure sensor that is suitable for mass production and that can be used in a high temperature atmosphere.

〔従来の技術〕[Conventional technology]

従来、半導体圧力センサとしては、半導体ダイヤフラム
上に半導体感圧素子(歪ゲージ)を拡散等の方法によっ
て形成し、圧力変化をピエゾ抵抗効果による抵抗値の変
化として検出するものが知られている。ここで上記圧力
センサの精度は、ダイヤプラムの両面の平行度、及びそ
の均一性に依存する。
Conventionally, as a semiconductor pressure sensor, one is known in which a semiconductor pressure sensitive element (strain gauge) is formed on a semiconductor diaphragm by a method such as diffusion, and a pressure change is detected as a change in resistance value due to a piezoresistive effect. Here, the accuracy of the pressure sensor depends on the parallelism of both sides of the diaphragm and its uniformity.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記した従来の圧力センサは以下の如き欠点を
有する。
However, the conventional pressure sensor described above has the following drawbacks.

即ち工業的大量生産が困難である。ダイヤフラムの両面
を平行度よく、かつ均一に作製する過程の制御が困難だ
からである。一般にダイヤフラムは半導体基板をエツチ
ングして所望の厚さとするのであるが、エツチング速度
はエツチング液の温度、攪拌状態、組成の変化等に左右
されるため、その制御が極めて困難だからである。
That is, industrial mass production is difficult. This is because it is difficult to control the process of manufacturing both surfaces of the diaphragm with good parallelism and uniformity. Generally, a diaphragm is formed by etching a semiconductor substrate to a desired thickness, but the etching rate is extremely difficult to control because it depends on the temperature, agitation state, changes in composition, etc. of the etching solution.

また、歪ゲージとしてのピエゾ抵抗はPn接合で電気的
に分離されているため、半導体の性質上高温での使用が
困難であった。
Furthermore, since piezoresistors used as strain gauges are electrically isolated by a Pn junction, it is difficult to use them at high temperatures due to the nature of semiconductors.

本発明は、上記点に鑑み、受圧部の平行度を精度良く制
御して各チップ間の受圧部の厚さを均一化でき、しかも
感圧素子領域の周囲を効果的に電気的分離でき、高温で
の使用を可能にできる半導体圧力センサの製造方法を提
供することを目的とする。
In view of the above points, the present invention is capable of accurately controlling the parallelism of the pressure receiving portions to make the thickness of the pressure receiving portions between each chip uniform, and moreover, effectively electrically isolating the periphery of the pressure sensitive element area. An object of the present invention is to provide a method for manufacturing a semiconductor pressure sensor that can be used at high temperatures.

〔問題点を解決するための手段〕[Means for solving problems]

そこで本発明では半導体基板の一主面の内部にイオン打
ち込みにより絶縁体層を形成する工程と、この絶縁体層
の上部の前記一主面の半導体基板領域のうち、少なくと
も感圧素子領域の周囲を電気的に分離する電気的絶縁体
部を形成する工程と、半導体基板の反対主面より前記感
圧素子領域に対応する領域について前記絶縁体層までエ
ツチングして受圧部を形成する工程とを備えることを特
徴とする。
Therefore, the present invention includes a step of forming an insulating layer inside one main surface of a semiconductor substrate by ion implantation, and a step of forming an insulating layer on the inside of one main surface of a semiconductor substrate, and surrounding at least a pressure-sensitive element region of the semiconductor substrate region on the one main surface above this insulating layer. a step of forming an electrical insulator section for electrically isolating the semiconductor substrate; and a step of etching a region corresponding to the pressure sensitive element region from the opposite main surface of the semiconductor substrate to the insulator layer to form a pressure receiving section. It is characterized by being prepared.

〔実施例〕〔Example〕

次に本発明をよりよく理解するために図に示す実施例を
用いて具体的に説明する。第1図(A)はP型車結晶シ
リコン基板1を示す。第1図(B)はこのシリコン基板
1の一方の主面の全面にN0イオン(窒素イオン)を所
定深さの位置に分布するように加速して打ち込み、′例
えば150KeV以上でlXl017個/d程度打ち込
み、他方の主面にも受圧部を形成すべき受圧形成領域4
外の部分に上記条件でN+イオンを打ち込み、その後好
ましくはN2雰囲気中で1200℃にて2〜3時間熱処
理する事により絶縁体層である窒化シリコン層2,3を
成形したものである。ここで窒化シリコン層2が第2停
止層、窒化シリコン層3が第1停止層である。この停止
層は単結晶シリコン基板1の内部に非常に精度よく均一
に形成され、さらに基板1の表面は単結晶状態になって
いる。続いて基板1の第2停止層2の上面にP型車結晶
シリコンN5をエピタキシャル成長させたものを第1図
(C)に示す。このシリコンN5の膜厚は圧力センサの
圧力測定範囲或いは要求圧力感度により任意に選択する
事が出来る。
Next, in order to better understand the present invention, the present invention will be specifically explained using examples shown in the drawings. FIG. 1(A) shows a P-type wheel crystal silicon substrate 1. FIG. FIG. 1(B) shows that N0 ions (nitrogen ions) are accelerated and implanted into the entire surface of one main surface of the silicon substrate 1 so as to be distributed at a predetermined depth. Pressure-receiving forming area 4 where a pressure-receiving part should also be formed on the other main surface.
The silicon nitride layers 2 and 3, which are insulator layers, are formed by implanting N+ ions into the outer portion under the above conditions and then heat-treating preferably at 1200° C. for 2 to 3 hours in an N2 atmosphere. Here, the silicon nitride layer 2 is the second stop layer, and the silicon nitride layer 3 is the first stop layer. This stop layer is uniformly formed inside the single-crystal silicon substrate 1 with great precision, and the surface of the substrate 1 is in a single-crystal state. Subsequently, P-type wheel crystal silicon N5 is epitaxially grown on the upper surface of the second stop layer 2 of the substrate 1, as shown in FIG. 1(C). The film thickness of this silicon N5 can be arbitrarily selected depending on the pressure measurement range of the pressure sensor or the required pressure sensitivity.

引続き、第1図(D)になすように前記と同様にしてこ
のエピタキシャルP型車結晶9937層5中にN゛イオ
ン所定の深さの位置に分布するように打ち込み、N2雰
囲気中で熱処理をおこなって電気的絶縁層をなす窒化シ
リコンN6を形成した。そこで窒化シリコン層6の上部
には単結晶シリコン@5A、下部には単結晶シリコン層
5Bが存在している。
Subsequently, as shown in FIG. 1(D), N2 ions were implanted into the epitaxial P-type wheel crystal 9937 layer 5 so as to be distributed at a predetermined depth, and heat-treated in a N2 atmosphere. This was done to form silicon nitride N6, which serves as an electrically insulating layer. Therefore, monocrystalline silicon@5A exists on the top of the silicon nitride layer 6, and monocrystalline silicon layer 5B exists on the bottom.

次に、第1図(E)または第2図に示すように感圧素子
領域(例えばピエゾ抵抗素子)8、及び感圧素子の出力
を補償、増幅する検出処理回路を同一基板上に形成する
場合には、その回路構成素子領域aを除く部分(つまり
第2図中斜線部分b)を、通常用いられるLOCO5法
により窒化シリコン層6まで達するように選択酸化して
電気的絶縁体部となる酸化シリコン膜7を形成し、各素
子部の周囲をこの酸化シリコン膜7及び窒化シリコン層
6とで完全に取り囲むようにした。なお、ピエゾ抵抗素
子部を形成後にこの素子部8に所定濃度に不純物を拡散
するのも良いが、素子部8の形成前に予めP型エピタキ
シャルN5または5Aの濃度を制御しておけば、上記の
選択酸化の際に同時に所望不純物濃度の素子形成が行な
え、素子形成プロセスが簡単化、均一化されるので望ま
しい。
Next, as shown in FIG. 1(E) or FIG. 2, a pressure sensitive element region (for example, a piezoresistive element) 8 and a detection processing circuit for compensating and amplifying the output of the pressure sensitive element are formed on the same substrate. In this case, the portion excluding the circuit component region a (that is, the shaded portion b in FIG. 2) is selectively oxidized by the commonly used LOCO5 method to reach the silicon nitride layer 6 to become an electrical insulator portion. A silicon oxide film 7 was formed so that each element portion was completely surrounded by the silicon oxide film 7 and the silicon nitride layer 6. Note that it is also possible to diffuse impurities to a predetermined concentration into the element part 8 after forming the piezoresistive element part, but if the concentration of the P-type epitaxial N5 or 5A is controlled in advance before the formation of the element part 8, the above-mentioned effect can be achieved. This is desirable because elements with a desired impurity concentration can be formed at the same time during the selective oxidation of the element, which simplifies and makes the element formation process uniform.

続いて、基板表面に酸化シリコン膜または窒化シリコン
膜などの絶縁膜9を形成し、その後、絶縁膜9にコンタ
クト孔部9Aを開けてピエゾ抵抗素子8への電気接続を
行なうための配線層10を形成した。この配線層10の
材料として/l、またはモリブデンシリサイド、タング
ステンシリサイド、モリブデン、タングステン等の高融
点金属などを用いている。
Subsequently, an insulating film 9 such as a silicon oxide film or a silicon nitride film is formed on the surface of the substrate, and then a contact hole 9A is formed in the insulating film 9 to form a wiring layer 10 for electrical connection to the piezoresistive element 8. was formed. As a material for this wiring layer 10, /l, or a high melting point metal such as molybdenum silicide, tungsten silicide, molybdenum, or tungsten is used.

引続いて、パッシベーション膜としてプラズマCVD法
により窒化シリコン膜11を形成し、外部取出し用のコ
ンタクト孔部11Aを開けた。このようにパッシベーシ
ョン膜として本実施例の如く窒化膜(S!:+N4膜)
を用いれば、シリコン(Si)と熱膨張係数を合わせる
ことができ、一層高温雰囲気での使用が可能になる。ま
たその他゛にもシリコンと熱膨張係数の近似した5io
zJI*など他の絶縁膜を選択するようにしても良い。
Subsequently, a silicon nitride film 11 was formed as a passivation film by plasma CVD, and a contact hole 11A for external extraction was opened. In this way, as a passivation film, a nitride film (S!: +N4 film) is used as in this example.
By using silicon (Si), the thermal expansion coefficient can be matched with that of silicon (Si), making it possible to use it in an even higher temperature atmosphere. In addition, 5io, which has a thermal expansion coefficient similar to that of silicon, is also available.
Other insulating films such as zJI* may be selected.

次に、KOHなどのアルカリ液によるアルカリエツチン
グ、その他のシリコンエツチング液中で単結晶シリコン
基板1をエツチングする。この際第1停止層3により予
定の受圧部形成領域4外の部分ではエツチングの進行を
阻止され、一方受圧部形成領域4では第2停止層2まで
エツチングされ自動的にエツチングが終了するのでこの
受圧部形成領域4の全面にわたり平行度よくエツチング
される。そこで第1図(F)図示の如く被検出対象の圧
力により可動(変形)するダイヤフラムをなす受圧部1
2.及び受圧部12の支持部13が形成される。
Next, the single crystal silicon substrate 1 is etched in an alkaline etching solution such as KOH or other silicon etching solution. At this time, the first stop layer 3 prevents the etching from progressing in the area outside the planned pressure receiving part forming area 4, while in the pressure receiving part forming area 4, etching is completed up to the second stop layer 2 and the etching is automatically completed. Etching is performed over the entire surface of the pressure receiving portion forming region 4 with good parallelism. Therefore, as shown in FIG. 1 (F), the pressure receiving part 1 is a diaphragm that moves (deforms) due to the pressure of the object to be detected.
2. And the support part 13 of the pressure receiving part 12 is formed.

なお、圧力センサはこの受圧部12の変形により感圧素
子領域8の抵抗がピエゾ抵抗効果でもって変化すること
を利用してその圧力を検出するものである。第2図は第
1図(F)の途中プロセスにおける模式的平面図で、選
択酸化された酸化シリコン膜7(斜面部分b)の−パタ
ーン例を示している。
Note that the pressure sensor detects the pressure by utilizing the fact that the resistance of the pressure sensing element region 8 changes due to the piezoresistance effect due to the deformation of the pressure receiving portion 12. FIG. 2 is a schematic plan view in the middle of the process of FIG. 1(F), showing an example of a pattern of the selectively oxidized silicon oxide film 7 (slope portion b).

なお、本実施例においてはイオン打ち込みに窒素イオン
を用いたが酸素イオン、炭素イオン等を用いても同様な
方法で達成できる事はもちろんである。又は、第1停止
層3の形成はイオン打ち込みでなく、基板1表面に5i
nz膜、Si3N4膜。
In this embodiment, nitrogen ions were used for ion implantation, but it is of course possible to achieve the same results by using oxygen ions, carbon ions, etc. Alternatively, the first stop layer 3 may be formed by 5i on the surface of the substrate 1 instead of by ion implantation.
nz film, Si3N4 film.

A 1 z O!膜等を形成し写真食刻法により第1停
止層を作る事もできる。また、本発明の要旨から明らか
なように、上記実施例においてP型シリコンをn型シ゛
リコンに、n型シリコンをP型シリコンにおきかえても
その作用に変化はない。又、停止層とは必ずしもシリコ
ンエツチング液でエツチングされない層である必要はな
く、エツチング速度がシリコン基板より非常に小さけれ
ば停止層としての役割を果す事ができるものである。ま
た、上述の実施例では歪ゲージとしてP型拡散層8を設
けたが、拡散層8を設けず他の素子を用いてシリコンよ
りなるダイヤフラムの歪変形を検出するようにしてもよ
い。
A 1 z O! It is also possible to form the first stop layer by forming a film or the like and using photolithography. Further, as is clear from the gist of the present invention, even if the P-type silicon is replaced with n-type silicon and the n-type silicon is replaced with P-type silicon in the above embodiments, there is no change in the operation. Further, the stop layer does not necessarily have to be a layer that is not etched with a silicon etching solution, and can serve as a stop layer if the etching rate is much lower than that of the silicon substrate. Further, in the above embodiment, the P-type diffusion layer 8 was provided as a strain gauge, but the diffusion layer 8 may not be provided and other elements may be used to detect the strain deformation of the diaphragm made of silicon.

次に、第3図は本発明の他の実施例を示すものである。Next, FIG. 3 shows another embodiment of the present invention.

本例では前記実施例のような厚いエピタキシャル層5を
形成せず非常に薄いエピタキシャル層を形成するか、も
しくは全くエピタキシャル層を形成せずに行ない、しか
もエツチング停止用の第2停止層2と電気的絶縁層6と
を兼務する1つの絶縁膜をシリコン基板内部に設けたも
のである。
In this example, instead of forming the thick epitaxial layer 5 as in the previous example, a very thin epitaxial layer is formed, or no epitaxial layer is formed at all. One insulating film that also serves as the external insulating layer 6 is provided inside the silicon substrate.

すなわち、P型車結晶シリコン基板101に一主面及び
反対主面よりN゛イオン所定深さの位置まで打ち込み後
熱処理を施すことにより、窒化シリコン層からなる第1
停止J’W103、及び第2停止層102を形成し、第
2停止層102の上部にあるシリコン基板領域(または
エピタキシャル層を含めて)を選択酸化して第2停止層
102に達する酸化シリコン層104、及び感圧素子領
域105を形成したものである。なお、106は絶縁膜
、107は配線層、108はパッシベーション膜、10
9は受圧部、110は受圧部109の支持部である。こ
れらの形成方法は前記実施例と同様である。
That is, by performing heat treatment on the P-type wheel crystal silicon substrate 101 after implanting N ions to a predetermined depth from one principal surface and the opposite principal surface, a first silicon nitride layer is formed.
A silicon oxide layer that forms the stop J'W 103 and the second stop layer 102 and selectively oxidizes the silicon substrate region (or including the epitaxial layer) above the second stop layer 102 to reach the second stop layer 102. 104 and a pressure sensitive element region 105 are formed. Note that 106 is an insulating film, 107 is a wiring layer, 108 is a passivation film, and 10
9 is a pressure receiving part, and 110 is a support part of the pressure receiving part 109. The method of forming these is the same as in the previous embodiment.

本実施例によれは、受圧部の肉厚を薄くシ圧カセンサを
さらに小型化にできるようになる。
According to this embodiment, the wall thickness of the pressure receiving portion can be made thinner, and the pressure sensor can be further miniaturized.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明方法においては、半導体基板内
に予め所定の停止層を形成しこの基板をエツチングする
ようにしているため、受圧部の厚さ及び平行度はイオン
打ち込み層できまり、その制御はきわめて容易であるば
かりでなく、目的とする受圧部の厚さに達するとエツチ
ングは自動的に終了するので特性のそろった素子を多数
製造することが可能である。さらに本発明の停止層を使
用した方法では受圧部の厚さの異なるウェーハ、たとえ
は20μ、25μ等の数種のものを混合しても同じエツ
チング精度でもって多数のウェーハにおいてエツチング
は自動的に終了するので、同−処理が出来、その結果精
度よく多数の半導体ダンヤフラムを製造できる。
As described above, in the method of the present invention, a predetermined stop layer is formed in advance in the semiconductor substrate and this substrate is etched, so the thickness and parallelism of the pressure receiving part are determined by the ion implantation layer. Not only is control extremely easy, but the etching is automatically terminated when the desired thickness of the pressure-receiving portion is reached, making it possible to manufacture a large number of devices with uniform characteristics. Furthermore, in the method using the stop layer of the present invention, even if several wafers with different thicknesses of pressure receiving parts, such as 20μ and 25μ, are mixed, etching can be performed automatically on a large number of wafers with the same etching accuracy. As a result, the same process can be performed, and as a result, a large number of semiconductor dungeon frames can be manufactured with high precision.

しかも、感圧素子領域の周囲を電気的絶縁体部でもって
完全に電気的分離を行なっているため、感圧素子部の漏
れ電流をなくして高温雰囲気での使用を可能にできる。
Furthermore, since the periphery of the pressure-sensitive element area is completely electrically isolated by the electrical insulator, leakage current from the pressure-sensitive element area can be eliminated, making it possible to use it in a high-temperature atmosphere.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(F)は本発明の一実施例となる製造工
程を示す断面図、第2図は本発明方法の説明に用いる模
式的平面図、第3図は本発明の他の実施例を示す断面図
である。 1.101・・・単結晶シリコン基板、2,102・・
・絶縁体層をなす窒化シリコン層(第2停止層)。 3.103・・・窒化シリコン層(第1停止層)、6・
・・窒化シリコン層、7.104・・・電気的絶縁体部
の要部をなす酸化シリコン膜、8.105・・・感圧素
子領域、9,106・・・絶縁膜、10,107・・・
配線層、12,109・・・受圧部。 (Aン                      
    (B)(E)               
(F)8湿りL神、べ 第1図
FIGS. 1(A) to (F) are cross-sectional views showing the manufacturing process according to an embodiment of the present invention, FIG. 2 is a schematic plan view used to explain the method of the present invention, and FIG. FIG. 1.101... Single crystal silicon substrate, 2,102...
- A silicon nitride layer (second stop layer) forming an insulator layer. 3.103...Silicon nitride layer (first stop layer), 6.
...Silicon nitride layer, 7.104...Silicon oxide film forming the main part of electrical insulator section, 8.105...Pressure sensitive element region, 9,106...Insulating film, 10,107...・・・
Wiring layer, 12, 109...pressure receiving part. (A
(B) (E)
(F) 8 Moisture L God, Be Figure 1

Claims (1)

【特許請求の範囲】[Claims]  半導体基板の一主面の内部にイオン打ち込みにより絶
縁体層を形成する工程と、この絶縁体層の上部の前記一
主面の半導体基板領域のうち、少なくとも感圧素子領域
の周囲を電気的に分離する電気的絶縁体部を形成する工
程と、半導体基板の反対主面より前記感圧素子領域に対
応する領域について前記絶縁体層までエッチングして受
圧部を形成する工程とを備えることを特徴とする半導体
圧力センサの製造方法。
A step of forming an insulating layer inside one principal surface of the semiconductor substrate by ion implantation, and electrically connecting at least the area around the pressure-sensitive element region of the semiconductor substrate region of the one principal surface above the insulating layer. The present invention is characterized by comprising a step of forming a separating electrical insulator portion, and a step of etching a region corresponding to the pressure sensitive element region from the opposite main surface of the semiconductor substrate to the insulator layer to form a pressure receiving portion. A method for manufacturing a semiconductor pressure sensor.
JP19437585A 1985-09-03 1985-09-03 Manufacture of semiconductor pressure sensor Pending JPS6254477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19437585A JPS6254477A (en) 1985-09-03 1985-09-03 Manufacture of semiconductor pressure sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19437585A JPS6254477A (en) 1985-09-03 1985-09-03 Manufacture of semiconductor pressure sensor

Publications (1)

Publication Number Publication Date
JPS6254477A true JPS6254477A (en) 1987-03-10

Family

ID=16323544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19437585A Pending JPS6254477A (en) 1985-09-03 1985-09-03 Manufacture of semiconductor pressure sensor

Country Status (1)

Country Link
JP (1) JPS6254477A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240971A (en) * 1989-03-14 1990-09-25 Nippondenso Co Ltd Semiconductor pressure sensor
JPH04148569A (en) * 1990-10-11 1992-05-21 Touyoko Kagaku Kk Semiconductor pressure sensor and manufacture of the same
JPH08181332A (en) * 1995-08-09 1996-07-12 Touyoko Kagaku Kk Manufacture of semiconductor pressure sensor
JP2007309914A (en) * 2006-04-20 2007-11-29 Denso Corp Method of manufacturing physical quantity sensor
JP2008270797A (en) * 1992-04-08 2008-11-06 Glenn J Leedy Manufacturing of insulating film layer isolation ic

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02240971A (en) * 1989-03-14 1990-09-25 Nippondenso Co Ltd Semiconductor pressure sensor
JPH04148569A (en) * 1990-10-11 1992-05-21 Touyoko Kagaku Kk Semiconductor pressure sensor and manufacture of the same
JP2008270797A (en) * 1992-04-08 2008-11-06 Glenn J Leedy Manufacturing of insulating film layer isolation ic
JP2009218606A (en) * 1992-04-08 2009-09-24 Taiwan Semiconductor Manufacturing Co Ltd Manufacture of membrane dielectric insulation ic
JP4648979B2 (en) * 1992-04-08 2011-03-09 台湾積體電路製造股▲ふん▼有限公司 Insulating layer separation IC manufacturing
JP4730672B2 (en) * 1992-04-08 2011-07-20 台湾積體電路製造股▲ふん▼有限公司 Insulating layer separation IC manufacturing
JPH08181332A (en) * 1995-08-09 1996-07-12 Touyoko Kagaku Kk Manufacture of semiconductor pressure sensor
JP2007309914A (en) * 2006-04-20 2007-11-29 Denso Corp Method of manufacturing physical quantity sensor

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