JPH05114744A - Method of manufacturing semiconductor pressure sensor - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor pressure sensor, which is capable of obtaining the sensor having a superior controllability of the thickness of a diaphragm and a high-accuracy and stable quality. CONSTITUTION:A semiconductor pressure sensor is manufactured by such a method in which a second single crystal silicon substrate 103 formed with a first thermal oxide film 104 is joined to the main surface of a first single crystal silicon substrate 101 formed with a p<-> diffused layer 102, an n-type epitaxial layer 106 is formed on the layer 102, impurities are diffused into this layer 106 to form piezoresistance elements 108 and after that, the substrate 103 is removed by etching until this layer 102 is exposed using the layer 102 as an etching stop layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure sensor utilizing the piezoresistive effect of a silicon semiconductor.

[0002]

2. Description of the Related Art Silicon pressure sensors are compact, lightweight, have high performance and excellent responsiveness, so
It is becoming more frequently used in the field.

This type of device is called an "integrated capacitive pressure sensor" {The Institute of Electrical Engineers of Japan, C.I. Volume 109 December issue (820P
(P) Heisei 1)}, and it is common to detect the pressure by using the resistance change due to the pressure of the piezoresistive element formed on the silicon diaphragm where a part of the silicon substrate is thinned. ..

A method of manufacturing this type of pressure sensor will be described below with reference to FIGS. 2 (a) to 2 (e).

First, as shown in FIG.
0) P-type single crystal silicon substrate 201 having a crystal orientation plane
An N ⁺ buried layer 202 containing N-type high-concentration impurities is formed in the bipolar element formation region on the one main surface side.

Then, a P ⁺ buried layer 203 containing a P-type high-concentration impurity is formed in the piezoresistive region on the one main surface side including the N ⁺ buried layer 202.

Next, as shown in FIG. 2B, N is formed on one main surface including the N ⁺ buried layer 202 and the P ⁺ buried layer 203.
A type epitaxial layer 204 is formed.

Then, a P-type high concentration impurity is diffused from the main surface side of the N-type epitaxial layer 204 around the N ⁺ buried layer 202, and ^{P is} added from the main surface of the N-type epitaxial layer 204.
Type P ⁺ separation layer 2 reaching the single crystal silicon substrate 201
Form 05.

Next, using a known LSI manufacturing technique, as shown in FIG. 2C, a piezoresistive element 206 formed by diffusing P-type impurities and P-type and N-type impurities are sequentially formed. An active element 207 represented by a bipolar transistor is formed by diffusion.

In the step of forming the diffusion layer described above, an oxide film 208 is formed on the main surface side of the N-type epitaxial layer 204 including the piezoresistive element 206 and the active element 207 and the main surface side opposite to the P-type single crystal silicon substrate 201. Is formed.

Next, as shown in FIG. 2D, an oxide film 208 on the N-type epitaxial layer 204 is opened to form a contact hole 209, and then an electrode wiring 210, a surface protective film 211, And the back surface protection film 212 is formed.

Next, as shown in FIG. 2E, a piezoresistive element 206 having a back surface protective film 212 and an oxide film 208 formed on the opposite main surface side of the P-type single crystal silicon substrate 201.
After opening a region corresponding to the back surface of the formation region, the P-type single crystal silicon substrate 201 is removed by etching until the tip reaches the P ⁺ buried layer 203 by alkaline anisotropic etching or the like, and the diaphragm 213 is formed.

At this time, the P ⁺ buried layer 203 is formed in order to control the thickness of the diaphragm 213 with high accuracy, and the impurity concentration of the P ⁺ buried layer 203 is set to about 1 × 10 ^19.
The impurity concentration dependency that the alkali anisotropic etching is stopped by setting the atoms / cm ³ or more is used. In this way, a semiconductor pressure sensor in which a piezoresistive element is arranged on the diaphragm is formed.

[0014]

However, in the manufacturing method described above, after the P ⁺ buried layer 203 is formed, the P ^{+
Since the +} isolation layer 205, the piezoresistive element 206, and the active element 207 such as a bipolar transistor element are formed by the diffusion technique, the P ⁺ buried layer 203 itself is also diffused and the impurity concentration is lowered.

Therefore, it is difficult to maintain an impurity concentration of 1 × 10 ¹⁹ atoms / cm ³ or more during etching for forming the diaphragm 213, and the diaphragm 213 does not function sufficiently as an etching stop layer.
There was a problem that the thickness of the fluctuated.

Since the thickness of the diaphragm 213 has a strong influence on the change in the resistance value of the piezoresistive element 206,
The method shown in the conventional example is not satisfactory for the above reason, and thus it has been difficult to obtain a highly accurate semiconductor pressure sensor.

Further, a process condition will be described as an example of a problem when the P ⁺ buried layer 203 functions as an etching stop layer. For example, when the N-type epitaxial layer 204 is formed to a thickness of 20 μm, heat treatment at 1200 ° C. for about 25 hours is required for diffusion of the P ⁺ separation layer 205.

Under this heat treatment condition, the impurity concentration condition immediately after the formation of the P ⁺ buried layer is 2 × 10 ²⁰ atoms / cm ³ in order to maintain the impurity concentration of the P ⁺ buried layer of 1 × 10 ¹⁹ atoms / cm ³ or more. That is all.

However, under this impurity concentration condition, the P ⁺ buried layer is diffused to the main surface side of the N type epitaxial layer 204 by the heat treatment for forming the P ⁺ isolation layer, and the piezoresistive element 206 cannot be formed. There was a problem, and it was difficult to integrate the pressure sensor and the output signal processing circuit into a single chip.

Among the problems of the above-mentioned prior art, the present invention has a problem that the diaphragm thickness varies due to the deterioration of the etching stopping property at the time of diaphragm formation due to the decrease of the impurity concentration of the P ⁺ buried layer. The present invention provides a method for manufacturing a semiconductor pressure sensor, which has been solved.

[0021]

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor pressure sensor, wherein an oxide film is formed on the main surface side of a first single crystal semiconductor substrate including a P-type semiconductor layer. After bonding the second single crystal semiconductor substrate formed on the front surface side, removing the first single crystal semiconductor substrate until the P-type semiconductor layer is exposed from the main surface side opposite to the first single crystal semiconductor substrate And a step of forming an N-type crystal semiconductor layer on the exposed main surface side of the P-type semiconductor layer and forming a piezoresistive element on the N-type single crystal semiconductor layer, and a step opposite to the second single crystal semiconductor substrate. And a step of removing a part of the single crystal semiconductor substrate until the oxide film is exposed from a predetermined position on the main surface.

[0022]

According to the present invention, since the steps described above are introduced in the method for manufacturing a semiconductor pressure element, the P-type diffusion layer is formed on the main surface side of the first single crystal semiconductor substrate, and the main surface side is formed. After adhering the second single crystal semiconductor substrate having an oxide film formed thereon to the main surface side of the first single crystal semiconductor substrate including the P-type diffusion layer, from the opposite main surface side of the first single crystal semiconductor substrate The P-type diffusion layer is removed as an etching stop layer by etching to expose the P-type diffusion layer, and an N-layer is formed on the P-type diffusion layer.
A type epitaxial layer is formed. After forming the piezoresistive element in the N-type epitaxial layer, the diaphragm is formed by etching away the oxide film as the etching stop layer from the opposite main surface side of the second single crystal semiconductor substrate, and thus, The above problems can be eliminated.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method for manufacturing a semiconductor pressure sensor of the present invention will be described below with reference to the drawings. Figure 1
FIGS. 1A to 1G are process explanatory views of one embodiment.

First, as shown in FIG. 1A, as a first single crystal semiconductor substrate having a (100) crystal orientation plane, for example, a junction depth is formed on the main surface side of a first single crystal silicon substrate 101. 3 μm, impurity concentration 5 × 10 ¹⁹ atoms / cm
³ of a high concentration of P ⁺ to form a diffusion layer 102.

Next, as shown in FIG. 1B, for example, as a second single crystal semiconductor substrate having a (100) crystal orientation plane, an oxide film is formed on the exposed surface of the second single crystal silicon substrate 103. , The first thermal oxide film 104 is formed.

After that, Nikkei Microbody 198
In August and March, P82-98 “Wafer bonding technology”, a known wafer bonding technology is used, and the main surface side of the first single crystal silicon substrate 101 and the second single crystal silicon substrate 103 are processed. Stick together the main surface side comrades.

Now, the wafer bonding conditions will be described in detail. First, the first single crystal silicon substrate 101
Then, the main surface of the second single crystal silicon substrate 103 is washed with, for example, a perhydrogen sulfuric acid solution to make it hydrophilic.

Next, the first single crystal silicon substrate 101 and the second single crystal silicon substrate 10 in a clean room temperature atmosphere.
The three main surfaces are brought into contact with each other. Thereafter, for example, by performing heat treatment at 1100 ° C. for 120 minutes in a nitrogen atmosphere, wafer bonding with a tensile strength of 150 kg / cm ² or more can be realized.

Further, the thickness of the first thermal oxide film 104 formed on the main surface side of the second single crystal silicon substrate 103 takes into consideration the influence of the stress of the thermal oxide film on the pressure sensor formed later. Set to about 3000Å.

Next, as shown in FIG. 1C, P ^{+ is} applied from the opposite main surface side of the first single crystal silicon substrate 101 with an alkaline anisotropic etching solution such as KOH, NaOH or hydrazine. Etching is performed using the diffusion layer 102 as an etching stop layer to expose the P ⁺ diffusion layer 102.

Next, as shown in FIG. 1D, a high concentration N is formed at a desired position on the exposed main surface side of the P ⁺ diffusion layer 102, for example, in order to reduce the collector resistance of the vertical NPN transistor. ^{The +} buried layer 105 is formed, and an N type epitaxial layer 106 as an N type single crystal semiconductor layer is formed on the main surface side of the P ⁺ diffusion layer 102 including the N ⁺ buried layer 105 by a known epitaxial technique.
At a generation temperature of about 0 ° C., for example, a specific resistance of 2 Ω-cm and a thickness of 20 μm are formed.

After that, in order to electrically separate active elements such as bipolar transistors from each other, a well-known photolithography / etching technique is used to form an impurity concentration of 1 × 10 ²⁰ atoms / cm ³ or more at a desired position. A high-concentration P-type impurity is subjected to a heat treatment at 1200 ° C. for 25 hours or more to obtain N
P ⁺ diffusion layer 1 from the main surface side of the epitaxial layer 106
P ⁺ separation layer 1 by diffusing until it reaches 02.
07 is formed.

Next, as shown in FIG. 1E, a well-known LSI manufacturing technique is used to diffuse P-type impurities from the main surface side at a desired position of the N-type epitaxial layer 106. Piezoresistive element 108 as semiconductor pressure sensor
Then, an active element 109 typified by a bipolar transistor formed by sequentially diffusing P-type and N-type impurities is formed.

In the step of forming the diffusion layer described above, the second thermal oxide film 110 is formed on the main surface side of the N type epitaxial layer 106 including the piezoresistive element 108 or the active element 109.

Next, as shown in FIG. 1F, the second thermal oxide film is opened to form the contact hole 111, and then the electrode wiring 112, the front surface protective film 113, and the back surface protective film 114. Are sequentially formed.

Next, as shown in FIG. 1G, the back surface protective film 114 formed on the opposite main surface side of the second single crystal silicon substrate 103 and the piezo resistance of the second thermal oxide film 110. A region corresponding to the back surface of the formation region of the element 108 is opened by a known photolithographic etching technique.

After that, the second single crystal silicon substrate 103 is etched away by alkali anisotropic etching or the like until the tip reaches the first thermal oxide film 104 to form a diaphragm 115. In this way, a semiconductor pressure sensor in which the piezoresistive element 108 is arranged on the diaphragm 115 is formed.

[0038]

As described in detail above, according to the present invention, an oxide film is formed on the main surface side of the first single crystal semiconductor substrate including the P type diffusion layer by using the wafer bonding technique. After bonding the two single crystal semiconductor substrates, an N type single crystal semiconductor layer is formed on the P type diffusion layer, a piezoresistive element is formed on this N type single crystal semiconductor layer, and then the oxide film is etched when the diaphragm is formed. As the stop layer, the second single crystal semiconductor layer is removed by etching until it is exposed. Therefore, variations in the diaphragm thickness due to etching can be significantly reduced, and the diaphragm thickness is the same as that of the N-type single crystal semiconductor layer. Since it is determined only by the growth thickness accuracy, it is possible to manufacture a semiconductor pressure sensor with high accuracy and stable quality.

Further, as an etching stop layer at the time of forming the diaphragm, a high concentration (1 × 10 ²⁰ atoms / cm 2) as in the conventional case is used.
⁽³ or more) P-type diffusion layer is not used, but an embedded oxide film formed by wafer bonding technology is used. Therefore, when forming an output signal processing circuit such as zero point correction or temperature compensation composed of bipolar transistors, etc. The problem of upward diffusion of the P-type diffusion layer to the piezoresistive element region due to the heat treatment can be eliminated, so that the pressure sensor and the output signal processing circuit can be easily integrated into one chip.

[Brief description of drawings]

FIG. 1 is a process explanatory view of an embodiment of a method for manufacturing a semiconductor pressure sensor of the present invention.

FIG. 2 is a process explanatory view of a conventional method for manufacturing a semiconductor pressure sensor.

[Explanation of symbols]

101 First Single Crystal Silicon Substrate 102 P ⁺ Diffusion Layer 103 Second Single Crystal Silicon Substrate 104 First Thermal Oxide Film 105 N ⁺ Buried Layer 106 N-Type Epitaxial Layer 107 P ⁺ Separation Layer 108 Piezoresistive Element 109 Active Element 110 Second thermal oxide film 111 Contact hole 112 Electrode wiring 113 Front surface protection film 114 Back surface protection film 115 Diaphragm

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[Procedure amendment]

[Submission date] October 5, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

Claims (1)

[Claims] 1. A step of forming a semiconductor layer of a first conductivity type on one main surface side of a first single crystal semiconductor substrate, and the first single crystal semiconductor substrate including the semiconductor layer of the first conductivity type. A step of bonding a second single crystal semiconductor substrate having an oxide film formed on the surface side thereof to the main surface side of the first conductivity type semiconductor from the opposite main surface side of the first single crystal semiconductor substrate. Removing the first single crystal semiconductor substrate until the layer is exposed, and forming a second conductivity type single crystal semiconductor layer on the exposed main surface side of the first conductivity type semiconductor layer, The oxide film is removed from a desired position on the opposite main surface of the second single crystal semiconductor substrate by diffusing impurities in the second conductivity type single crystal semiconductor layer to form a piezoresistive element. A process for removing a part of the second single crystal semiconductor substrate until it is exposed. When, a method of manufacturing a semiconductor pressure sensor further comprising.