JP2688609B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2688609B2 JP2688609B2 JP63058271A JP5827188A JP2688609B2 JP 2688609 B2 JP2688609 B2 JP 2688609B2 JP 63058271 A JP63058271 A JP 63058271A JP 5827188 A JP5827188 A JP 5827188A JP 2688609 B2 JP2688609 B2 JP 2688609B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- epitaxial layer
- diffusion
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は受光素子部と増幅素子部とを同一基板に形成
した半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device in which a light receiving element section and an amplification element section are formed on the same substrate.
フォトトランジスタ受光方式には入射光に対する直進
性・応答速度が良好であるフォトダイオードが用いられ
ている。しかし、このフォトダイオードは受光感度が低
いため、その後段に増幅部としてのトランジスタが接続
されている。即ち、この受光方式の素子構造はフォトダ
イオードとトランジスタとの複合素子構造となってい
る。従って、その製造工程では、1個数当たり2チップ
で2回のダイボンディングが必要となり、工程が煩雑で
あった。In the phototransistor light receiving system, a photodiode is used which has a good linearity and a good response speed with respect to incident light. However, since this photodiode has low light receiving sensitivity, a transistor as an amplifier is connected to the subsequent stage. That is, the light receiving element structure is a composite element structure of a photodiode and a transistor. Therefore, in the manufacturing process, it is necessary to perform die bonding twice with two chips per one, and the process is complicated.
そこで、1チップにフォトダイオードとトランジスタ
形成した半導体装置(チップ)を用いれば1チップで1
回のダイボンディングでフォトトランジスタ受光方式の
装置の製作が可能であるが、そのためには両者を同一基
板に形成する必要がある。Therefore, if a semiconductor device (chip) in which a photodiode and a transistor are formed on one chip is used,
It is possible to fabricate a phototransistor light-receiving device by die-bonding once, but for that purpose, both must be formed on the same substrate.
ところが、フォトダイオードとトランジスタは使用す
る基板の抵抗値が相互に異なるため、何れか一方の基板
に統一することはできない。このため、上記目的の半導
体装置(チップ)を製造することが困難であった。However, since the resistance values of the substrates used for the photodiode and the transistor are different from each other, it is not possible to unify them on one of the substrates. Therefore, it is difficult to manufacture the semiconductor device (chip) for the above purpose.
本発明はこのような事情に鑑みてなされたもので、フ
ォトダイオードとトランジスタ等の複数素子を同一基板
に形成した半導体装置の製造方法を提供することであ
る。The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a semiconductor device in which a plurality of elements such as a photodiode and a transistor are formed on the same substrate.
このために、本発明の半導体装置の製造方法は、受光
素子と増幅素子を同一基板上に形成する半導体装置の製
造方法において、上記基板上に該基板よりも比抵抗の小
さいエピタキシャル層を成長形成する工程と、該エピタ
キシャル層を異方性エッチングによってパターニング開
口して上記基板を露出させる工程と、該露出した基板内
に上記受光素子のアノード領域を拡散で形成すると同時
に上記エピタキシャル層内に上記増幅素子のベース領域
を拡散で形成する工程と、該ベース領域中にエミッタ領
域を拡散で形成する工程と、を含むことを特徴とするよ
う構成した。Therefore, in the method for manufacturing a semiconductor device of the present invention, in the method for manufacturing a semiconductor device in which a light receiving element and an amplifying element are formed on the same substrate, an epitaxial layer having a specific resistance smaller than that of the substrate is grown on the substrate. And exposing the substrate by patterning and opening the epitaxial layer by anisotropic etching, and forming the anode region of the light receiving element by diffusion in the exposed substrate and at the same time amplifying the amplification region in the epitaxial layer. The device is characterized by including a step of forming a base region of the element by diffusion and a step of forming an emitter region in the base region by diffusion.
以下、本発明の一実施例の薄膜半導体装置Aの製造方
法について説明する。第1図(a)(b)(c)はその
工程を示す説明図である。まず、結晶方位が<100>で
フォトダイオードに適した比抵抗(80〜100Ω・cm)と
厚みを有するシリコンウエハでなる基板1にトランジス
タに適した比抵抗(5〜8Ω・cm)と厚みを有するエピ
タキシャル層2を成長させる(第1図(a)参照)。Hereinafter, a method of manufacturing the thin film semiconductor device A according to the embodiment of the present invention will be described. 1 (a), (b) and (c) are explanatory views showing the process. First, a substrate 1 made of a silicon wafer having a crystal orientation <100> and a specific resistance (80 to 100 Ω · cm) suitable for a photodiode is provided with a specific resistance (5 to 8 Ω · cm) and a thickness suitable for a transistor. The epitaxial layer 2 having is grown (see FIG. 1 (a)).
次に、フォトダイオードとなるエピタキシャル層2の
一部を異方性エッチング液によってパターンニング除去
して基板1の表面の一部を開口する(第1図(b)参
照)。その後、該開口部分の基板1に対するアノード拡
散とトランジスタとなる部分のエピタキシャル層2に対
するベース拡散とを同時に行ってアノード3とベース4
を形成し、さらに、該ベース4の一部にエミッタ拡散を
行ってエミッタ5を形成する(第1図(c)参照)。Next, a part of the epitaxial layer 2 to be the photodiode is patterned and removed with an anisotropic etching solution to open a part of the surface of the substrate 1 (see FIG. 1 (b)). Thereafter, the anode diffusion to the substrate 1 in the opening portion and the base diffusion to the epitaxial layer 2 in the portion to be the transistor are simultaneously performed to perform the anode 3 and the base 4 diffusion.
Is formed, and further, an emitter diffusion is performed on a part of the base 4 to form an emitter 5 (see FIG. 1 (c)).
なお、6はシリコン酸化膜等からなる絶縁膜、7は裏
面に形成したカソード、8は基板1とエピタキシャル層
2との間に形成した埋込領域層、9はアノード3とベー
ス4とを接続する配線、10はエミッタ電極、11はコレク
タ電極、12はコレクタ電極11と埋込領域層8とを接続す
るコレクタウォールである。In addition, 6 is an insulating film made of a silicon oxide film, 7 is a cathode formed on the back surface, 8 is a buried region layer formed between the substrate 1 and the epitaxial layer 2, and 9 is a connection between the anode 3 and the base 4. Wiring, 10 is an emitter electrode, 11 is a collector electrode, and 12 is a collector wall that connects the collector electrode 11 and the buried region layer 8.
以上により1チップの同一基板にフォトダイオードと
トランジスタとが組込まれた半導体装置Aが製作され
る。第2図はその等価回路図である。このように形成さ
れた半導体装置Aでは、フォトダイオードとトランジス
タを各々に適した比抵抗値・厚さにすることができる。
よって両者の各々の特性が個別のチップに形成したもの
の特性より劣下することが回避できる。As described above, the semiconductor device A in which the photodiode and the transistor are incorporated on the same substrate of one chip is manufactured. FIG. 2 is an equivalent circuit diagram. In the semiconductor device A thus formed, the photodiode and the transistor can have a specific resistance value and thickness suitable for each.
Therefore, it is possible to prevent the characteristics of both of them from deteriorating from the characteristics of those formed on separate chips.
以上から本発明の半導体装置の製造方法によれば、フ
ォトダイオードとトランジスタとを各々の特性を損なう
ことなく同一基板に形成することが可能となる。よっ
て、この半導体装置(チップ)を用いればフォトトラン
ジスタ方式の半導体装置の製作が1チップの1回のダイ
ボンディングで可能となり、その工程の簡略化、製造コ
ストダウン等が図れる。As described above, according to the semiconductor device manufacturing method of the present invention, the photodiode and the transistor can be formed on the same substrate without deteriorating the characteristics of each. Therefore, by using this semiconductor device (chip), a phototransistor type semiconductor device can be manufactured by die bonding of one chip once, and the process can be simplified and the manufacturing cost can be reduced.
第1図(a)(b)(c)は本発明の一実施例の半導体
装置の製造工程を示す説明図、第2図はその半導体装置
の等価回路図である。 1……基板、2……エピタキシャル層、3……アノー
ド、4……ベース、5……エミッタ、6……絶縁膜、7
……カソード、8……埋込領域層、9……配線、10……
エミッタ電極、11……コレクタ電極、12……コレクタウ
ォール。1 (a), (b), and (c) are explanatory views showing the manufacturing process of the semiconductor device of one embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the semiconductor device. 1 ... Substrate, 2 ... Epitaxial layer, 3 ... Anode, 4 ... Base, 5 ... Emitter, 6 ... Insulating film, 7
...... Cathode, 8 …… Embedded region layer, 9 …… Wiring, 10 ……
Emitter electrode, 11 …… collector electrode, 12 …… collector wall.
Claims (1)
る半導体装置の製造方法において、 上記基板上に該基板よりも比抵抗の小さいエピタキシャ
ル層を成長形成する工程と、 該エピタキシャル層を異方性エッチングによってパター
ニング開口して上記基板を露出させる工程と、 該露出した基板内に上記受光素子のアノード領域を拡散
で形成すると同時に上記エピタキシャル層内に上記増幅
素子のベース領域を拡散で形成する工程と、 該ベース領域中にエミッタ領域を拡散で形成する工程
と、 を含むことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which a light-receiving element and an amplifying element are formed on the same substrate, wherein a step of growing an epitaxial layer having a specific resistance smaller than that of the substrate on the substrate and a step of forming the epitaxial layer differently. Exposing the substrate by patterning by means of isotropic etching, and forming the anode region of the light receiving element in the exposed substrate by diffusion and simultaneously forming the base region of the amplification element in the epitaxial layer by diffusion A method of manufacturing a semiconductor device, comprising: a step of forming an emitter region in the base region by diffusion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63058271A JP2688609B2 (en) | 1988-03-14 | 1988-03-14 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63058271A JP2688609B2 (en) | 1988-03-14 | 1988-03-14 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01232774A JPH01232774A (en) | 1989-09-18 |
JP2688609B2 true JP2688609B2 (en) | 1997-12-10 |
Family
ID=13079517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63058271A Expired - Fee Related JP2688609B2 (en) | 1988-03-14 | 1988-03-14 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2688609B2 (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62158372A (en) * | 1986-01-07 | 1987-07-14 | Oki Electric Ind Co Ltd | Light-receiving element and manufacture thereof |
JPS62247563A (en) * | 1986-04-18 | 1987-10-28 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1988
- 1988-03-14 JP JP63058271A patent/JP2688609B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01232774A (en) | 1989-09-18 |
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