JPH0831462B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to the structure of a bipolar transistor and its integrated circuit.

(Prior Art) Conventionally, for example, a high-concentration n-type buried impurity layer is provided in a region where an element active region is to be formed on an n-type silicon substrate by an ion implantation method or the like, and a collector region is formed on the collector region. After epitaxially growing the layer, a p-type base diffusion region and a high-concentration n-type emitter region are provided therein to form an npn-type bipolar transistor (for example, eye.
EE, Journal of Solead State Circuits (IEEE, J, Solid-State Circuits, Vo
l.SC-16, No. 5, pp.424-429, 1981)).

(Problems to be Solved by the Invention) FIG. 2 shows a schematic sectional structure of a conventional npn-type bipolar transistor, in which 101 is a p-type silicon substrate, 102 is a high-concentration n-type buried impurity layer, and 103. Is an n-type epitaxial growth layer, 104 is a p-type channel stopper region, 1
A structure in which 05 is a field oxide film, 106 is a base region, 107 is an emitter region, 108 is a collector contact region, 109 is an interlayer insulating film, and 110 is each metal wiring electrode is often used.

Thus, in the conventional bipolar transistor, the emitter / base / collector regions are arranged in this order on the surface of the semiconductor layer. Since the wiring electrodes are taken out from the respective regions, it is difficult to reduce the unit size of the transistor, and it is necessary to provide a margin in the wiring region so that the respective wirings do not cross each other. It was an obstacle to high integration.

It is an object of the present invention to provide a new bipolar transistor or integrated circuit structure that solves these problems.

(Means for Solving Problems) In the present invention, an emitter / base / collector region is formed in this order in a semiconductor thin film layer separated by an insulator element separation region, and the semiconductor thin film layer is formed on the collector region side. In a semiconductor device in which a bipolar transistor having a collector impurity diffusion region provided on the surface of the semiconductor thin film layer in contact with the insulator layer is integrated on the support substrate. A first collector electrode is provided by opening the insulator layer on the impurity diffusion region, and on the emitter side is an impurity region of the same conductivity type as the collector impurity diffusion region provided in the semiconductor thin film layer. A second collector electrode is provided by opening the interlayer insulating film so that the collector wiring has a minimum collector wiring distance through the collector electrode. Is connected via the first collector electrode or the second collector electrode, and the insulating layer and the supporting substrate are adhered by an insulating adhesive layer.

(Function) In this bipolar transistor structure, the collector electrode wiring is provided on the impurity diffusion region for collector,
It is not necessary to form the collector impurity diffusion region on the semiconductor surface, and the unit size of the transistor can be reduced to the sum of the sizes of the base and emitter regions.

According to the present invention, the collector electrode is formed on the side opposite to the base and emitter regions, so that the unit size of the transistor is significantly reduced. In addition, since the collector electrode wiring is formed separately from the base and emitter wiring, the area required for the wiring can be greatly reduced. Due to these synergistic effects, remarkable features are exhibited in reducing the chip area of the bipolar integrated circuit or increasing the density of elements.

(Example) FIG. 1 is a schematic cross-sectional view showing a part of the structure of the present invention, which is compared with FIG. 2 showing a conventional structure. In FIG. 1, 1 is a high-concentration n-type buried impurity layer, 2 is an epitaxial layer, 3 is a field insulating film, 4 is a base region,
Reference numeral 5 is an emitter region, 6 is a collector contact region, 7 and 9 are interlayer insulating films, 8 is an electrode wiring formed on the surface of a semiconductor layer, 10 is a collector electrode wiring, 11 is a protective film, 12 is an adhesive layer, and 13 is a support. Each of the substrates is shown.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 3 is a schematic sectional view showing the manufacturing process of the npn bipolar transistor. An n-type high concentration impurity layer 202 is formed by ion-implanting arsenic on the entire surface of a p-type silicon substrate 201 having a specific resistance of about 10 Ωcm. Subsequently, an epitaxial layer 203 having a thickness of about 1 μm is grown by a vapor phase growth method, and then a field insulating film 204 having a thickness of 1 μm for element isolation is formed by a selective oxidation method (LOCOS method). Then, p-type base diffusion region 20 is formed by ion implantation and heat treatment.
5, and after forming the high-concentration p-type base contact region 206,
Polycrystalline silicon containing n-type impurities is deposited by a CVD method, and the polycrystalline silicon other than the emitter region is removed by a photo-etching technique. Appropriate heat treatment is performed to form an n-type emitter diffusion region 207 and an emitter contact region 208.
Next, an interlayer insulating film 209, for example, a silicon oxide film is deposited by a CVD method, each contact hole is provided, aluminum is sputter-deposited, and a wiring pattern is formed by using a photo-etching technique. In this way, the base and emitter electrode wirings 210 are obtained, and the structure of FIG. 3A is formed. After depositing a protective film 211, for example, a silicon oxide film by a low temperature CVD method, an adhesive layer 212 such as an epoxy polymer resin is spin-coated and another supporting substrate 213 such as a glass plate is attached to it. Thus, FIG. 3 (b) is obtained. Next, the silicon substrate 201 is removed from the back surface by a mechanopolishing method until the bottom of the field insulating film 204 is exposed. For example, when colloidal silica is used as the abrasive grains and organic amine is used as the chemical liquid, the field insulating film 204 can be used as a stopper to polish the silicon layer, and a thin, flat and smooth silicon surface can be obtained. Then, a silicon oxide film of the interlayer insulating film 209 is deposited on the polished silicon surface layer by a low temperature CVD method such as photo CVD or ECR plasma CVD. Next, contact holes are opened by using a photo-etching technique, and a metal film such as aluminum is deposited by a sputter deposition method to form collector electrode wirings 214. At this time, if it is desired to connect the collector electrode to the base or emitter wiring side, the field oxide film in the portion to be connected is preferably opened at the same time when the contact hole in the collector region is opened to perform metal film wiring. Thus, FIG. 3 (c) is obtained. Next, a protective film (for example, a silicon oxide film or a nitride film) 21
After depositing 5, an insulating adhesive layer 216 having a property different from that of the material of the adhesive layer 212 is formed on the protective film 215, and another supporting substrate 217 is formed.
3D is obtained by adhering. An organic polymer material such as a polyimide resin or an inorganic low melting point material such as lead glass can be used for the adhesive layer 216, and a glass substrate, a silicon substrate, or a metal plate such as a heat radiating material can be used for the supporting substrate 217. Can be selected according to the characteristics of the device.
Finally, the support substrate 213 can be easily peeled off by immersing it in a solvent such as trichlene that causes the contact layer 212 to contact without affecting the adhesive layer 216. FIG. 3E is formed in this way, and the protective film 211 on the bonding pad can be removed by using a photo-etching technique if necessary. In this way, the unit size of the conventional semiconductor layer with the base, emitter, and collector wiring on one side is
While it was 21 μm, it can be reduced to 14 μm in the present invention, and high density can be achieved.

Further, when the collector wiring is formed on the same side as the emitter and the collector wiring as described in FIG. 3 is formed on the side opposite to the emitter as in the conventional example, a schematic cross section is shown in FIG. In addition, the collector electrode wiring of the transistor can be mixedly formed on the base / emitter region side and the high-concentration impurity diffusion region side. When performing complicated wiring, the wiring layer can be selected so as to minimize the collector wiring distance as in this embodiment.

In the first and second embodiments, the base / emitter region is formed so as to be on the surface, but the collector electrode wiring side may be on the surface.

(Effect of the Invention) In the bipolar transistor manufactured according to the present invention, the collector electrode wiring can be formed separately from the base / emitter wiring and the layer, so that the area required for the wiring can be reduced. Further, when the collector electrode is formed in the high-concentration impurity region without providing it on the base / emitter surface, the unit size of the transistor is significantly reduced, which is very effective for increasing the density of the device. Further, when forming a complicated circuit, it is possible to shorten the collector wiring distance, which is also advantageous in increasing the speed of the device.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an npn type bipolar transistor showing an example of the structure of the present invention, and FIG. 2 is a schematic sectional view of a conventional structure shown in comparison with FIG. FIG. 3 is a schematic cross-sectional view showing the manufacturing steps of a bipolar transistor in the order of steps as a typical embodiment for realizing the present invention, and FIG. 4 is a schematic view in which collector wiring has two layers in order to shorten the wiring. FIG. The numbers in the figure are as follows. 1,102,202, ... High-concentration n-type buried impurity layer, 2,103,203 ... n-type epitaxial growth layer, 3,105,204 ... Field insulating film, 4,106,205 ... Base region, 5,107,207 ... Emitter region, 6,108 ... Collector contact region, 7,9,109,209 ... … Interlayer insulating film, 8,110,210 …… Electrode wiring formed on semiconductor surface, 10,214 …… Collector electrode wiring, 12,212,216 …… Adhesive layer, 13,213,217… Support substrate, 101,201 …… P-type silicon substrate, 104 …… P-type channel stopper Area, 206 …… Base contact area, 208 …… Emitter contact area, 11,211,215 …… Protective film.

Claims (1)

[Claims] 1. An emitter / base / collector region is formed in this order in a semiconductor thin film layer that is element-isolated by an insulator element isolation region, and the semiconductor thin film layer forms an insulator layer on a support substrate on the collector region side. In a semiconductor device in which a bipolar transistor having a collector impurity diffusion region formed on the surface of the semiconductor thin film layer in contact with the insulator layer is integrated, the insulator layer on the collector impurity diffusion region is formed. And a first collector electrode is provided by opening the first collector electrode, and an interlayer insulating film on the impurity region of the same conductivity type as the collector impurity diffusion region provided in the semiconductor thin film layer on the emitter side is opened by the second collector electrode. A collector electrode of the first collector electrode is provided so that the collector wire has a minimum collector wire distance through the collector electrode. The semiconductor device characterized by being connected through a second collector electrode, and said insulating layer and the support substrate are bonded by an insulating adhesive layer.