JPH0719836B2 - Method for manufacturing dielectric-isolated semiconductor device - Google Patents

Method for manufacturing dielectric-isolated semiconductor device

Info

Publication number
JPH0719836B2
JPH0719836B2 JP60021872A JP2187285A JPH0719836B2 JP H0719836 B2 JPH0719836 B2 JP H0719836B2 JP 60021872 A JP60021872 A JP 60021872A JP 2187285 A JP2187285 A JP 2187285A JP H0719836 B2 JPH0719836 B2 JP H0719836B2
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
semiconductor substrate
insulator
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60021872A
Other languages
Japanese (ja)
Other versions
JPS61182241A (en
Inventor
恒男 塚越
純一 大浦
弘通 大橋
優 新保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60021872A priority Critical patent/JPH0719836B2/en
Publication of JPS61182241A publication Critical patent/JPS61182241A/en
Publication of JPH0719836B2 publication Critical patent/JPH0719836B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に係り、特に誘電体を用
いて素子分離を行う誘電体分離形半導体装置の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dielectric isolation type semiconductor device in which elements are isolated using a dielectric.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来ICやLSIなどで各素子間の分離を絶縁体で行なうい
わゆる誘電体分離法は、pn接合分離に比べて、(1)も
れ電流を極めて小さくすることができる、(2)耐圧を
大きくすることができる、(3)電圧印加の方向に気を
配る必要がない、等の利点を有する。
Compared to pn junction isolation, the so-called dielectric isolation method in which conventional ICs and LSIs are used to isolate elements from each other with an insulator can (1) greatly reduce leakage current, and (2) increase breakdown voltage. It has advantages such as that (3) it is not necessary to pay attention to the direction of voltage application.

理想的な誘電体分離は、各素子を電極接続部を除いて絶
縁体で完全に包み込むことで達成される。このような素
子は例えば、サファイア上にシリコンをエピタキシャル
成長させたSOS基板を用いて形成することができる。し
かしながら、サファイアは高価であり、またシリコンと
の結晶整合性も完全ではなく良質の単結晶膜が得られな
い、膜厚を充分厚くすることができない、などの理由
で、作製できる素子の種類に制限がある。
The ideal dielectric isolation is achieved by completely wrapping each element with an insulator except for the electrode connections. Such an element can be formed using, for example, an SOS substrate in which silicon is epitaxially grown on sapphire. However, sapphire is expensive, and the crystal matching with silicon is not perfect, so that a high-quality single crystal film cannot be obtained, and the film thickness cannot be increased sufficiently. There is a limit.

サファイアのような絶縁体基板を用いない誘電体分離法
も、これまで数多く提案されている。その一例を第2図
(a)〜(e)を用いて説明する。まず第2図(a)に
示すように、シリコン単結晶基板41の上にエピタキシャ
ル法により形成したシリコン単結晶層42(421,422)に
所望の拡散層43(431,432)を形成した素子を作製し、
更にメサエッチングにより各素子間を分離して全面をSi
O2等の絶縁膜44で覆う。この後第2図(b)に示すよう
に、これら素子の上部に多結晶シリコン支持体層45を堆
積し、次いで第2図(c)に示すようにシリコン基板41
を研磨やエッチング等により各素子が完全に分離される
まで削り落してその表面を絶縁膜46で覆う。この後第2
図(d)に示すように、絶縁膜46側に再度多結晶シリコ
ン支持体層47を堆積する。そして第2図(e)に示すよ
うに、支持体層45をエッチング除去して誘電体分離され
た素子を得る。
Many dielectric isolation methods that do not use an insulating substrate such as sapphire have been proposed so far. One example thereof will be described with reference to FIGS. 2 (a) to (e). First, as shown in FIG. 2A, a desired diffusion layer 43 (43 1 , 43 2 ) is formed on a silicon single crystal layer 42 (42 1 , 42 2 ) formed on a silicon single crystal substrate 41 by an epitaxial method. A device having
Furthermore, each element is separated by mesa etching and the entire surface is
Cover with an insulating film 44 such as O 2 . Thereafter, as shown in FIG. 2 (b), a polycrystalline silicon support layer 45 is deposited on these elements, and then a silicon substrate 41 is formed as shown in FIG. 2 (c).
Are ground by polishing or etching until each element is completely separated, and the surface thereof is covered with an insulating film 46. Second after this
As shown in FIG. 3D, the polycrystalline silicon support layer 47 is deposited again on the insulating film 46 side. Then, as shown in FIG. 2 (e), the support layer 45 is removed by etching to obtain a dielectrically separated element.

この様な従来の方法での最大の問題は、支持体層の形成
が必須である点にある。支持体層の堆積や除去等の余分
な工程が必要なだけでなく、例えば良く使われる多結晶
シリコンの場合でも、堆積速度が遅いために、研磨等の
工程に耐え得る充分な厚さを得るために非常に長い時間
を要する。支持体層の堆積工程を省略する目的で、例え
ば第2図(c)の工程で素子分離を終了し、素子の裏面
から配線を取り出すことも提案されている。しかしこの
方法は、配線構造が複雑になり種々の制約条件が新たに
加わる。また支持体としてシリコン基板等を酸化物やガ
ラスなどの接着層を介して張付ける方法も提案されてい
るが、この方法では、1300℃を超える温度と数10kg/cm2
以上の高い圧力が必要であった。この様な条件では、ク
リープなどにより基板に変形を生じたり、素子領域に形
成された拡散層の不純物分布が変化する等の不都合が生
じる。
The biggest problem with such a conventional method is that the formation of a support layer is essential. Not only extra steps such as deposition and removal of the support layer are required, but also in the case of commonly used polycrystalline silicon, since the deposition rate is slow, a sufficient thickness to withstand the steps such as polishing is obtained. It takes a very long time. For the purpose of omitting the step of depositing the support layer, it has been proposed to complete the element isolation in the step of FIG. 2C and take out the wiring from the back surface of the element. However, in this method, the wiring structure becomes complicated and various constraints are newly added. A method of attaching a silicon substrate or the like as a support through an adhesive layer such as oxide or glass has also been proposed, but in this method, a temperature exceeding 1300 ° C. and several tens kg / cm 2 are used.
The above high pressure was required. Under such a condition, the substrate may be deformed due to creep or the like, and the impurity distribution of the diffusion layer formed in the element region may be changed.

〔発明の目的〕[Object of the Invention]

本発明は、上記した点に鑑みなされたもので、簡便な工
程で信頼性の高い誘電体分離を可能とした半導体装置の
製造方法を提供することを目的とする。
The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of highly reliable dielectric isolation with simple steps.

〔発明の概要〕[Outline of Invention]

本発明は、二枚の半導体単結晶基板の表面が充分平滑に
鏡面研磨されている時、その研磨面同士を充分に清浄な
雰囲気下で直接密着させることにより強固な基板接合体
が得られるという知見に基き、この技術を誘電体分離に
適用する。本発明は、鏡面研磨された第1及び第2の半
導体基板の少なくとも一方の半導体基板の鏡面に酸化膜
を形成し、この酸化膜を介して鏡面同士を対向させて密
着させることで第1及び第2の半導体基板を接合する接
合工程と;前記工程で得られた基板接合体を200℃以上
に加熱する熱処理工程と;第1の半導体基板の厚みを所
望の厚さにする工程と;第1の半導体基板表面に半導体
層をエピタキシャル成長せしめる工程と;前記半導体層
と第1の半導体基板とを貫通し前記酸化膜に達する絶縁
体を埋め込む工程とを具備した誘電体分離形半導体装置
の製造方法において、前記第1の半導体基板の厚みを所
望の厚さにする工程の後に第1の半導体基板を島状半導
体領域に分離する分離溝を形成し、この分離溝に絶縁体
を埋め込んだ後に、前記半導体層をエピタキシャル成長
せしめ、この半導体層に分離溝を形成し、この分離溝に
絶縁体を埋め込んで第1の半導体基板に形成された分離
溝中の絶縁体と連結させて前記半導体層と第1の半導体
基板とを貫通した絶縁体を形成することを特徴とする誘
電体分離形半導体装置の製造方法である。
According to the present invention, when the surfaces of two semiconductor single crystal substrates are mirror-polished to be sufficiently smooth, a strong substrate bonded body can be obtained by directly adhering the polished surfaces to each other in a sufficiently clean atmosphere. Based on our findings, we apply this technique to dielectric isolation. According to the present invention, an oxide film is formed on the mirror surface of at least one of the first and second semiconductor substrates that have been mirror-polished, and the mirror surfaces are made to face each other through the oxide film to be in close contact with each other. A bonding step of bonding the second semiconductor substrate; a heat treatment step of heating the substrate bonded body obtained in the above step to 200 ° C. or higher; a step of making the first semiconductor substrate have a desired thickness; 1. A method for manufacturing a dielectric isolation type semiconductor device, comprising: a step of epitaxially growing a semiconductor layer on a surface of a first semiconductor substrate; and a step of burying an insulator that penetrates the semiconductor layer and the first semiconductor substrate and reaches the oxide film. In the step 1, after forming the desired thickness of the first semiconductor substrate, an isolation groove for isolating the first semiconductor substrate into island-shaped semiconductor regions is formed, and an insulator is embedded in the isolation groove. The semiconductor Is epitaxially grown to form an isolation groove in the semiconductor layer, and an insulator is embedded in the isolation groove to connect with the insulator in the isolation groove formed in the first semiconductor substrate to form the semiconductor layer and the first semiconductor. A method of manufacturing a dielectric isolation type semiconductor device, which comprises forming an insulator penetrating a substrate.

〔発明の効果〕〔The invention's effect〕

本発明によれば多結晶シリコンなどの支持体層を堆積し
たり、除去したりする工程を用いることがなく、反りの
発生による問題がない為、極めて簡単に素子分離を行な
った半導体装置を得ることができる。又溝の形成を順次
重ねる事により半導体結晶層の厚みを大きくすることが
できる。さらに表面が平坦化になっている為、配線が容
易にできる。
According to the present invention, since a step of depositing or removing a support layer such as polycrystalline silicon is not used and there is no problem due to occurrence of warpage, a semiconductor device in which element isolation is performed is obtained very easily. be able to. The thickness of the semiconductor crystal layer can be increased by sequentially forming the grooves. Furthermore, since the surface is flat, wiring can be facilitated.

〔発明の実施例〕Example of Invention

以下本発明の実施例を図面を参照して説明する。第1図
(a)〜(k)は、本発明を用いたフォトダイオードア
レイの一実施例である。単結晶基板11と面指数100,抵抗
率0.03Ω−cm以下でN型の第2のシリコン単結晶基板12
を用意する。この例では、第2のシリコン基板12の表面
に酸化膜等の第1の絶縁膜13が形成されている。これら
の基板の相対向する面は鏡面研磨されている。これらの
基板11,12を第1図(b)に示すように密着させ200℃以
上の温度で熱処理して接合させる。室温で密着させるだ
けでもかなりの接合強度が得られるが、200℃以上で熱
処理することにより、接合強度が著しく改善される。但
し熱処理温度の上限は、クリープなどを生じないように
1300℃とすることが必要である。
Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to (k) show an embodiment of a photodiode array using the present invention. Single crystal substrate 11 and N-type second silicon single crystal substrate 12 having a surface index of 100 and a resistivity of 0.03 Ω-cm or less
To prepare. In this example, a first insulating film 13 such as an oxide film is formed on the surface of the second silicon substrate 12. The opposite surfaces of these substrates are mirror-polished. These substrates 11 and 12 are brought into close contact with each other as shown in FIG. 1 (b) and heat-treated at a temperature of 200 ° C. or more to join them. Although it is possible to obtain a considerable bonding strength just by bringing them into close contact at room temperature, the heat treatment at 200 ° C or higher significantly improves the bonding strength. However, the upper limit of heat treatment temperature is to prevent creep etc.
It is necessary to set the temperature to 1300 ° C.

このように形成された基板接合体に、本実施例では基板
12にエピタキシャル膜を形成する。そのために第1図
(c)に示すように、基板12を必要な厚さになるまで研
磨,エッチング等により削り取る。次に第1図(d)に
示すように基板12の表面の一部をレジスト膜や酸化膜等
で覆い異方向性エッチングによって幅1〜2μmの溝を
第1の絶縁膜13に達するまで形成し、この後第1図
(e)に示すように溝が第2の絶縁膜14で埋まる条件で
酸化膜を形成する。さらに第1図(f)に示すように一
般に知られているPEP工程によって、前記溝幅に対して
若干大きい5μm幅の酸化膜を残して除去する。
In the present embodiment, the substrate bonded body thus formed is
An epitaxial film is formed on 12. Therefore, as shown in FIG. 1 (c), the substrate 12 is scraped off by polishing, etching or the like until the required thickness is obtained. Next, as shown in FIG. 1D, a part of the surface of the substrate 12 is covered with a resist film, an oxide film or the like to form a groove having a width of 1 to 2 μm by the anisotropic etching until the first insulating film 13 is reached. Then, thereafter, as shown in FIG. 1E, an oxide film is formed under the condition that the groove is filled with the second insulating film 14. Further, as shown in FIG. 1 (f), a generally known PEP process is performed to remove the oxide film having a width of 5 μm, which is slightly larger than the groove width.

次にこの上に第1図(g)に示したように、基板12より
不純物濃度の低い第3の半導体結晶のN型のエピタキシ
ャル成長膜15を所望の厚さで形成する。
Next, as shown in FIG. 1 (g), an N-type epitaxial growth film 15 of a third semiconductor crystal having a lower impurity concentration than that of the substrate 12 is formed thereon to a desired thickness.

次に第1図(h)に示すようにエピタキシャル成長膜15
の表面の第2の絶縁膜14の真上を再び異方向性エッチン
グによって幅1〜2μmの溝を絶縁膜14に達するまで形
成し、この後第1図(i)に示すように溝が第3の絶縁
膜16で埋まるように酸化膜を形成する。この様に形成し
た基板15の一部領域にN型の不純物であるたとえばリン
を選択的に基板12に達するまで拡散し、次いでP型の不
純物であるたとえばボロンを選択的に拡散しP層18を得
る。この様に構成されたフォトダイオード(第1図
(j))を直列接続させる為にアルミニウムを約10μm
の厚さで蒸着し、配線19を形成して第1図(k)のよう
な所望の半導体装置が完成する。
Next, as shown in FIG. 1 (h), an epitaxial growth film 15 is formed.
A groove having a width of 1 to 2 μm is formed right above the second insulating film 14 on the surface of the substrate by anisotropic etching again until the insulating film 14 is reached. After that, the groove is formed as shown in FIG. 1 (i). An oxide film is formed so as to be filled with the third insulating film 16. In a part of the substrate 15 thus formed, N-type impurities such as phosphorus are selectively diffused until reaching the substrate 12, and then P-type impurities such as boron are selectively diffused to form the P layer 18. To get About 10 μm of aluminum is used to connect the photodiodes (Fig. 1 (j)) configured in this way in series.
To form a wiring 19, and a desired semiconductor device as shown in FIG. 1 (k) is completed.

以上のようにして本実施例によれば、信頼性の高い誘電
体分離構造の半導体装置を簡単に作ることができる。
As described above, according to this embodiment, a highly reliable semiconductor device having a dielectric isolation structure can be easily manufactured.

本発明の最大の特徴は、絶縁膜を介して直接接合した半
導体単結晶基板の上に所望の不純物濃度と厚みを持った
半導体結晶を何段にも積み重ねていく事ができる。又配
線形状を変える事によって分離された素子の直列接続や
並列接続が容易に可能となる。
The greatest feature of the present invention is that semiconductor crystals having a desired impurity concentration and thickness can be stacked in multiple layers on a semiconductor single crystal substrate directly bonded through an insulating film. Further, by changing the wiring shape, it is possible to easily connect the separated elements in series or in parallel.

本発明は上記実施例ではフォトダイオードについて説明
したが、トランジスタやサイリスタ,MOS FET等も形成す
る事ができる。又絶縁物を埋込む溝の形成の加工におい
て一方向の溝を作らなければ隣の半導体装置とを任意に
電気的に結合することができる。
Although the present invention describes the photodiode in the above embodiment, a transistor, a thyristor, a MOS FET or the like can be formed. Further, in forming the groove for burying the insulator, if a groove in one direction is not formed, an adjacent semiconductor device can be electrically connected arbitrarily.

又本実施例では、絶縁膜を介して直接接合した半導体単
結晶基板を使って説明したが、半導体単結晶中に酸素を
イオン注入して絶縁膜を表面より浅い領域に形成し、こ
の上にエピタキシャル成長によって半導体結晶を積み重
ねる方法でもまったく同じ効果を得ることができる。
In this embodiment, the semiconductor single crystal substrate directly bonded through the insulating film has been described. However, oxygen is ion-implanted into the semiconductor single crystal to form the insulating film in a region shallower than the surface, The same effect can be obtained by stacking semiconductor crystals by epitaxial growth.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の素子製造工程を示す図、第
2図は従来の誘電体分離法による素子製造工程を示す図
である。 11……第1のシリコン単結晶基板 12……第2の 〃 13……第1の絶縁膜 14……第2の 〃 15……エピタキシャル成長膜 16……第3の絶縁膜 17……N型拡散層 18……P型拡散層 19……配線電極
FIG. 1 is a diagram showing a device manufacturing process of an embodiment of the present invention, and FIG. 2 is a diagram showing a device manufacturing process by a conventional dielectric isolation method. 11 …… First silicon single crystal substrate 12 …… Second 〃13 …… First insulating film 14 …… Second 〃15 …… Epitaxial growth film 16 …… Third insulating film 17 …… N type Diffusion layer 18 …… P-type diffusion layer 19 …… Wiring electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 新保 優 神奈川県川崎市幸区小向東芝町1 株式会 社東芝総合研究所内 (56)参考文献 特開 昭56−155547(JP,A) 特公 昭49−26455(JP,B1) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yu Shinbo 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research Institute Ltd. (56) Reference JP-A-56-155547 (JP, A) Japanese Patent Publication Sho 49-26455 (JP, B1)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】鏡面研磨された第1及び第2の半導体基板
の少なくとも一方の半導体基板の鏡面に酸化膜を形成
し、この酸化膜を介して鏡面同士を対向させて密着させ
ることで第1及び第2の半導体基板を接合する接合工程
と;前記工程で得られた基板接合体を200℃以上に加熱
する熱処理工程と;第1の半導体基板の厚みを所望の厚
さにする工程と;第1の半導体基板表面に半導体層をエ
ピタキシャル成長せしめる工程と;前記半導体層と第1
の半導体基板とを貫通し前記酸化膜に達する絶縁体を埋
め込む工程とを具備した誘電体分離形半導体装置の製造
方法において、前記第1の半導体基板の厚みを所望の厚
さにする工程の後に第1の半導体基板を島状半導体領域
に分離する溝を形成し、この分離溝に絶縁体を埋め込ん
だ後に、前記半導体層をエピタキシャル成長せしめ、こ
の半導体層に分離溝を形成し、この分離溝に絶縁体を埋
め込んで第1の半導体基板に形成された分離溝中の絶縁
体と連結させて前記半導体層と第1の半導体基板とを貫
通した絶縁体を形成することを特徴とする誘電体分離形
半導体装置の製造方法。
1. An oxide film is formed on the mirror surface of at least one of the first and second semiconductor substrates that have been mirror-polished, and the mirror surfaces are made to face each other through the oxide film and are brought into close contact with each other. And a joining step of joining the second semiconductor substrate; a heat treatment step of heating the substrate joined body obtained in the above step to 200 ° C. or higher; a step of making the first semiconductor substrate have a desired thickness; Epitaxially growing a semiconductor layer on the surface of the first semiconductor substrate; the semiconductor layer and the first semiconductor layer;
And a step of burying an insulator that penetrates the semiconductor substrate and reaches the oxide film. After the step of adjusting the thickness of the first semiconductor substrate to a desired thickness, A groove for separating the first semiconductor substrate into island-shaped semiconductor regions is formed, an insulator is embedded in the separation groove, and then the semiconductor layer is epitaxially grown to form a separation groove in the semiconductor layer. A dielectric isolation, characterized in that an insulator is embedded and is connected to an insulator in a separation groove formed in a first semiconductor substrate to form an insulator penetrating the semiconductor layer and the first semiconductor substrate. Method of manufacturing a semiconductor device.
JP60021872A 1985-02-08 1985-02-08 Method for manufacturing dielectric-isolated semiconductor device Expired - Lifetime JPH0719836B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60021872A JPH0719836B2 (en) 1985-02-08 1985-02-08 Method for manufacturing dielectric-isolated semiconductor device

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Application Number Priority Date Filing Date Title
JP60021872A JPH0719836B2 (en) 1985-02-08 1985-02-08 Method for manufacturing dielectric-isolated semiconductor device

Publications (2)

Publication Number Publication Date
JPS61182241A JPS61182241A (en) 1986-08-14
JPH0719836B2 true JPH0719836B2 (en) 1995-03-06

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106466A (en) * 1987-10-19 1989-04-24 Fujitsu Ltd Manufacture of semiconductor device
JPH01251636A (en) * 1988-03-31 1989-10-06 Toshiba Corp Manufacture of dielectric isolation wafer
JP3036970B2 (en) * 1992-06-09 2000-04-24 日本電気株式会社 Semiconductor integrated circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4926455A (en) * 1972-07-11 1974-03-08
JPS56155547A (en) * 1980-05-06 1981-12-01 Nec Corp Semiconductor device

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JPS61182241A (en) 1986-08-14

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