JP2003098025A - Semiconductor sensor and its manufacturing method - Google Patents

Semiconductor sensor and its manufacturing method

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Publication number
JP2003098025A
JP2003098025A JP2001292738A JP2001292738A JP2003098025A JP 2003098025 A JP2003098025 A JP 2003098025A JP 2001292738 A JP2001292738 A JP 2001292738A JP 2001292738 A JP2001292738 A JP 2001292738A JP 2003098025 A JP2003098025 A JP 2003098025A
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JP
Japan
Prior art keywords
oxide film
crystal silicon
single crystal
silicon
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001292738A
Other languages
Japanese (ja)
Other versions
JP4845308B2 (en
Inventor
Mitsuru Hirose
満 広瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Copal Electronics Corp
Original Assignee
Nidec Copal Electronics Corp
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Priority to JP2001292738A priority Critical patent/JP4845308B2/en
Publication of JP2003098025A publication Critical patent/JP2003098025A/en
Application granted granted Critical
Publication of JP4845308B2 publication Critical patent/JP4845308B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a highly sensitive semiconductor sensor hardly generating a leakage current even in a high temperature environment over 120 deg.C, capable of adjusting easily the impurity concentration in the depth direction of a piezo resistance element, and its manufacturing method. SOLUTION: This semiconductor sensor is constituted as follows. After removing an oxide film formed on a silicon substrate except a part where the piezo resistance element is to be formed, an n-type or p-type epitaxial layer having a desired impurity concentration is developed, to thereby develop single-crystal silicon on the part except the oxide film and polycrystal silicon on the oxide film respectively. In the state where the polycrystal silicon formed on the oxide film is removed, the epitaxial layer is developed until the single-crystal silicon developed from the part except the oxide film covers the oxide film and has the desired thickness. Hereby, the single-crystal silicon having the desired impurity concentration is formed on the oxide film, and the single-crystal silicon is used as the piezo resistance element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ピエゾ抵抗効果を
利用した半導体センサに関し、特に120℃以上の高温
での使用に適応した、高感度な半導体センサ及びその製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor sensor utilizing the piezoresistive effect, and more particularly to a highly sensitive semiconductor sensor adapted for use at a high temperature of 120 ° C. or higher and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来のピエゾ抵抗効果を利用した半導体
センサは、n型(あるいはp型)のシリコン基板中に拡
散法やイオン注入法により、p型(あるいはn型)のピ
エゾ抵抗素子を形成していた。
2. Description of the Related Art A conventional semiconductor sensor utilizing the piezoresistive effect forms a p-type (or n-type) piezoresistive element in an n-type (or p-type) silicon substrate by a diffusion method or an ion implantation method. Was.

【0003】[0003]

【発明が解決しようとする課題】しかし、この方式では
120℃以上の高温になると、PN接合からの漏れ電流
が増加し、測定精度が大幅に悪化してしまうという問題
があった。
However, this method has a problem that when the temperature is higher than 120 ° C., the leakage current from the PN junction increases and the measurement accuracy deteriorates significantly.

【0004】また、シリコン基板の表面に形成された絶
縁膜上に多結晶シリコンを形成し、ここにピエゾ抵抗素
子を形成することにより、シリコン基板とピエゾ抵抗素
子とを絶縁膜により電気的に分離し、PN接合による漏
れ電流を防ぐ方法も取られているが、多結晶シリコンは
単結晶シリコンに比べて結晶性が劣るため、圧力等の応
力に対するピエゾ抵抗素子の出力感度が大幅に低下する
という問題があった。
Further, by forming polycrystalline silicon on an insulating film formed on the surface of a silicon substrate and forming a piezoresistive element there, the silicon substrate and the piezoresistive element are electrically separated by the insulating film. However, although a method of preventing a leakage current due to a PN junction is also taken, since the crystallinity of polycrystalline silicon is inferior to that of single crystal silicon, the output sensitivity of the piezoresistive element with respect to stress such as pressure is significantly reduced. There was a problem.

【0005】さらに、SOIウェハ等を利用することに
より、結晶性に依存する感度低下は抑制することができ
るが、ピエゾ抵抗素子が拡散法やイオン注入法により形
成されているため、ピエゾ抵抗素子の深さ方向に対する
不純物濃度が均一にならず、最も大きな応力を受けるシ
リコンと酸化膜との界面付近のピエゾ抵抗素子の不純物
濃度が一般的に低くなってしまうことから、ピエゾ抵抗
効果が十分に発揮されず、結果として感度が低下してし
まうという問題があった。
Further, by using an SOI wafer or the like, it is possible to suppress the decrease in sensitivity depending on the crystallinity, but since the piezoresistive element is formed by the diffusion method or the ion implantation method, the piezoresistive element The impurity concentration in the depth direction is not uniform, and the impurity concentration of the piezoresistive element in the vicinity of the interface between silicon and the oxide film, which receives the largest stress, is generally low, so the piezoresistive effect is fully exerted. However, there is a problem that the sensitivity is lowered as a result.

【0006】本発明は以上のような従来の欠点に鑑み、
これらの欠点を除去するためになされたものであり、1
20℃以上の高温環境下にあっても漏れ電流がほとんど
発生することがなく、ピエゾ抵抗素子の深さ方向に対す
る不純物濃度の調整が容易な、高感度な半導体センサ及
びその製造方法を得ることを目的としている。
The present invention has been made in view of the above-mentioned conventional drawbacks.
It was made to eliminate these drawbacks.
To obtain a highly sensitive semiconductor sensor and a manufacturing method thereof, in which a leakage current hardly occurs even in a high temperature environment of 20 ° C. or higher, and the impurity concentration in the depth direction of a piezoresistive element can be easily adjusted. Has an aim.

【0007】本発明の目的と新規な特徴は、次の説明を
添付図面と照らし合わせて読むことにより、より完全に
明らかになるであろう。ただし、図面はもっぱら解説の
ためのものであって、本発明の技術的範囲を限定するも
のではない。
The objects and novel features of the present invention will become more fully apparent by reading the following description in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the technical scope of the present invention.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明はシリコン基板に形成した起歪部にピエゾ抵
抗素子を配置した半導体センサにおいて、シリコン基板
上に酸化膜を形成し、この酸化膜をピエゾ抵抗素子を形
成する部分を残して除去した後、所望の不純物濃度のn
型あるいはp型のエピタキシャル層を成長させることに
より、前記酸化膜上以外の部分には単結晶シリコンを、
前記酸化膜上には多結晶シリコンを各々成長させ、この
酸化膜上に形成された多結晶シリコンを除去した状態
で、酸化膜上以外の部分から成長した単結晶シリコンが
前記酸化膜上を覆い所望の厚さになるまでエピタキシャ
ル層を成長させることにより、前記酸化膜上に所望の不
純物濃度の単結晶シリコンを形成し、酸化膜上以外の部
分に成長した単結晶シリコンを除去した後、前記酸化膜
上に形成された単結晶シリコンを絶縁膜で覆うことによ
り、この単結晶シリコンをピエゾ抵抗素子とすることに
より半導体センサを構成している。
In order to achieve the above object, the present invention is a semiconductor sensor in which a piezoresistive element is arranged in a strain-generating part formed on a silicon substrate, and an oxide film is formed on the silicon substrate. After removing the oxide film leaving a portion for forming a piezoresistive element, n of a desired impurity concentration is obtained.
-Type or p-type epitaxial layer is grown so that single-crystal silicon is formed on the portion other than on the oxide film.
Polycrystalline silicon is grown on the oxide film, and the polycrystalline silicon formed on the oxide film is removed, and the single crystal silicon grown from a portion other than the oxide film covers the oxide film. The epitaxial layer is grown to a desired thickness to form single crystal silicon having a desired impurity concentration on the oxide film, and the single crystal silicon grown on a portion other than the oxide film is removed. By covering the single crystal silicon formed on the oxide film with an insulating film, the single crystal silicon is used as a piezoresistive element to form a semiconductor sensor.

【0009】また、シリコン基板に形成した起歪部にピ
エゾ抵抗素子を配置した半導体センサの製造方法におい
て、シリコン基板上に酸化膜を形成する工程と、この酸
化膜をピエゾ抵抗素子を形成する部分を残して除去する
工程と、所望の不純物濃度のn型あるいはp型のエピタ
キシャル層を成長させ、前記酸化膜上に成長した多結晶
シリコンを除去した状態で、前記酸化膜上を前記シリコ
ン基板上から成長した単結晶シリコンで覆い、該酸化膜
上に所望の厚さの単結晶シリコンを成長させる工程と、
前記酸化膜上以外の部分に成長した単結晶シリコンを除
去する工程と、前記酸化膜上に形成された前記単結晶シ
リコンを絶縁膜で覆う工程とを備えることにより半導体
センサの製造方法を構成している。
Further, in a method of manufacturing a semiconductor sensor in which a piezoresistive element is arranged in a strained portion formed on a silicon substrate, a step of forming an oxide film on the silicon substrate and a portion for forming this piezoresistive element on the oxide film. And removing the polycrystalline silicon grown on the oxide film by growing an n-type or p-type epitaxial layer having a desired impurity concentration and removing the polycrystalline silicon grown on the oxide film from the silicon substrate. Covering with single crystal silicon grown from, and growing single crystal silicon of a desired thickness on the oxide film,
A method of manufacturing a semiconductor sensor is configured by including a step of removing single crystal silicon grown on a portion other than the oxide film and a step of covering the single crystal silicon formed on the oxide film with an insulating film. ing.

【0010】[0010]

【実施の形態】以下、添付図面を参照して本発明の実施
の形態を詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

【0011】図1乃至図2の本発明の実施の形態の一例
を示す図において、1はp型のシリコン基板で、その略
中央部に形成された薄肉の起歪部9には、応力を検知可
能なピエゾ抵抗素子3a,3b,3c,3dが配置され
ており、アルミ等の導体からなるリード部5a,5b,
・・・,5hを介して、アルミ等の導体からなる電極パ
ッド7a,7b,7c,7dへと電気的に接続されてい
る。
In the drawings showing an example of the embodiment of the present invention shown in FIGS. 1 and 2, reference numeral 1 denotes a p-type silicon substrate, and stress is applied to a thin strained portion 9 formed in a substantially central portion thereof. Detectable piezoresistive elements 3a, 3b, 3c, 3d are arranged, and lead portions 5a, 5b, made of a conductor such as aluminum,
, 5h, and electrically connected to the electrode pads 7a, 7b, 7c, 7d made of a conductor such as aluminum.

【0012】ここで、図3の本発明の製造工程を示す図
を参照することにより、その構造を詳細に説明する。
The structure will now be described in detail with reference to FIG. 3 showing the manufacturing process of the present invention.

【0013】(1)p型(100)面のシリコン基板1
の表面に、(2)熱酸化等の方法により0.5μm以下
の酸化膜25aを形成する。ここでは、熱酸化により酸
化膜を形成した例を示しているため、シリコン基板1の
裏面にも酸化膜25bが形成されているが、CVD等の
方法を用いることにより、シリコン基板1の表面のみに
酸化膜25aを形成することもできる。
(1) p-type (100) plane silicon substrate 1
An oxide film 25a having a thickness of 0.5 μm or less is formed on the surface of (2) by a method such as thermal oxidation. Here, since the oxide film is formed by thermal oxidation, the oxide film 25b is also formed on the back surface of the silicon substrate 1. However, by using a method such as CVD, only the front surface of the silicon substrate 1 is formed. Alternatively, the oxide film 25a can be formed.

【0014】(3)この酸化膜25aを、前記ピエゾ抵
抗素子3a,3b,3c,3dを形成する部分を残して
除去(パターニング)することにより、この領域以外の
シリコン基板1を露出させる。
(3) The oxide film 25a is removed (patterned) except for the portions where the piezoresistive elements 3a, 3b, 3c and 3d are formed, so that the silicon substrate 1 other than this region is exposed.

【0015】(4)ピエゾ抵抗素子として適切な不純物
濃度(例えば、2×10の18乗/立方cm程度)とな
るように、ボロン等の不純物がドープされたエピタキシ
ャル層を、エピタキシャル成長により、シリコン基板1
及び酸化膜25a上に成長させる。このとき、図4に示
すように、シリコン基板1上には、シリコン基板1の結
晶方位に依存した単結晶シリコン21が、酸化膜25a
上には、特定の結晶方位が存在しない多結晶シリコン2
3が各々成長する。
(4) An epitaxial layer doped with impurities such as boron so as to have an appropriate impurity concentration (for example, about 2 × 10 18 / cubic cm) as a piezoresistive element is epitaxially grown on a silicon substrate. 1
And on the oxide film 25a. At this time, as shown in FIG. 4, the single crystal silicon 21 depending on the crystal orientation of the silicon substrate 1 is formed on the silicon substrate 1 by the oxide film 25a.
Polycrystalline silicon 2 with no specific crystal orientation on top
3 each grow.

【0016】(5)前記、酸化膜25a上に形成された
多結晶シリコン23をエッチングにより除去する。この
とき、シリコン基板1上に形成された単結晶シリコン2
1も、図5に示すように一部エッチングされる。
(5) The polycrystalline silicon 23 formed on the oxide film 25a is removed by etching. At this time, the single crystal silicon 2 formed on the silicon substrate 1
1 is also partially etched as shown in FIG.

【0017】(6)(4)のエピタキシャル成長工程
と、(5)の多結晶シリコン23のエッチング工程を繰
り返すことにより、酸化膜25a上に形成された多結晶
シリコン23を除去した状態で、シリコン基板1上から
成長した単結晶シリコン21が酸化膜25a上を覆い、
所望の厚さとなるようにエピタキシャル層を成長させる
ことにより、図6に示すように、酸化膜25a上に、所
望の不純物濃度の単結晶シリコン21を形成する。
By repeating the epitaxial growth steps (6) and (4) and the etching step of the polycrystalline silicon 23 (5), the polycrystalline silicon 23 formed on the oxide film 25a is removed and the silicon substrate is removed. 1. The single crystal silicon 21 grown from above covers the oxide film 25a,
By growing the epitaxial layer to have a desired thickness, the single crystal silicon 21 having a desired impurity concentration is formed on the oxide film 25a as shown in FIG.

【0018】(7)酸化膜25a上以外の部分に形成さ
れた単結晶シリコン21をエッチングにより除去する。
このとき、前記酸化膜25aの外縁が僅かに露出するよ
うに、単結晶シリコン21をパターニングすることが望
ましい。
(7) The single crystal silicon 21 formed on a portion other than the oxide film 25a is removed by etching.
At this time, it is desirable to pattern the single crystal silicon 21 so that the outer edge of the oxide film 25a is slightly exposed.

【0019】(8)酸化膜25a上に単結晶シリコン2
1が形成された状態で熱酸化を行うことにより、エピタ
キシャル成長工程等における加工歪みを除去するととも
に、シリコン基板1の表裏面と単結晶シリコン21の表
面に酸化膜を形成し、絶縁膜(酸化膜25c)で覆われ
た単結晶シリコン21をピエゾ抵抗素子3a,3b,3
c,3dとする。
(8) Single crystal silicon 2 is formed on the oxide film 25a.
By performing thermal oxidation in the state in which 1 is formed, the processing strain in the epitaxial growth process and the like is removed, and an oxide film is formed on the front and back surfaces of the silicon substrate 1 and the surface of the single crystal silicon 21. 25c) the single crystal silicon 21 covered with the piezoresistive elements 3a, 3b, 3
c and 3d.

【0020】(9)乃至(12)は、薄肉の起歪部9の
製造方法や、前記ピエゾ抵抗素子3a,3b,3c,3
dと、前記電極パッド7a,7b,7c,7dとを電気
的に接続するためのコンタクトホール11の製造方法の
一例を示したものであるが、公知の技術であり、各種製
造方法が適用できることから、その説明を省略する。
(9) to (12) are the manufacturing method of the thin strain element 9 and the piezoresistive elements 3a, 3b, 3c, 3
1 shows an example of a method for manufacturing the contact hole 11 for electrically connecting the electrode pad 7a, 7b, 7c, 7d to the electrode pad 7a, 7b, 7c, 7d, but it is a known technique and various manufacturing methods can be applied. Therefore, the description is omitted.

【0021】このように、本発明の半導体センサにあっ
ては、所望の結晶方位、所望の不純物濃度でエピタキシ
ャル成長させた単結晶シリコンを、所望の形状に形成し
た上で絶縁膜(ここでは、酸化膜)で覆い、この単結晶
シリコンをピエゾ抵抗素子としたことから、他のピエゾ
抵抗素子と空間的に独立しているとともに、シリコン基
板を含めて電気的にも絶縁されていることから、汚染な
どの影響によるピエゾ抵抗素子表面からの漏れ電流を抑
制することができるとともに、PN接合を有していない
ことから、120℃以上の高温環境下にあっても、漏れ
電流を抑制することができる。
As described above, in the semiconductor sensor of the present invention, single crystal silicon epitaxially grown with a desired crystal orientation and a desired impurity concentration is formed into a desired shape and then an insulating film (oxidized here) is formed. Since it is covered with a film) and this single crystal silicon is used as a piezoresistive element, it is spatially independent of other piezoresistive elements and is electrically insulated including the silicon substrate. It is possible to suppress the leakage current from the surface of the piezoresistive element due to the influence of, for example, and since it does not have a PN junction, it is possible to suppress the leakage current even in a high temperature environment of 120 ° C. or higher. .

【0022】また、エピタキシャル成長により単結晶と
して成長しているため、ピエゾ抵抗素子の結晶性が良好
であるとともに、所望の不純物濃度となるように、所定
量の不純物をドープしたエピタキシャル層を成長させて
いることから、ピエゾ抵抗素子の断面深さ方向に対して
も、不純物濃度を適切に制御することができるため、応
力が最も高くなる部分では、最適なピエゾ抵抗効果が得
られるように構成し、リード部等と電気的に接続する部
分(コンタクトホール)では、接触抵抗が最も少なくな
るように構成するなど、諸々の特性に応じてピエゾ抵抗
素子の深さ方向に対する不純物濃度を容易に調整するこ
とができる。
Further, since it is grown as a single crystal by epitaxial growth, the crystallinity of the piezoresistive element is good, and an epitaxial layer doped with a predetermined amount of impurities is grown so as to have a desired impurity concentration. Therefore, since the impurity concentration can be appropriately controlled even in the cross-sectional depth direction of the piezoresistive element, it is configured so that the optimum piezoresistive effect can be obtained at the portion where the stress is highest, It is possible to easily adjust the impurity concentration in the depth direction of the piezoresistive element according to various characteristics, such as configuring the contact resistance at the part that is electrically connected to the lead part (contact hole) to be the smallest. You can

【0023】なお、図1乃至図6に示した半導体センサ
は、専ら気体や液体等の圧力を検出する圧力センサの構
造を例に説明しているが、シリコン基板に形成した起歪
部にピエゾ抵抗素子を配置した、ピエゾ抵抗効果を利用
する半導体センサであれば、加速度センサ、傾斜計等、
様々な半導体センサに適用できることは勿論のこと、シ
リコン基板の結晶方位、ピエゾ抵抗素子の形状(パター
ン)、起歪部の形状等、これらに限定されるものでない
ことは言うまでもない。
The semiconductor sensor shown in FIGS. 1 to 6 has been described by taking as an example the structure of a pressure sensor that exclusively detects the pressure of gas or liquid. However, the strain sensor formed on the silicon substrate has piezoelectric elements. If it is a semiconductor sensor that uses a piezoresistive effect and has a resistive element, an acceleration sensor, inclinometer, etc.
Needless to say, the present invention is not limited to various semiconductor sensors, but is not limited to the crystal orientation of the silicon substrate, the shape (pattern) of the piezoresistive element, the shape of the strain generating portion, and the like.

【0024】また、単結晶シリコンをパターニングした
後に、シリコン基板及びピエゾ抵抗素子の表面に熱酸化
による酸化膜を形成し、かつ、その上に窒化膜を形成し
た例を示しているが、熱酸化による酸化膜を形成せず
に、直接他の絶縁膜を形成することもできる。
In addition, an example is shown in which, after patterning single crystal silicon, an oxide film by thermal oxidation is formed on the surfaces of the silicon substrate and the piezoresistive element, and a nitride film is formed thereon. It is also possible to directly form another insulating film without forming an oxide film by the above method.

【0025】[0025]

【発明の効果】以上、詳細に説明したように本発明にあ
っては次に列挙する効果を得ることができる。
As described above in detail, the following effects can be obtained in the present invention.

【0026】(1)シリコン基板に形成した起歪部にピ
エゾ抵抗素子を配置した半導体センサにおいて、シリコ
ン基板上に酸化膜を形成し、この酸化膜をピエゾ抵抗素
子を形成する部分を残して除去した後、所望の不純物濃
度のn型あるいはp型のエピタキシャル層を成長させる
ことにより、前記酸化膜上以外の部分には単結晶シリコ
ンを、前記酸化膜上には多結晶シリコンを各々成長さ
せ、この酸化膜上に形成された多結晶シリコンを除去し
た状態で、酸化膜上以外の部分から成長した単結晶シリ
コンが前記酸化膜上を覆い所望の厚さになるまでエピタ
キシャル層を成長させることにより、前記酸化膜上に所
望の不純物濃度の単結晶シリコンを形成し、酸化膜上以
外の部分に成長した単結晶シリコンを除去した後、前記
酸化膜上に形成された単結晶シリコンを絶縁膜で覆うこ
とにより、この単結晶シリコンをピエゾ抵抗素子とする
ことにより半導体センサを構成しているため、120℃
以上の高温環境下にあっても、漏れ電流がほとんど発生
することがなく、ピエゾ抵抗素子の深さ方向に対する不
純物濃度の調整が容易で、高感度な半導体センサを得る
ことができる。
(1) In a semiconductor sensor in which a piezoresistive element is arranged in a strain generating portion formed on a silicon substrate, an oxide film is formed on the silicon substrate, and the oxide film is removed except for the portion where the piezoresistive element is formed. After that, an n-type or p-type epitaxial layer having a desired impurity concentration is grown to grow single crystal silicon on a portion other than the oxide film and polycrystalline silicon on the oxide film. By removing the polycrystalline silicon formed on the oxide film, the epitaxial layer is grown until the single crystal silicon grown from a portion other than the oxide film covers the oxide film to a desired thickness. Formed on the oxide film after forming single crystal silicon having a desired impurity concentration on the oxide film and removing the single crystal silicon grown on a portion other than the oxide film. By covering the single crystal silicon with the insulating film, which constitutes the semiconductor sensor by the single-crystal silicon piezoresistive element, 120 ° C.
Even under the above high temperature environment, almost no leakage current is generated, the impurity concentration in the depth direction of the piezoresistive element can be easily adjusted, and a highly sensitive semiconductor sensor can be obtained.

【0027】(2)シリコン基板に形成した起歪部にピ
エゾ抵抗素子を配置した半導体センサの製造方法におい
て、シリコン基板上に酸化膜を形成する工程と、この酸
化膜をピエゾ抵抗素子を形成する部分を残して除去する
工程と、所望の不純物濃度のn型あるいはp型のエピタ
キシャル層を成長させ、前記酸化膜上に成長した多結晶
シリコンを除去した状態で、前記酸化膜上を前記シリコ
ン基板上から成長した単結晶シリコンで覆い、該酸化膜
上に所望の厚さの単結晶シリコンを成長させる工程と、
前記酸化膜上以外の部分に成長した単結晶シリコンを除
去する工程と、前記酸化膜上に形成された前記単結晶シ
リコンを絶縁膜で覆う工程とを備えることにより、
(1)の効果を有する半導体センサの製造方法を得るこ
とができる。
(2) In a method of manufacturing a semiconductor sensor in which a piezoresistive element is arranged in a strained portion formed on a silicon substrate, a step of forming an oxide film on the silicon substrate and a piezoresistive element formed from this oxide film. A step of removing the remaining portion, and a step of growing an n-type or p-type epitaxial layer having a desired impurity concentration and removing the polycrystalline silicon grown on the oxide film, the oxide film is placed on the silicon substrate. Covering with single crystal silicon grown from above and growing single crystal silicon of a desired thickness on the oxide film;
By including a step of removing the single crystal silicon grown on a portion other than the oxide film, and a step of covering the single crystal silicon formed on the oxide film with an insulating film,
A method of manufacturing a semiconductor sensor having the effect (1) can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態の半導体センサの平
面図。
FIG. 1 is a plan view of a semiconductor sensor according to a first embodiment of the present invention.

【図2】図1のII−II方向から見た断面図。FIG. 2 is a cross-sectional view seen from a II-II direction in FIG.

【図3】本発明の第1の実施の形態の半導体センサの製
造工程を示す図。
FIG. 3 is a diagram showing a manufacturing process of the semiconductor sensor according to the first embodiment of the invention.

【図4】図3のA部の部分拡大図。FIG. 4 is an enlarged view of part A of FIG.

【図5】図3のB部の部分拡大図。5 is a partially enlarged view of portion B of FIG.

【図6】図3のC部の部分拡大図。FIG. 6 is a partially enlarged view of a C portion of FIG.

【符号の説明】[Explanation of symbols]

1:シリコン基板、3a,3b,3c,3d:ピエゾ抵
抗素子、5a,5b,5c,5d,5e,5f,5g,
5h:リード部、7a,7b,7c,7d:電極パッ
ド、9:起歪部、 11:コンタクトホー
ル、21:単結晶シリコン、 23:多結晶シリコ
ン、25a,25b,25c,25d:酸化膜、27
a,27b:窒化膜。
1: Silicon substrate, 3a, 3b, 3c, 3d: Piezoresistive element, 5a, 5b, 5c, 5d, 5e, 5f, 5g,
5h: Lead part, 7a, 7b, 7c, 7d: Electrode pad, 9: Strain element, 11: Contact hole, 21: Single crystal silicon, 23: Polycrystalline silicon, 25a, 25b, 25c, 25d: Oxide film, 27
a, 27b: nitride film.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板に形成した起歪部にピエゾ
抵抗素子を配置した半導体センサにおいて、 シリコン基板上に酸化膜を形成し、この酸化膜をピエゾ
抵抗素子を形成する部分を残して除去した後、所望の不
純物濃度のn型あるいはp型のエピタキシャル層を成長
させることにより、前記酸化膜上以外の部分には単結晶
シリコンを、前記酸化膜上には多結晶シリコンを各々成
長させ、この酸化膜上に形成された多結晶シリコンを除
去した状態で、酸化膜上以外の部分から成長した単結晶
シリコンが前記酸化膜上を覆い所望の厚さになるまでエ
ピタキシャル層を成長させることにより、前記酸化膜上
に所望の不純物濃度の単結晶シリコンを形成し、酸化膜
上以外の部分に成長した単結晶シリコンを除去した後、
前記酸化膜上に形成された単結晶シリコンを絶縁膜で覆
うことにより、この単結晶シリコンをピエゾ抵抗素子と
したことを特徴とする半導体センサ。
1. In a semiconductor sensor in which a piezoresistive element is arranged in a strained portion formed on a silicon substrate, an oxide film is formed on the silicon substrate, and the oxide film is removed except for a portion where the piezoresistive element is formed. After that, by growing an n-type or p-type epitaxial layer having a desired impurity concentration, single crystal silicon is grown on a portion other than the oxide film, and polycrystalline silicon is grown on the oxide film. By removing the polycrystalline silicon formed on the oxide film, by growing the epitaxial layer until the single crystal silicon grown from a portion other than the oxide film covers the oxide film to a desired thickness, After forming single crystal silicon having a desired impurity concentration on the oxide film and removing the single crystal silicon grown on a portion other than the oxide film,
A semiconductor sensor, wherein the single crystal silicon formed on the oxide film is covered with an insulating film to form the single crystal silicon as a piezoresistive element.
【請求項2】 シリコン基板に形成した起歪部にピエゾ
抵抗素子を配置した半導体センサの製造方法において、 シリコン基板上に酸化膜を形成する工程と、この酸化膜
をピエゾ抵抗素子を形成する部分を残して除去する工程
と、所望の不純物濃度のn型あるいはp型のエピタキシ
ャル層を成長させ、前記酸化膜上に成長した多結晶シリ
コンを除去した状態で、前記酸化膜上を前記シリコン基
板上から成長した単結晶シリコンで覆い、該酸化膜上に
所望の厚さの単結晶シリコンを成長させる工程と、前記
酸化膜上以外の部分に成長した単結晶シリコンを除去す
る工程と、前記酸化膜上に形成された前記単結晶シリコ
ンを絶縁膜で覆う工程とを備えることを特徴とする半導
体センサの製造方法。
2. A method of manufacturing a semiconductor sensor in which a piezoresistive element is arranged in a strain-generating part formed on a silicon substrate, a step of forming an oxide film on the silicon substrate, and a portion where the oxide film forms a piezoresistive element. And removing the polycrystalline silicon grown on the oxide film by growing an n-type or p-type epitaxial layer having a desired impurity concentration and removing the polycrystalline silicon grown on the oxide film from the silicon substrate. Covering the oxide film with single crystal silicon having a desired thickness, removing the single crystal silicon grown on a portion other than the oxide film, and forming the oxide film And a step of covering the single crystal silicon formed above with an insulating film.
JP2001292738A 2001-09-26 2001-09-26 Semiconductor sensor and manufacturing method thereof Expired - Fee Related JP4845308B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006145462A (en) 2004-11-24 2006-06-08 Ngk Spark Plug Co Ltd Pressure sensor
JP2009036630A (en) * 2007-08-01 2009-02-19 Mitsumi Electric Co Ltd Semiconductor pressure sensor and its manufacturing method
WO2009072704A1 (en) * 2007-12-05 2009-06-11 Electronics And Telecommunications Research Institute Micro piezoresistive pressure sensor and manufacturing method thereof
JP2009300197A (en) * 2008-06-12 2009-12-24 Alps Electric Co Ltd Semiconductor pressure sensor
JP2010071678A (en) * 2008-09-16 2010-04-02 Dainippon Printing Co Ltd Acceleration sensor and method of manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0797645B2 (en) * 1989-08-11 1995-10-18 日産自動車株式会社 Piezoresistive element
JPH08293616A (en) * 1995-04-24 1996-11-05 Nagano Keiki Seisakusho Ltd Semiconductor pressure sensor
JPH1022511A (en) * 1996-06-28 1998-01-23 Matsushita Electric Works Ltd Semiconductor pressure sensor and its manufacture
JPH10267777A (en) * 1997-03-24 1998-10-09 Unisia Jecs Corp Device for detecting subject to be measured and its manufacture
JPH11211736A (en) * 1997-11-20 1999-08-06 Seiko Instruments Inc Self-detection-type spm probe and spm device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0797645B2 (en) * 1989-08-11 1995-10-18 日産自動車株式会社 Piezoresistive element
JPH08293616A (en) * 1995-04-24 1996-11-05 Nagano Keiki Seisakusho Ltd Semiconductor pressure sensor
JPH1022511A (en) * 1996-06-28 1998-01-23 Matsushita Electric Works Ltd Semiconductor pressure sensor and its manufacture
JPH10267777A (en) * 1997-03-24 1998-10-09 Unisia Jecs Corp Device for detecting subject to be measured and its manufacture
JPH11211736A (en) * 1997-11-20 1999-08-06 Seiko Instruments Inc Self-detection-type spm probe and spm device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006145462A (en) 2004-11-24 2006-06-08 Ngk Spark Plug Co Ltd Pressure sensor
JP2009036630A (en) * 2007-08-01 2009-02-19 Mitsumi Electric Co Ltd Semiconductor pressure sensor and its manufacturing method
WO2009072704A1 (en) * 2007-12-05 2009-06-11 Electronics And Telecommunications Research Institute Micro piezoresistive pressure sensor and manufacturing method thereof
US8261617B2 (en) 2007-12-05 2012-09-11 Electronics And Telecomunications Research Institute Micro piezoresistive pressure sensor and manufacturing method thereof
JP2009300197A (en) * 2008-06-12 2009-12-24 Alps Electric Co Ltd Semiconductor pressure sensor
JP2010071678A (en) * 2008-09-16 2010-04-02 Dainippon Printing Co Ltd Acceleration sensor and method of manufacturing the same

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