JPS60260162A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60260162A JPS60260162A JP11685484A JP11685484A JPS60260162A JP S60260162 A JPS60260162 A JP S60260162A JP 11685484 A JP11685484 A JP 11685484A JP 11685484 A JP11685484 A JP 11685484A JP S60260162 A JPS60260162 A JP S60260162A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- diffusion
- impurity layer
- concentration impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 6
- 238000011109 contamination Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000002161 passivation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、半導体装置の製造方法に係り、特に、ツェナ
ダイオードを備えた半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a Zener diode.
（ロ）従来技術
通常、バイポーラ型の半導体装置に形成されるツェナダ
イオードは、ブレーナ型トランジスタのエミッタおよび
ベースを利用して製造されている。(B) Prior Art Usually, a Zener diode formed in a bipolar type semiconductor device is manufactured using the emitter and base of a Brainer type transistor.
そして例えば、前記ツェナダイオードは、ペース領域よ
りもエミッタ領域が小さく形成される構造上、Ｐ−Ｎ接
合面の端部が基板界面に露出してしまう。即ち、この部
分でもってツェナ電圧特性が定められる。For example, because the Zener diode has a structure in which the emitter region is formed smaller than the space region, the end of the PN junction surface is exposed at the substrate interface. That is, this portion determines the Zener voltage characteristics.
しかして、前記Ｐ−Ｎ接合面の端部が外部からの汚染等
の影響を受けやすいので、パシベーション膜を形成して
いる。このパシベーション膜には、ガラスバシヘーショ
ンおよび窒化膜パシベーションの二種類がある。However, since the end portion of the P-N junction surface is easily affected by external contamination, a passivation film is formed. There are two types of passivation films: glass passivation and nitride film passivation.
しかしながら、前記各パシベーション膜を形成しても外
部からの汚染等の影響を完全に防止することができない
事。またパシベーションを形成す−る事により、前記ツ
ェナダイオードのツェナ電圧がドリフトするという問題
を生じる。従って、製品としての信頼性の低下を招くこ
ととなる。However, even if each of the passivation films is formed, it is not possible to completely prevent the effects of external contamination and the like. Furthermore, the formation of passivation causes the problem that the Zener voltage of the Zener diode drifts. Therefore, the reliability of the product will be lowered.
さらに、従来のツェナダイオードのツェナ電圧値の設定
は、エミツタ層の拡散深さに依存されている。Furthermore, setting the Zener voltage value of a conventional Zener diode is dependent on the diffusion depth of the emitter layer.
即ち、前記エミツタ層の拡散深さは、ベース領域の所定
位置の高濃度不純物の拡散時間および拡散温度を適宜に
可変することにより行われている。That is, the diffusion depth of the emitter layer is determined by appropriately varying the diffusion time and diffusion temperature of the high concentration impurity at a predetermined position in the base region.
しかしながら、上述のような方法では、拡散深さが浅く
なるように制御するのが困難である。However, with the method described above, it is difficult to control the diffusion depth to be shallow.
そのため、低いツェナ電圧値のツェナダイオードを形成
するのは技術的に困難である。Therefore, it is technically difficult to form a Zener diode with a low Zener voltage value.
また、前記エミツタ層の拡散深さをコントロールする場
合、拡散炉の拡散温度および拡散時間等をそれぞれ可変
してやる必要があり、非當にわずられしいという問題も
ある。Furthermore, when controlling the diffusion depth of the emitter layer, it is necessary to vary the diffusion temperature and diffusion time of the diffusion furnace, which is extremely cumbersome.
（ハ）目的
本発明は、ツェナ電圧のドリフトをなくして、製品とし
て信頼性の向上を図り得るツェナダイオードを備えた半
導体装置の製造方法を提供することを目的としている。(C) Objective The present invention aims to provide a method for manufacturing a semiconductor device equipped with a Zener diode, which can eliminate Zener voltage drift and improve the reliability of the product.
さらに、所望のツェナ電圧値を容易に得ることのできる
ツェナダイオードを備えた半導体装置の製造方法をも提
供することを目的としている。A further object of the present invention is to provide a method for manufacturing a semiconductor device equipped with a Zener diode that can easily obtain a desired Zener voltage value.
（ニ）構成
本発明に係る半導体装置の製造方法は、ツェナダイオー
ドを備えた半導体装置の製造方法であって、所定箇所に
埋め込み拡散層が形成された基板上にエピタキシャル層
を成長させる工程と、基板に形成する各素子を絶縁分離
する分離拡散層と、これの中央部にダイオード領域を形
成する第１の高濃度不純物層とを前記埋め込み拡散層に
達するまで同時に拡散する工程と、
前記第１の高濃度不純物層の表面に、これと逆極性の不
純物を含む所望の膜厚のポリシリコンを形成する工程と
、
前記ポリシリコンから不純物を拡散させて前記第１の高
濃度不純物層よりも大きい面積で、かつ、所望の拡散深
さである第２の高濃度不純物層を形成する工程とを具備
したことを特徴とする。(D) Structure A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a Zener diode, which includes the step of growing an epitaxial layer on a substrate on which a buried diffusion layer is formed at a predetermined location; simultaneously diffusing an isolation diffusion layer for insulating and isolating each element formed on the substrate and a first high concentration impurity layer for forming a diode region in the center thereof until reaching the buried diffusion layer; forming polysilicon of a desired thickness containing impurities of opposite polarity on the surface of the first high concentration impurity layer; and diffusing impurities from the polysilicon to form a layer larger than the first high concentration impurity layer. The method is characterized by comprising a step of forming a second high concentration impurity layer having a desired area and a desired diffusion depth.
（ボ）実施例
第１図は本発明に係る製造方法で形成された半導体装置
の一実施例を略示した断面図である。(B) Embodiment FIG. 1 is a sectional view schematically showing an embodiment of a semiconductor device formed by the manufacturing method according to the present invention.
１はＰ型のシリコン基板からなる半導体基板、２はＰ中
型の埋め込み拡散層、３はＮ型のエピタキシャル層、４
ａはＰ中型の分離拡散層であり、リング状に拡散され前
記埋め込み拡散Ｎ２と接続している。４ｂはＰ中型の第
１の高濃度不純物層であり、前記埋め込み拡散層２に達
するまで拡散されている。1 is a semiconductor substrate made of a P-type silicon substrate, 2 is a P medium-sized buried diffusion layer, 3 is an N-type epitaxial layer, 4
A is a P medium-sized separation diffusion layer, which is diffused in a ring shape and connected to the buried diffusion N2. 4b is a first high concentration impurity layer of P medium type, which is diffused until it reaches the buried diffusion layer 2.
５はＮ十型の不純物を含むポリシリコンであり、この膜
厚を可変することにより第２の高濃度不純物層６の拡散
深さを設定することができる。Reference numeral 5 denotes polysilicon containing N0 type impurities, and by varying the film thickness, the diffusion depth of the second high concentration impurity layer 6 can be set.
前記第２の高濃度不純物層６は、前記ポリシリコンから
拡散されることにより、前記第１の高濃度不純物Ｆｆｔ
４ｂよりも大きい面積に形成される。即ちＰ−Ｎ接合面
が基板界面に露出しない構造にされている。The second high concentration impurity layer 6 is diffused from the polysilicon to form the first high concentration impurity layer Fft.
4b is formed to have a larger area. That is, the structure is such that the PN junction surface is not exposed at the substrate interface.
７は前記分離拡散Ｆｉ４ａとポリシリコン５とを除くエ
ピタキシャルＮ３の上部に形成されたシリコン酸化膜で
ある。7 is a silicon oxide film formed on the epitaxial layer N3 excluding the isolation diffusion Fi4a and polysilicon 5.
８は前記ポリシリコン５を熱処理した後、形成されたシ
リコン酸化膜である。8 is a silicon oxide film formed after the polysilicon 5 is heat-treated.
９ａ、９ｂはアルミニウム等からなる電極であり、前記
分離拡散Ｎ４ａとポリシリコン５との表面に蒸着形成さ
れている。Reference numerals 9a and 9b are electrodes made of aluminum or the like, which are deposited on the surfaces of the separated and diffused N4a and the polysilicon 5.
１０は例えば窒化膜からなるパシベーション膜である。10 is a passivation film made of, for example, a nitride film.
次に、本発明に係る半導体装置の製造方法を第２図に従
って以下説明する。Next, a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIG.
第２図は半導体装置の製造方法の一実施例を略示した説
明図である。FIG. 2 is an explanatory diagram schematically showing one embodiment of a method for manufacturing a semiconductor device.
ｔａｌ Ｐ型の半導体基板１の表面にシリコン酸化膜１
１を形成して、埋め込み拡散層２を形成する部分の前記
シリコン酸化膜１１をエツチングする。前記シリコン酸
化膜１１をマスクとしてＰ十型不純物を熱拡散して埋め
込み拡散層２を拡散する。A silicon oxide film 1 is formed on the surface of a P-type semiconductor substrate 1.
1 is formed, and a portion of the silicon oxide film 11 where the buried diffusion layer 2 is to be formed is etched. The buried diffusion layer 2 is diffused by thermally diffusing the P0 type impurity using the silicon oxide film 11 as a mask.
（ｂｌ 前記シリコン酸化膜１１を除去して、基板１の
表面にＮ型のエピタキシャル層３を成長させる。(bl) The silicon oxide film 11 is removed and an N-type epitaxial layer 3 is grown on the surface of the substrate 1.
（Ｃ） 前記エピタキシャル層３の表面に再度シリコン
酸化膜１２を形成して、分離拡散Ｎ４ａ、第１の高濃度
不純物層４ｂを形成する部分の前記シリコン酸化膜１２
をエツチングした後、この表面にＰ小型不純物拡散源１
３を付着させる。(C) A silicon oxide film 12 is formed again on the surface of the epitaxial layer 3 to form a portion of the silicon oxide film 12 where the isolation diffusion N4a and the first high concentration impurity layer 4b are to be formed.
After etching, a P small impurity diffusion source 1 is placed on this surface.
Attach 3.
（ｄｌ 前記Ｐ十型不純物拡散源１３を熱処理すること
により、分離拡散層４ａおよび第１の高濃度不純物層４
ｂと前記埋め込み拡散層２とを接続させる。(dl By heat-treating the P-type impurity diffusion source 13, the separation diffusion layer 4a and the first high concentration impurity layer 4 are
b and the buried diffusion layer 2 are connected.
（ｅ） 前記シリコン酸化膜１２とＰ小型不純物拡散源
１３とを除去して、再度シリコン酸化膜７を形成する。(e) The silicon oxide film 12 and the P small impurity diffusion source 13 are removed, and the silicon oxide film 7 is formed again.
次に、ポリシリコン５を形成する部分のシリコン酸化膜
７をエツチングして、Ｎ生型不純物を含むポリシリコン
５を所望の膜厚で形成しバターニングする。Next, the silicon oxide film 7 in the portion where the polysilicon 5 is to be formed is etched to form a polysilicon 5 containing N-type impurities to a desired thickness and patterned.
（ｆ） 所定の拡散温度、拡散時間でもって熱処理する
ことにより、前記ポリシリコン５から前記第１の高濃度
不純物層４ｂよりも大きい面積の第２の高濃度不純物Ｎ
６を拡散させる。このとき前記ポリシリコン５の表面に
はシリコン酸化膜８が形成される。(f) A second high concentration impurity N having a larger area than the first high concentration impurity layer 4b is formed from the polysilicon 5 by heat treatment at a predetermined diffusion temperature and diffusion time.
Diffuse 6. At this time, a silicon oxide film 8 is formed on the surface of the polysilicon 5.
ｔｇｌ 前記ポリシリコン５の表面のシリコン酸化膜８
と、前記分離拡散Ｆｔ４ａの表面のシリコン酸化膜７と
をエツチングすることにより、各コンタクトホールを形
成する。tgl Silicon oxide film 8 on the surface of the polysilicon 5
Each contact hole is formed by etching the silicon oxide film 7 on the surface of the isolation diffusion Ft4a.
（ｈｌ 半導体基板の表面にアルミニウム等を蒸着しバ
ターニングして各電極９ａ、９ｂを形成する。次に窒化
膜等のパシベーション膜１０を形成する。(hl) Aluminum or the like is deposited on the surface of the semiconductor substrate and patterned to form each electrode 9a, 9b. Next, a passivation film 10 such as a nitride film is formed.
尚、上述した実施例で電極９ａは、分離拡散層４ａの表
面に形成されているが、本発明はこれに限定されず、例
えば基板１の裏面に形成するも好ましい。Although the electrode 9a is formed on the surface of the separation diffusion layer 4a in the embodiment described above, the present invention is not limited thereto, and it is also preferable to form it on the back surface of the substrate 1, for example.
また、上述した実施例の半導体装置によるツェナ電圧値
の特性を第３図に示す。Further, FIG. 3 shows the characteristics of the Zener voltage value of the semiconductor device of the above-described embodiment.
（へ）効果
本発明は、第１の高濃度不純物層の表面にこれよりも大
きい面積の第２の高濃度不純物層を形成しているので、
Ｐ−Ｎ接合面が基板界面に露出しない。(F) Effect The present invention forms a second high concentration impurity layer with a larger area on the surface of the first high concentration impurity layer.
The P-N junction surface is not exposed at the substrate interface.
従って、外部からの汚染等の影響を受けないので、ツェ
ナダイオードのツェナ電圧のドリフトを防止することが
できる結果、製品として信頼性を向上することができる
。Therefore, since it is not affected by external contamination, it is possible to prevent the Zener voltage of the Zener diode from drifting, and as a result, the reliability of the product can be improved.
また、ポリシリコンの膜厚を可変して第２の高濃度不純
物層の拡散深さを定めているので、ツェナダイオードの
ツェナ電圧値を任意に設定することができる。Further, since the diffusion depth of the second high concentration impurity layer is determined by varying the thickness of the polysilicon film, the Zener voltage value of the Zener diode can be set arbitrarily.
さらに、ポリシリコンの膜厚がそれぞれ異なるものであ
っても、その拡散深さは前記ポリシリコンでもって定め
られるので、各々同一の拡散炉で拡散することができる
。即ち、拡散炉の拡散温度を可変してやる必要がないの
で、製造作業の能率第１図は本発明に係る製造方法で形
成された半導体装置の一実施例を略示した断面図、第２
図は半導体装置の製造方法の一実施例を略示した説明図
、第３図は本発明の製造方法で形成されたツェナダイオ
ードを備えた半導体装置のツェナ電圧値の特性図である
。Furthermore, even if the polysilicon film thicknesses are different, the diffusion depth is determined by the polysilicon, so each can be diffused in the same diffusion furnace. That is, since there is no need to vary the diffusion temperature of the diffusion furnace, the efficiency of the manufacturing operation is improved.Figure 1 is a cross-sectional view schematically showing one embodiment of a semiconductor device formed by the manufacturing method according to the present invention, and Figure 2
The figure is an explanatory diagram schematically showing one embodiment of the method for manufacturing a semiconductor device, and FIG. 3 is a characteristic diagram of the Zener voltage value of a semiconductor device equipped with a Zener diode formed by the manufacturing method of the present invention.
ｌ ・・・半導体基板、２ ・・・埋め込み拡散層、３
・・・エピタキシャル層、４ａ・・・分離拡散層、４
ｂ・・・第１の高濃度不純物層、５ ・・・ポリシリコ
ン、６ ・・・第２の高濃度不純物層。l...Semiconductor substrate, 2...Buried diffusion layer, 3
...Epitaxial layer, 4a...Isolation diffusion layer, 4
b: first high concentration impurity layer, 5: polysilicon, 6: second high concentration impurity layer.
特許出願人 ローム株式会社 代理人 弁理士 大 西 孝 治 第１図 （ａ） （Ｃ） 第２図（ぞの１） 第２図Ｃぞ ２８８Patent applicant: ROHM Co., Ltd. Agent: Patent Attorney Takaharu Onishi Figure 1 (a) (C) Figure 2 (Zone 1) Figure 2 C 288
Claims (1)
において、 所定箇所に埋め込み拡散層が形成された基板上にエピタ
キシャル層を成長させる工程と、基板に形成する各素子
を絶縁分離する分離拡散層と、これの中央部にダイオー
ド領域を形成する第１の高濃度不純物層とを前記埋め込
み拡散層に達するまで同時に拡散する工程と、 前記第１の高濃度不純物層の表面に、これと逆極性の不
純物を含む所望の膜厚のポリシリコンを形成する工程と
、 前記ポリシリコンから不純物を拡散させて前記第１の高
濃度不純物層よりも大きい面積で、かつ、所望の拡散深
さである第２の高濃度不純物層を形成する工程とを具備
したことを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device equipped with a Zener diode includes a step of growing an epitaxial layer on a substrate in which a buried diffusion layer is formed at a predetermined location, and an isolation diffusion layer for insulating and separating each element formed on the substrate. , simultaneously diffusing a first high-concentration impurity layer forming a diode region in the center of the first high-concentration impurity layer until it reaches the buried diffusion layer; forming a polysilicon layer containing impurities and having a desired thickness; and diffusing impurities from the polysilicon to form a second layer having a larger area than the first high concentration impurity layer and a desired diffusion depth. 1. A method of manufacturing a semiconductor device, comprising: forming a highly concentrated impurity layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59116854A JPH0691267B2 (en) | 1984-06-06 | 1984-06-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59116854A JPH0691267B2 (en) | 1984-06-06 | 1984-06-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60260162A true JPS60260162A (en) | 1985-12-23 |
| JPH0691267B2 JPH0691267B2 (en) | 1994-11-14 |
Family
ID=14697266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59116854A Expired - Lifetime JPH0691267B2 (en) | 1984-06-06 | 1984-06-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691267B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314399A2 (en) * | 1987-10-30 | 1989-05-03 | Precision Monolithics Inc. | Buried zener diode and method of forming the same |
| US5241213A (en) * | 1991-07-30 | 1993-08-31 | Harris Corporation | Buried zener diode having auxiliary zener junction access path |
| CN105556679A (en) * | 2013-10-01 | 2016-05-04 | 威世通用半导体公司 | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243383A (en) * | 1975-10-02 | 1977-04-05 | Nec Corp | Process for productiong of constant voltage diode |
| JPS55134983A (en) * | 1979-04-09 | 1980-10-21 | Ibm | Surface breakdown zener diode |
| JPS5737884A (en) * | 1980-08-19 | 1982-03-02 | Nec Corp | Semiconductor device |
| JPS57207380A (en) * | 1981-06-16 | 1982-12-20 | Rohm Co Ltd | Zener diode |
-
1984
- 1984-06-06 JP JP59116854A patent/JPH0691267B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243383A (en) * | 1975-10-02 | 1977-04-05 | Nec Corp | Process for productiong of constant voltage diode |
| JPS55134983A (en) * | 1979-04-09 | 1980-10-21 | Ibm | Surface breakdown zener diode |
| JPS5737884A (en) * | 1980-08-19 | 1982-03-02 | Nec Corp | Semiconductor device |
| JPS57207380A (en) * | 1981-06-16 | 1982-12-20 | Rohm Co Ltd | Zener diode |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314399A2 (en) * | 1987-10-30 | 1989-05-03 | Precision Monolithics Inc. | Buried zener diode and method of forming the same |
| US5241213A (en) * | 1991-07-30 | 1993-08-31 | Harris Corporation | Buried zener diode having auxiliary zener junction access path |
| CN105556679A (en) * | 2013-10-01 | 2016-05-04 | 威世通用半导体公司 | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| EP3053198A1 (en) * | 2013-10-01 | 2016-08-10 | Vishay General Semiconductor LLC | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| EP3053198A4 (en) * | 2013-10-01 | 2017-05-03 | Vishay General Semiconductor LLC | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
| US9966429B2 (en) | 2013-10-01 | 2018-05-08 | Vishay General Semiconductor Llc | Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0691267B2 (en) | 1994-11-14 |
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