JPS62209868A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62209868A JPS62209868A JP5216586A JP5216586A JPS62209868A JP S62209868 A JPS62209868 A JP S62209868A JP 5216586 A JP5216586 A JP 5216586A JP 5216586 A JP5216586 A JP 5216586A JP S62209868 A JPS62209868 A JP S62209868A
- Authority
- JP
- Japan
- Prior art keywords
- type
- semiconductor device
- buried
- breakdown voltage
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、ツェナダイオードを備えた半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device including a Zener diode.
〈従来の技術〉
通常、バイポーラ型の半導体基板に形成されるツェナダ
イオードは、ブレーナ型トランジスタのエミッタ領域と
一ベース領域とを利用している７このような領域を利用
した場合のツェナダイオードでは、ベース領域に比べて
エミッタ領域が小さいから、ＰＮ接合面の端部が基板界
面に露出している。<Prior Art> Usually, a Zener diode formed on a bipolar semiconductor substrate uses the emitter region and one base region of a Brainer transistor.7 In a Zener diode using such regions, Since the emitter region is smaller than the base region, the end of the PN junction surface is exposed to the substrate interface.
ところで、ツェナダイオードのブレークダウン電圧は、
基板表面からの深さに対応する不純物濃度で示す勾配で
決まる。ところが、ＰＮ接合面を前記のように基板表面
に露出させている場合は、電極との接触抵抗を小さくす
るためその不純物濃度を基板表面で最も大きくしている
から、そのブレークダウン電圧は、前記基板界面の状態
の影響を受けやすくなっている。そこで、従来は、この
影響を軽減するためにパシベーション膜を形成している
。By the way, the breakdown voltage of a Zener diode is
It is determined by the slope of the impurity concentration that corresponds to the depth from the substrate surface. However, when the PN junction surface is exposed on the substrate surface as described above, the impurity concentration is maximized at the substrate surface in order to reduce the contact resistance with the electrode, so the breakdown voltage is It is easily affected by the condition of the substrate interface. Therefore, conventionally, a passivation film is formed to reduce this influence.
〈発明が解決しようとする問題点〉
しかるに、このようなパシベーション膜を形成したとし
ても基板界面付近にはＮａなどの可動イオンが作用して
おり、ブレークダウン電圧に強く影響を与えることから
基板界面でブレークダウンさせることは非常に不安定で
あった。<Problems to be solved by the invention> However, even if such a passivation film is formed, mobile ions such as Na act near the substrate interface, which strongly affects the breakdown voltage. It was very unstable to break it down.
く目的〉
本発明は、基板界面から深いところにＰＮ接合面を形成
して、界面状態の影響を受けない安定したブレークダウ
ン電圧を有する半導体装置の製造方法を提供することを
目的としている。An object of the present invention is to provide a method for manufacturing a semiconductor device that forms a PN junction plane deep from the substrate interface and has a stable breakdown voltage that is not affected by the interface state.
く問題点を解決するための手段〉
そこで、本発明では、上部分離拡散層と下部分離拡散層
との間に、基板界面から所定深さを存して埋込分離領域
を形成し、この埋込分離領域の表面に、これと逆極性及
び同極性の高濃度不純物をそれぞれ拡散し、この高濃度
不純物の拡散領域のそれぞれに電極を設けて半導体装置
を製造することを特徴としている。Therefore, in the present invention, a buried isolation region is formed between the upper isolation diffusion layer and the lower isolation diffusion layer at a predetermined depth from the substrate interface. The semiconductor device is manufactured by diffusing high-concentration impurities of the opposite polarity and the same polarity into the surface of the isolation region, respectively, and providing electrodes in each of the high-concentration impurity diffusion regions.
〈作用〉
ツェナダイオードが動作したとき、ブレークダウン電圧
は基板界面から深いところのエピタキシャル層内で発生
する。<Operation> When the Zener diode operates, a breakdown voltage is generated within the epitaxial layer deep from the substrate interface.
〈実施例〉
第１図は、本発明の一実施例に係る半導体装置の製造方
法により製造された半導体装置の暗示断面図である。<Example> FIG. 1 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an example of the present invention.
ｌはツェナダイオードを備えた半導体装置であって、こ
の半導体装置１の表面である基板界面１ａより所定の深
さを有していて、Ｐ型のシリコン基板からなる下部分離
拡散層２と、Ｎ型のエピタキシャル層からなる上部分離
拡散層３との間に、Ｐ型で、高濃度不純物の埋込分離領
域が形成されている。そして、この埋込Ｐ＋分離領域の
表面には、これと逆極性すなわちＮの高濃度不純物と、
同極性すなわちＰの高濃度不純物とが拡散されている。1 is a semiconductor device equipped with a Zener diode, which has a predetermined depth from the substrate interface 1a which is the surface of the semiconductor device 1, and has a lower isolation diffusion layer 2 made of a P-type silicon substrate and an N A buried isolation region of high concentration impurity of P type is formed between the upper isolation diffusion layer 3 made of a type epitaxial layer. Then, on the surface of this buried P+ isolation region, there is an impurity of opposite polarity, that is, a high concentration of N.
Impurities of the same polarity, that is, high concentration of P, are diffused.
また、このＮ＋及びＰ＋拡散領域５ ａ、 ５ ｂのそ
れぞれには、電極６が設けられている。Further, an electrode 6 is provided in each of the N+ and P+ diffusion regions 5a, 5b.
以下、第２図（ａ）ないしくｅ）の製造工程図を参照し
て本発明の実施例に係る半導体装置の製造方法を説明す
る。Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained with reference to manufacturing process diagrams shown in FIGS. 2(a) to 2e).
（ａ） Ｐ型シリコン基板を用意する。(a) Prepare a P-type silicon substrate.
（ｂ） Ｐ型シリコン基板２表面にシリコン酸化膜７を
生成した後、窓開けをする。窓開は箇所からボロンを拡
散・熱処理をする。(b) After forming a silicon oxide film 7 on the surface of the P-type silicon substrate 2, a window is opened. For window openings, boron is diffused and heat treated from certain points.
（Ｃ）シリコン酸化膜７を除去して後、Ｎエピタキシャ
ル層３を成長させて、埋め込みＰ＋分離領域４を形成す
る。(C) After removing the silicon oxide film 7, an N epitaxial layer 3 is grown to form a buried P+ isolation region 4.
（ｄ）シリコン酸化膜８を生成し、所要箇所に窓開けを
してその窓開は箇所にボロンを拡散・熱処理して埋め込
みＰ＋分離領域４に至るＮ＋拡散領域５ａを形成する。(d) A silicon oxide film 8 is formed, windows are opened at required locations, and boron is diffused and heat treated at the openings to form N+ diffusion regions 5a that reach the buried P+ isolation regions 4.
（ｅ）所要箇所に窓開けをしてその窓開は箇所にボロン
を拡散・熱処理して埋め込みＰ＋分離領域に至るＰ＋拡
散領域５ｂを形成する。そして、Ｎ＋およびＰ＋拡散領
域５ ａ、 ５ ｂのそれぞれに電極６を取り付ける。(e) A window is opened at a required location, and boron is diffused and heat treated at the window opening to form a P+ diffusion region 5b reaching the buried P+ isolation region. Then, electrodes 6 are attached to each of the N+ and P+ diffusion regions 5a, 5b.
このようにして製造されたツェナダイオードでは、ＰＮ
接合面が基板界面から深いところのエピタキシャル層内
に形成されるからブレークダウン電圧がその界面状態の
影響を受けることかなくなり、安定したブレークダウン
電圧を得ることができる。In the Zener diode manufactured in this way, the PN
Since the bonding surface is formed in the epitaxial layer deep from the substrate interface, the breakdown voltage is not affected by the interface state, and a stable breakdown voltage can be obtained.
〈発明の効果〉
以上のように本発明製造方法によれば、埋込分離領域で
あるＰＮ接合面を基板界面から深い位置のエピタキシャ
ル層内に形成するから面状態の影響を受けない安定した
ブレークダウン電圧を得ることができる。<Effects of the Invention> As described above, according to the manufacturing method of the present invention, since the PN junction surface, which is a buried isolation region, is formed in the epitaxial layer at a deep position from the substrate interface, a stable break that is not affected by the surface condition can be achieved. You can get down voltage.
第１図は本発明製造方法により製造された半導体装置の
暗示断面図、第２図は、本発明製造方法の製造工程を暗
示した説明図である。
ｌ・・・半導体装置、
３・・・上分離拡散層、
４・・・埋込分離領域、
５ ａ、 ５ ｂ・・・拡散領域、
６・・・電極。FIG. 1 is a suggested cross-sectional view of a semiconductor device manufactured by the manufacturing method of the present invention, and FIG. 2 is an explanatory diagram suggesting the manufacturing steps of the manufacturing method of the present invention. 1...Semiconductor device, 3...Upper isolation diffusion layer, 4...Buried isolation region, 5a, 5b...Diffusion region, 6...Electrode.
Claims (1)
において、 上部分離拡散層と下部分離拡散層との間に、基板界面か
ら所定深さを存して埋込分離領域を形成し、この埋込分
離領域の表面に、これと逆極性及び同極性の高濃度不純
物をそれぞれ拡散し、この高濃度不純物の拡散領域のそ
れぞれに電極を形成することを特徴とする半導体装置の
製造方法。(1) In a method for manufacturing a semiconductor device including a Zener diode, a buried isolation region is formed between an upper isolation diffusion layer and a lower isolation diffusion layer at a predetermined depth from the substrate interface, and the buried isolation region is formed at a predetermined depth from the substrate interface. 1. A method of manufacturing a semiconductor device, which comprises diffusing high concentration impurities of opposite polarity and same polarity to the surface of a separation region, and forming electrodes in each of the high concentration impurity diffusion regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5216586A JPS62209868A (en) | 1986-03-10 | 1986-03-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5216586A JPS62209868A (en) | 1986-03-10 | 1986-03-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62209868A true JPS62209868A (en) | 1987-09-16 |
Family
ID=12907218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5216586A Pending JPS62209868A (en) | 1986-03-10 | 1986-03-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62209868A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989005041A1 (en) * | 1987-11-23 | 1989-06-01 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
-
1986
- 1986-03-10 JP JP5216586A patent/JPS62209868A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989005041A1 (en) * | 1987-11-23 | 1989-06-01 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
| US4910158A (en) * | 1987-11-23 | 1990-03-20 | Hughes Aircraft Company | Zener diode emulation and method of forming the same |
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