JPH08167619A - Manufacture of vertical mos semiconductor device - Google Patents

Abstract

PURPOSE: To provide a manufacturing method of a vertical MOS semiconductor device which maintains on-resistance reduction allowed by pattern miniaturization and allows breakdown voltage improvement and speed increase. CONSTITUTION: The manufacturing method of a vertical MOS semiconductor device includes a process of forming a gird ring diffusion area 3 on semiconductor substrates 1 and 2 and a process of forming a body area 6 by diffusion and introducing a life time killer material into the semiconductor substrate 1 with the dopant which forms the body area 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical MOS semiconductor device, and more particularly to a method for manufacturing a vertical MOS semiconductor device having a high breakdown voltage and high output such as a power MOSFET or an insulated gate bipolar transistor (IGBT). Regarding

[0002]

2. Description of the Related Art FIG. 3 shows a conventional general power MOSF.
It is sectional drawing of ET. An N ⁺ type silicon semiconductor substrate 1 is provided with an N ⁻ type epitaxial layer 2. The N ⁻ type epitaxial layer 2 to be the drain region is provided with a large number of regularly arranged P type body regions 6,
An N ⁺ type source region 5 is formed in the type body region 6 to form an individual cell. A gate electrode 8 made of polycrystalline silicon is arranged above the adjacent body regions 6 and 6 via a thin gate insulating film. The source electrode 9 made of an aluminum film connects the source region 5 and the body region 6 in a short-circuited state.

When a positive voltage is applied to the drain electrode on the back surface of the semiconductor substrate 1 and a constant voltage above the threshold is applied to the gate electrode 8 with the source electrode 9 grounded, the N ⁺ type source region 5 and the drain region 2 are formed. An inversion layer is formed on the surface of the body region 6 (the surface of the channel region 4) between them, a channel of majority carriers is formed, and the MOSFET is turned on.

In the N ⁻ type epitaxial layer 2, a P ⁺ type guard ring diffusion region 3 is formed in the peripheral portion of the chip so as to surround a number of regularly arranged body regions 6. Furthermore, an N ⁺ type channel stop diffusion region 10 is provided at the surface end portion of the chip, and a shield electrode 11 made of, for example, an aluminum film is provided as the channel stop diffusion region 10.
Have ohmic contact with. In such a structure, the guard ring region 3 is for evenly spreading the depletion layer at the time of reverse bias to obtain a high breakdown voltage. A thick oxide film 7 is provided on the N ⁻ type epitaxial layer 2 which becomes the drain region. The oxide film 7 is subjected to phosphorus treatment or the like so as to suppress the instability of the interface and realize the uniform spread of the depletion layer, and prevents the breakdown voltage between the drain 2 and the body 6 from deteriorating and the leak current from increasing. .

[0005]

Conventional vertical MOS according to the related art
In the semiconductor device, the guard ring diffusion region 3 and the convex portion of the body region 6 are formed in the same diffusion process, and usually have the same diffusion depth. For this reason, if the diffusion of the guard ring diffusion region 3 is deepened to increase the breakdown voltage, the convex portions of the body region 6 in the cell are also deeply diffused.
Therefore, although high breakdown voltage can be achieved, each body region 6, 6
The cells must be separated by a certain distance, which increases the cell size and the on-resistance.

In some power MOSFETs, a lifetime killer such as Pt (platinum) is injected in order to increase the speed of the built-in diode and in some IGBTs to increase the speed of itself. is there. In such a case, a lifetime killer of Pt (platinum) or the like is added in a minute amount to boron as a dopant in the same diffusion step for forming the convex portions of the guard ring diffusion region 3 and the body region 6. It is mixed and doped with diffusion of the dopant in the semiconductor substrate.

However, since the lifetime killer originally promotes recombination of minority carriers by creating a defect level in the crystal, a large amount of the lifetime killer introduced into the semiconductor substrate increases the leak current. There is a problem. Further, there is no problem that the leakage current increases when the amount of the lifetime killer is small, but there is no effect of improving the switching speed of the diode built in the power MOSFET or the IGBT.

The present invention has been made in view of the above-mentioned circumstances, and is a vertical MO that can maintain a reduction in on-resistance due to a finer pattern and can achieve a higher breakdown voltage and a higher speed.
An object is to provide a method for manufacturing an S semiconductor device.

[0009]

According to the method of manufacturing a vertical MOS semiconductor device of the present invention, a step of forming a guard ring diffusion region in a semiconductor substrate separately from the formation of a body region, and a step of forming the guard ring diffusion region after the formation of the guard ring diffusion region are performed. A step of introducing a lifetime killer material into the semiconductor substrate together with a dopant forming the body region to form the body region by diffusion.

[0010]

Since the guard ring diffusion region in the peripheral portion of the chip is formed by diffusing independently from the convex portion of the body region in the cell portion, depletion is achieved by the deep guard ring diffusion region containing no lifetime killer material. The layers can be spread deeper and uniformly, and high breakdown voltage can be realized. Then, by forming a relatively shallow body region, miniaturization of the cell size,
Along with lowering the on-resistance, it is possible to increase the speed of the vertical MOS semiconductor device by introducing the lifetime killer material.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a sectional view of a power MOSFET manufactured by a manufacturing method according to an embodiment of the present invention. In this embodiment, the diffusion depth of the P ⁺ guard ring diffusion region 3 is formed deeper than the diffusion depth of the convex portion of the P ⁺ body region 6. Unlike the conventional method, this guard ring diffusion is performed independently of the diffusion of the body region without including the lifetime killer material. In forming the body region 6, P, together with boron which is a dopant forming the body region, is used.
t (platinum) is doped as a lifetime killer material and widely diffused in the semiconductor substrates 1 and 2. The diffusion depth of the convex portion of the body region 6, the diffusion depth of the channel portion 4 of the body region 6, and the diffusion depth of the N ⁺ type source region 5 are the same as those of the conventional structure. Further, the arrangement of the gate electrode 8 and the like is the same as that of the conventional structure, and the distance between the adjacent body regions 6 and 6 is also the same.

In this embodiment, the diffusion depth of the P ⁺ type guard ring region is about 15 to 30 μm, and the diffusion depth of the convex portion of the P ⁺ type body region 6 is about 5 to 10 μm. The diffusion depth of the channel portion 4 is about 3 μm. With such a structure, the breakdown voltage can be greatly improved while the pattern is miniaturized and the ON resistance is maintained at the conventional value.

As a conventional method of performing the diffusion of the guard ring and the diffusion of the body region by one-time diffusion, the body regions are diffused up to the depth of the guard ring diffusion region of this embodiment to maintain the interval between the body regions. Compared with the case described above, the pattern can be miniaturized to the extent that the number of cells on the chip is quadrupled, and the on-resistance can be reduced to about 1/2.

Further, as the body region 6 is formed by diffusion, Pt (platinum), which is a lifetime killer material, is widely diffused in the semiconductor substrate. This Pt (platinum) diffusion has a large diffusion constant and widely spreads throughout the substrate, but in reality, the concentration is high in the P ⁺ body region that is the diffusion source, that is, in the vicinity of the cell area, and as a lifetime killer. It is considered that the effect of is highly exerted. Therefore, when minority carriers are injected into the built-in diode formed by the P ⁺ type body region 6 and the N ⁻ type drain region 2, recombination is promoted in the drain region 2,
The switching speed of the diode can be improved. Compared with the conventional technique of doping the lifetime killer when forming the guard ring diffusion region, the concentration of Pt (platinum) becomes relatively low in the vicinity of the guard ring diffusion region 3, so that the increase in leak current is prevented and the breakdown voltage is increased. Can be kept high.

Next, the power MOSFE of one embodiment of the present invention
A method of manufacturing T will be described with reference to FIG.

First, N having the N ^-- type epitaxial layer 2
^{A +} type semiconductor substrate 1 is prepared. Then, P ⁺ type impurities are introduced by resist patterning to form a deep guard ring diffusion region 3 in the peripheral portion of the chip as shown in FIG. At this time, the dopant is only boron and does not include the lifetime killer material. Further, unlike the conventional manufacturing process, no diffusion region is formed in the cell region portion.

Next, as shown in FIG. 2B, P is added to the cell portion.
^{A +} type body region 6 is formed. In forming the body region 6 which is the diffusion region, a deep diffusion region 6 is formed by applying a polyboron film (trade name) containing Pt (platinum) on the surface of the semiconductor substrate and performing heat treatment.
Along with the formation of the body region 6 by boron, Pt (platinum)
Has a high diffusion coefficient, so that it spreads evenly in the semiconductor substrates 1 and 2, but its concentration is the P ⁺ -type body region 6 which is the diffusion source.
Is high in the periphery of the cell, and the guard ring diffusion region 3 in the periphery of the cell
It is considered to be relatively low in the surrounding area.

Next, the oxide film and the like adhering to the surfaces of the semiconductor substrates 1 and 2 are removed, and the power MOS is formed by the same procedure as in the conventional case.
Manufacturing FET. That is, first, a thick oxide film is formed on the surface of a semiconductor substrate, and a cell region is opened by resist patterning. Next, as shown in FIG. 3C, a thin oxide film is grown, a polycrystalline silicon film is deposited on the entire surface, and a gate electrode 8 is formed by resist patterning. Then, the P-type channel region 4 is formed by diffusion using the gate electrode 8 as a mask. Then, using the gate electrode 8 and the resist pattern as a mask, the N ⁺ type source region 5 is formed by ion implantation and heat treatment. Then, the contact portion is opened and an aluminum film is deposited on the entire surface by sputtering or the like, and an aluminum electrode 9 is formed by resist patterning.

The above-described embodiment is a power MOSFET.
Regarding N ⁺ type semiconductor substrate 1 to P ⁺
By making the device structure of the epitaxial layer 2 the same as the type, the gist of the present invention can be applied to the insulated gate bipolar transistor (IGBT) in exactly the same manner. That is, by separating the guard ring diffusion region 3 from the diffusion of the convex portion of the body region 6 and forming it deep without doping the lifetime killer material, the depletion layer can be made wider, and thus the depletion layer can be made wider. Withstand voltage can be realized. Then, independently of the formation of the guard ring diffusion region 3, the P ⁺ type body region 6 is formed relatively shallow using a dopant containing Pt (platinum) to reduce the fineness of the pattern and the on-resistance, and to perform switching. An insulated gate bipolar transistor (IGBT) with improved speed can be manufactured.

In the insulated gate bipolar transistor (IGBT), the PNP type transistor composed of the P ⁺ type body 6, the N ⁻ type drain region 2 and the P ⁺ type substrate 1 has a small number due to the existence of a lifetime killer. The recombination of carriers is promoted, and the switching speed of the IGBT itself can be improved.

Further, in the above-mentioned embodiment, the example of the N-channel vertical MOS semiconductor device has been explained.
It is needless to say that the same can be applied to the channel type vertical MOS semiconductor device. Further, in the above-described embodiment, the example in which the diffusion depth of the guard ring region is formed deeper than the convex portion of the body region while maintaining the diffusion depth of the cell portion has been described. By making the diffusion depth of the cell portion shallow while maintaining the depth, the cell size pattern is miniaturized, and the on-resistance is further reduced while maintaining a certain breakdown voltage to improve the switching speed. good. Furthermore, an example of using Pt (platinum) as the lifetime killer material has been described, but not limited to Pt (platinum), any material that is effective as a lifetime killer such as Au (gold) may be used. Good. As described above, various modifications can be made without departing from the spirit of the present invention.

In the drawings, the same reference numerals indicate the same or corresponding parts.

[0024]

As described above, according to the present invention, the vertical type M
The guard ring region is diffused independently of the body region of the OS semiconductor device, and the lifetime killer material is doped when the body region is diffused. As a result, it is possible to maintain the miniaturization of the pattern and the reduction of the on-resistance while realizing the high breakdown voltage of the vertical MOS semiconductor device, and the built-in diode or IG of the MOSFET.
BT can be speeded up.

[Brief description of drawings]

FIG. 1 is a sectional view of a vertical MOS semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a vertical MOS semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view of a conventional vertical MOS semiconductor device.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78

Claims (1)

[Claims] 1. A step of forming a guard ring diffusion region in the semiconductor substrate separately from the formation of the body region, and a lifetime killer material together with a dopant forming the body region in the semiconductor substrate after the formation of the guard ring diffusion region. And a step of forming a body region by diffusion to form a body region, the method for manufacturing a vertical MOS semiconductor device.