JPS63219164A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the pattern size for the enhancement of NPN transistor integration by a method wherein a deep high-concentration collector region is formed to surround a base region and the degree of impurity concentration is so set as to reduce the resistance the collector presents. CONSTITUTION:An N-type high-concentration region is formed into a ring, which surrounds an emitter region 27 and is provided with a portion 32 sandwiching a base region 26 and extending in parallel with the surface of an island region 25. The impurity concentration in a high-concentration collector region 28 is so set that a value VCBO1, which is an apparent value dependent upon a P-N junction between the base region 26 on the surface of the island region 25 and the high-concentration collector region 28, will not be lower than a value VCEO which is dependent upon a P-N junction between the base region 26 and the island region 25 just under the emitter region 27 active as a transistor component. Under the conditions, the portion 32 helps the saturation voltage to decrease further, which results in a reduced contact resistance and enhanced integration.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to improvements in NPN transistors incorporated into integrated circuits (ICs).

(b) Conventional technology Figure 3 shows a conventional NPN type transistor incorporated in an IC. An N+ type buried layer (3) formed in and an epitaxial layer (2)
An island region (5) separated into islands by a P+ type isolation region (4) penetrating through the P+ type isolation region (4) and a P
The base region (6) of the mold, the N+ type emitter region (7) formed on this surface, and the N+ type emitter region (7) formed on the surface of the island region (5).
It consists of a type collector contact region (8) and an electrode (10) that makes ohmink contact with each region through a contact hole formed in an oxide film (9).

The structure that refuses is the simplest and most common one, but the collector output resistance is large and the saturation voltage ■.

, (sat) is large.

Therefore, as shown in FIG. 4, conventionally, by providing an N+ type collector low resistance region (11) extending from the surface of the island region (5) to the buried layer (3), the collector extraction resistance can be reduced and Vcp(sat) For example, an NPN type transistor with a significantly smaller size is described in Fig. 1 of Japanese Patent Application Laid-open No. 59-74649.By providing a collector low resistance region (11), .,(sat
) can be reduced to about 173.

(c) Problems to be solved by the invention However, since the collector low resistance region (11) is formed by diffusion quite deeply from the surface of the epitaxial layer (2) to the buried layer (3), lateral diffusion is difficult. The drawback was that it could not be highly integrated. Moreover, collector low resistance region (11)
must be set at a high impurity concentration to diffuse quite deeply, whether it is in the base region (6) or isolation region (4).
If it comes into contact with the device, the withstand voltage will drop dramatically, which is a factor that prevents even higher integration.

(2) Means for solving the problems The present invention was made in view of the above-mentioned drawbacks, and the emitter region (
27) in a ring shape and base area (26)
An N-type high-concentration collector region (28) is formed so as to have a portion extending parallel to the surface of the island region (25), and its impurity concentration is set to the apparent base-collector breakdown voltage. VCBOI is determined by the actual base-collector breakdown voltage VCBO2, the emitter-collector breakdown voltage VC! ! By setting the impurity concentration to be no lower than O, it is possible to provide a semiconductor integrated circuit that improves the conventional drawbacks while maintaining the breakdown voltage.

(e) Effects According to the present invention, since the highly doped collector region (28), which is more doped than the epitaxial layer (22), surrounds the base region (26), the collector extraction resistance is reduced.

(sat) can be made small. Moreover, the portion (32>) extending parallel to the surface of the island region (25) at the bottom of the base region (26) of the high concentration collector region (28) further reduces Vc and (sat). The region (28) is a PN junction between the base region (26) and the island region (25) and a P-N junction between the island region (25) and the isolation region (24).
Since the depletion layer generated in the N junction is suppressed, the base region < 2
6) The distance from the peripheral end to the separation region (24) can be reduced.

In addition, the base region (26) and the high concentration collector region (28)
), the apparent base-collector breakdown voltage Vceo+ at the surface of the island region (25) decreases; 8° is an element related to the stone, and it is the base region (26
) and the island region <25), the substantial base-collector breakdown voltage ■ is determined by the PN junction. ll.

, so even if the apparent VCIIO+ decreases, the V. a. ■It is not related to this and remains the same as before. ,
. is obtained.

(f) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIGS. 1A and 1B show a semiconductor integrated circuit according to the present invention, which includes an N-type epitaxial layer (22) formed by laminating a P-type semiconductor substrate (21) and a buried layer on the surface of the substrate (21). A P+ type isolation region (24) penetrating the epitaxial layer (22) surrounding this buried layer (23), and an isolation region (24) formed by
), a P-type base region (26) formed on the surface of the island region (25), and an N+ type base region (26) formed on the surface of the base region (26). emitter region (27), an N-type high concentration collector region (28) formed to surround the emitter region (26), and a collector contact region (29) formed on the surface of the island region (25) by an emitter diffusion process. , an oxide film (30) covering the epitaxial layer (22), and a base region (26), an emitter region (27), and a collector contact region (29) through contact holes opened in this oxide film (30). and electrodes (31) that are in ohmic contact with each other.A highly concentrated collector region (
If a good ohmic contact can be obtained only with 28), the collector contact region (29) is unnecessary.

The highly concentrated collector region (28), which is a feature of the present invention, is formed so as to be in contact with the base region (26) and also with the isolation region (24), and its depth is deeper than the base region (26). The layer (23>) is formed to be shallower than the upper part.If it is shallower than the base region (26>), it is disadvantageous in terms of Vcx (sat) characteristics, which will be explained later.
23) It is unreasonable in terms of impurity concentration and diffusion time to form the layer deeply. In addition, the high concentration collector region (2
8) except for the emitter region (27) and the base region (26)
By overlapping most of the base area (26)
An island region (25) at the bottom and a portion (32) extending parallel to the surface.
) is formed. and high concentration collector region (28)
The apparently observed VCBOI is determined by the PN junction between the base region (26) and the highly doped collector region (28) on the surface of the island region (25), but the impurity concentration is determined by the impurity concentration directly under the emitter region (27) active as a transistor. V determined by the PN junction between the base region (26) and the island region (25). The impurity concentration is set so as not to fall below 2o. In the conventional structure, when the base region (6) and the collector contact region (8) come into contact, the above-mentioned apparent V. BOI
It is known that the impurity concentration decreases to several volts, so this impurity concentration is higher than the epitaxial layer (22) and lower than the emitter region (27), specifically, 1012 to 10
It is around '4. Due to the contact between the high concentration collector region (28) and the separation region (24), the separation withstand voltage (■) is achieved. -5
Although there is a risk that UB will decrease, the separation region (24) is the deepest diffusion region and has a fairly gentle concentration gradient, so the withstand voltage is around 100V in the conventional structure, and several tens of V in the present invention. There is no problem in practical use as it maintains

Emitter-collector breakdown voltage is one of the important elements of transistor characteristics. It is known that 8o is expressed by the following formula.

Vcio=BVci+oam bπ””””””””・・
(i) (where B is a proportionality constant and n is an integer) Here, VclLo is h□ times 1°ll. (base-collector current). . Since this is the voltage at which an avalanche-like multiplication phenomenon of (emitter-collector current) occurs,
Ultimately, the diode-like avalanche breakdown voltage of the base-collector junction in the region that determines the Vc++ oz value in equation (1), that is, the base region (26) and island region (25) directly below the emitter region (27) active as a transistor. P of
It means the breakdown voltage of N junction. Therefore, as in the present application, the .largecircle. BOI
Even if Vceog is subtracted, vceog in equation (1) does not change, so V expressed in equation (1). It has no effect on 6o. However, as mentioned above, the emitter.

Since there is a carrier flow of htx/ICll0 between the collectors, avalanche breakdown is more likely to occur than with base-collector diodes, and VCI! It is clear from equation (1) that O<VCBO. Therefore, VCBOI is vo. Although it has nothing to do with VCB. ■ Determined by . 6o
If you go below that, it will be V. KO = VCBOI.

Figure 2 shows such a V. 140% VcBo+, VCB
This is a characteristic diagram for explaining the relationship between O2, and the horizontal axis shows hFI+.
The breakdown voltage is plotted on the vertical axis. From equation (1), ■. l
! o is hFl! The larger the value, the lower the VC! 101
and ■. BOffi is hF! becomes constant with respect to now,
If the VCBOI of the conventional structure has the value shown in the figure, vcBoa will exhibit a slightly higher value due to the concentration gradient in the base region (<26). Although the VCBOI of the structure according to the present invention is reduced due to the contact between the highly doped collector region (28) and the base region (26),
CBOI remains unchanged for the reasons mentioned above, and vcB
ot is V. Vcxo remains unchanged unless it goes below 8o.

Further, in the present invention, it is preferable to set the impurity concentration of the high concentration collector region (28) in consideration of the ho of the transistor. In other words, when manufacturing a transistor, if the value of hF8 is set to 100, the veto value of the transistor is
Since it is necessary and sufficient to maintain the value at point A in FIG.
OI ), hFl! ■ in the range of 100 or less.

BOI is ■. Even if the impurity concentration is set to less than 80, a transistor can be obtained with no practical problems.

Therefore, according to the present invention, while maintaining the same withstand voltage as before,
A highly doped collector region (28) with a higher concentration than the epitaxial layer (22) occurs at the PN junction between the base region (26) and the island region (25) and at the PN junction between the island region (25) and the isolation region (24). Since the depletion layer is suppressed, the base region (
26) to the separation region (24),
Can be highly integrated. In addition, since the highly concentrated collector region (28) surrounds the base region (26) in a ring shape, the collector extraction resistance is reduced and Ve! (sat) can be made small. Moreover, the portion (32) extending parallel to the surface of the island region (25) provided at the bottom of the base region (26) further lowers the resistance to take out the collector by approximately 1 compared to that in FIG.
■ Even smaller than 72. , (sat) are obtained. Furthermore, it also contributes to preventing the formation of a P-type inversion layer on the surface of the island region <25).

(G) As described in detail, according to the present invention, by selecting the impurity concentration of the high concentration collector region (28), the pattern size can be increased while maintaining the withstand voltage of several tens of microns, which is the same as that of the conventional one. It has the advantage of being able to provide a semiconductor integrated circuit that can be highly integrated by reducing the pattern size.Also, while reducing the pattern size, the part where the highly doped collector region (28) surrounds the base region (26) and extends in parallel ( 32) is the emitter region (27)
Since it surrounds the lower part of the collector, the extraction resistance of the collector is greatly reduced to about 172 or less compared to the one in FIG.

! ! (sat). Furthermore, since the highly concentrated collector region (28) is formed on the surface of the island region (25) except for the base region (26), it also has the advantage of preventing a P-type inversion layer on the surface of the island region (25).

[Brief explanation of the drawing]

1A and 1B are a sectional view and a plan view, respectively, for explaining the present invention, FIG. 2 is a characteristic diagram for explaining the present invention, and FIGS. 3 and 4 are for explaining a conventional example. FIG. (21) is a P type semiconductor substrate, (24> is a P″″ type isolation region, (25> is an island region, (26) is a P type base region, (27) is an N+ type emic region, (28) is an N The high concentration collector region (32) of the mold is a part extending parallel to the surface of the island region (25). Applicant: Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 1 A Figure 1B Figure 2Figure 3

Claims (1)

[Claims] (1) A base region of one conductivity type formed on the surface of the island region serving as a collector, an emitter region of the opposite conductivity type formed on the surface of the base region, and a a highly concentrated collector region of opposite conductivity type with a portion extending parallel to the surface of the island region;
The impurity concentration of the high concentration collector region is determined by the breakdown voltage of the PN junction between the base region and the high concentration collector region on the surface of the island region, and the base of the PN junction between the base region and the island region directly below the emitter region. - A semiconductor integrated circuit characterized in that the impurity concentration is set to be higher than the emitter-collector breakdown voltage determined by the collector-collector breakdown voltage.