JPS63250865A - Pressure detecting element and manufacture thereof - Google Patents
Pressure detecting element and manufacture thereofInfo
- Publication number
- JPS63250865A JPS63250865A JP8646787A JP8646787A JPS63250865A JP S63250865 A JPS63250865 A JP S63250865A JP 8646787 A JP8646787 A JP 8646787A JP 8646787 A JP8646787 A JP 8646787A JP S63250865 A JPS63250865 A JP S63250865A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- substrate
- main surface
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 18
- 239000003566 sealing material Substances 0.000 claims abstract description 4
- 238000007789 sealing Methods 0.000 claims abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 3
- 238000005304 joining Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000035945 sensitivity Effects 0.000 abstract description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 26
- 238000001514 detection method Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Landscapes
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
- Weting (AREA)
Abstract
Description
本発明は、半導体マイクロ素子を用いた高感度、高精度
の圧力検出素子とその製造方法に関する。TECHNICAL FIELD The present invention relates to a highly sensitive and highly accurate pressure sensing element using a semiconductor microelement and a method for manufacturing the same.
従来、圧力によって生じる機械的応力をピエゾ抵抗効果
により検出して、圧力を測定する半導体圧力検出素子が
知られている。その半導体圧力検出素子は、単結晶シリ
コン基板の一部の肉厚を薄くしてダイヤプラムを形成し
、そのダイヤフラムに形成されたエピタキシャル層内に
感圧素子を拡散等で形成したものである。そして、圧力
は、ダイヤフラムに加わる圧力により生じるダイヤフラ
ムの歪みを感圧素子のピエゾ抵抗効果によって生じる抵
抗値の変化として検出される。2. Description of the Related Art Conventionally, semiconductor pressure sensing elements are known that measure pressure by detecting mechanical stress caused by pressure using a piezoresistive effect. The semiconductor pressure sensing element is made by thinning a portion of a single crystal silicon substrate to form a diaphragm, and a pressure sensing element is formed in an epitaxial layer formed on the diaphragm by diffusion or the like. Then, the pressure is detected as a change in the resistance value caused by the piezoresistive effect of the pressure-sensitive element, which is the distortion of the diaphragm caused by the pressure applied to the diaphragm.
上記の感圧素子は単結晶シリコン基板内にＰＮ接合で絶
縁されて形成されているため、圧力検出素子が高温環境
で使用されると、ＰＮ接合でのリーク電流が増加し、圧
力を正確に安定して検出できないという問題がある。
また、ダイヤフラムの形成は単結晶シリコン基板を感圧
素子の形成される側と反対側からエツチングすることに
より行われるため、ダイヤフラムの膜厚の均一な制御が
困難であり、素子の検出特性が不均一となる。
また、エツチングを単結晶シリコン基板の裏面から行っ
ており、ダイヤフラムを極薄く形成することが困難であ
るため、感圧素子を小型に構成することが困難である。
更に、絶縁層上に感圧素子を形成して、感圧素子を電気
的に絶縁するには、感圧素子に多結晶半導体が用いられ
ているが、多結晶半導体で感圧素子を構成すると、素子
特性の均一性と感度の点で問題がある。また、絶縁膜上
の多結晶シリコンを再結晶化して単結晶の感圧層を形成
することも行われているが、依然として素子特性の均一
性に問題があり、再結晶化するための特別の装置を必要
とするという問題もある。
本発明は上記の問題点を解決するためになされたもので
あり、その目的とするところは、小型で、高温でも安定
して圧力測定の可能な且つ素子特性が均一な高感度の圧
力検出素子とその製造方法を提供することである。The above pressure sensing element is formed in a single crystal silicon substrate insulated with a PN junction, so when the pressure sensing element is used in a high temperature environment, leakage current at the PN junction increases, making it difficult to accurately measure pressure. There is a problem that stable detection is not possible. Furthermore, since the diaphragm is formed by etching the single-crystal silicon substrate from the side opposite to the side on which the pressure-sensitive element is formed, it is difficult to control the film thickness of the diaphragm uniformly, resulting in poor detection characteristics of the element. It becomes uniform. Furthermore, since etching is performed from the back side of the single crystal silicon substrate, it is difficult to form an extremely thin diaphragm, making it difficult to construct a pressure sensitive element in a small size. Furthermore, in order to electrically insulate the pressure sensitive element by forming it on an insulating layer, a polycrystalline semiconductor is used for the pressure sensitive element. However, there are problems in terms of uniformity of device characteristics and sensitivity. In addition, attempts have been made to recrystallize polycrystalline silicon on an insulating film to form a single-crystal pressure-sensitive layer, but there is still a problem with the uniformity of device characteristics, and special methods are required for recrystallization. Another problem is that it requires equipment. The present invention has been made to solve the above problems, and its purpose is to provide a compact, highly sensitive pressure sensing element that can stably measure pressure even at high temperatures and has uniform element characteristics. and its manufacturing method.
本発明は上記問題点を解決するため、以下の手段を採用
する。即ち、本発明は、基板と、基板の主面に接合され
た耐エッチ性の良い第１絶縁層と、前記第１絶縁層のダ
イヤフラム部上に形成された単結晶半導体から成る感圧
層と、前記感圧層を覆うように形成された第２絶縁層と
、前記ダイヤフラム部周辺に前記基板に垂直な方向に、
前記第２絶縁層、前記第１絶縁層を貫通して形成された
エッチ孔と、そのエッチ孔を介して、前記第１絶縁層の
ダイヤフラム部下の前記基板をエツチングして形成され
た空洞と、前記エッチ孔を封止する封止材とから成る圧
力検出素子である。また、その製造方法発明は、素子基
板の主面の一定領域にエッチ速度の速い中間層を形成し
、単結晶半導体基板の主面から不純物をドープして感圧
層を形成し、感圧層の形成された単結晶半導体基板の主
面に第１絶縁層を形成し、第１絶縁層の形成された単結
晶半導体基板の主面と前記素子基板の主面とを接合し、
素子基板に接合された単結晶半導体基板のうち、前記感
圧層を残して残部の半導体を除去し、前記感圧層を覆う
ように第２絶縁層を形成し、前記中間層の周辺部に前記
素子基板に垂直な方向に、前記第２絶縁層及び前記第１
絶縁層を貫通し前記中間層に至るエッチ孔を形成し、そ
のエッチ孔を介して、前記中間層及び中間層下の前記素
子基板の一部をエツチングして空洞を形成し、前記エッ
チ孔を封止することをことを特徴とする。In order to solve the above problems, the present invention employs the following means. That is, the present invention includes a substrate, a first insulating layer with good etch resistance bonded to the main surface of the substrate, and a pressure sensitive layer made of a single crystal semiconductor formed on a diaphragm portion of the first insulating layer. , a second insulating layer formed to cover the pressure sensitive layer, and a second insulating layer formed around the diaphragm portion in a direction perpendicular to the substrate;
an etch hole formed through the second insulating layer and the first insulating layer, and a cavity formed by etching the substrate below the diaphragm of the first insulating layer through the etch hole; and a sealing material that seals the etched hole. In addition, the manufacturing method invention includes forming an intermediate layer having a high etch rate in a certain region of the main surface of the element substrate, doping impurities from the main surface of the single crystal semiconductor substrate to form a pressure sensitive layer, and forming the pressure sensitive layer. forming a first insulating layer on the main surface of the single crystal semiconductor substrate on which the first insulating layer is formed, and joining the main surface of the single crystal semiconductor substrate on which the first insulating layer is formed and the main surface of the element substrate;
Of the single crystal semiconductor substrate bonded to the element substrate, the remaining semiconductor is removed leaving the pressure sensitive layer, a second insulating layer is formed to cover the pressure sensitive layer, and a second insulating layer is formed around the intermediate layer. the second insulating layer and the first insulating layer in a direction perpendicular to the element substrate;
forming an etch hole that penetrates the insulating layer and reaching the intermediate layer; etching the intermediate layer and a portion of the element substrate under the intermediate layer through the etch hole to form a cavity; It is characterized by being sealed.
ダイヤフラムは第１絶縁層で構成され、そのダイヤフラ
ム下に空洞をアンダーカットエツチングにより形成して
、極薄い膜厚制御の容易なダイヤフラムが形成される。
ダイヤフラムは検出圧に応じて変形し、その変形が第１
絶縁層上に形成された単結晶半導体の感圧層により検出
されることにより圧力の検出が行われる。The diaphragm is composed of a first insulating layer, and a cavity is formed under the diaphragm by undercut etching to form an extremely thin diaphragm whose thickness can be easily controlled. The diaphragm deforms according to the detected pressure, and this deformation is the first
Pressure is detected by being detected by a single crystal semiconductor pressure sensitive layer formed on the insulating layer.
以下、本発明を具体的な実施例に基づいて説明する。
第１図に示すように、例えば（１００）面を主面とし、
Ｎ型導電型、比抵抗３〜６Ωｃｍの素子基板としての第
１の単結晶シリコン基板１上に５ｉ−Ｎ＝膜２がＬＰＣ
ＶＤ法又はプラズマＣＶＤ法により、５００〜２０００
人の厚さに形成される。次に、第２図に示すように、上
方にダイヤフラムが形成される領域３の５ｉＪ４［２を
ホトリソグラフィ・エツチング工程により除去し、シリ
コン基板１の主面を露出させる。次に、第３図に示すよ
うに、領域３及びその周辺の５１−Ｎ４Ｍ２上に、多結
晶シリコン層４を０．５〜２μｍの厚さに形成する。こ
の多結晶シリコンはエッチ速度の速い中間層となる。次
に、第４図に示すように、多結晶シリコン層４及び５Ｌ
Ｎ４膜２−ヒに５ｉ＝Ｎ、膜５を５００〜２０００人厚
さに形成する。こうして形成されたＳｉ、Ｎ４膜２及び
ＳｉＪ＜膜５とで素子基板の主面に形成される絶縁層が
構成される。
次に、第５図に示すように、第１の単結晶シリコン基板
１とは別の、Ｎ型導電型の例えば（１００）面を主面と
し、比抵抗３〜６Ωｃｍの第２の単結晶シリコン基板１
０の主面１０ａに、所定パターンに形成されたＳｉｎ、
膜をマスクとして硼素を高濃度に拡散し、マスクのＳ’
＋０２膜を除去してＰ＋ピエゾ抵抗素子１１を形成する
。このＰ＋ピエゾ抵抗素子１１が感圧層となる。そして
、第６図に示すように、Ｐ＋ピエゾ抵抗素子１１の形成
された第２の単結晶シリコン木板１０の主面１０ａ上に
Ｓｉ、Ｎ４膜１２を厚さ ５００〜２０００人に形成す
る。このＳｉ＋ＩＮ、膜１２が第１絶縁層となる。
次に、第７図に示すように、第１の単結晶シリコン基板
１の最表面層であるＳ＋３Ｎ−Ｗｊ！５上に、Ｓ○Ｇ
（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ）膜６を約１〜３μｍの
厚さに形成する。次に、第８図に示すように、第２の単
結晶シリコン基板１０の最表面層である５ｉＪ４膜１２
がＳＯＧ膜６に接合するように第１の単結晶シリコン基
板１と第２の単結晶シリコン基板１０とを赤外顕微鏡で
位置合わせし重ね合わせる。
そして、３００〜４００℃に加熱し、５〜１０ｋｇ／Ｃ
ｒｌに加圧して、５Ｉ３Ｎ−膜５と５ｉｓＮ４Ｗ１１２
、即ち、第１絶縁層と第２絶縁層とを５ＯＧＩＩ＊６を
介して接合する。更に、接合強度を得るため、ＳＯＧ膜
６の燃焼を９００〜１０００℃で行い、接合素子Ａを得
る。
次に、第９図に示すように、接合素子Ａにおける第２の
単結晶シリコン基板１０を表面からラッピングにより大
部分除去し、最終的に、他の面をワックス等で覆い、エ
チレンジアミン（２６０ｍｌ）、ピロカテコール（４５
ｇ） 、水（１２０ｍｌ）を主成分とするエツチング液
で第２の単結晶シリコン基板１０の基板部分を完全に除
去する。この時Ｎ型シリコンの基板部分が選択的にエツ
チングされ、高濃度にボロンを拡散したＰ＋ピエゾ抵抗
素子１１は殆どエツチングされずに残る。
次に、第１０図に示すように、接合素子Ａの最表面に第
２絶縁層としての５ｉ３１１４膜１３を５００〜２００
０Ａの厚さに形成する。
次に、第１１図に示すように、接合素子Ａの最表面から
５ｉａＮ＜膜１３．５ｉａＬ膜１２、ＳＯＧ膜６．５１
３Ｎ４膜５を貫通し多結晶シリコン層４に至るエッチ孔
１４を、ホトリソグラフィ、ドライエツチングにより形
成する。
次に、第１２図に示すように、８０〜９０℃の水酸化カ
リウム（ＫＯｌｌ）アルカリ溶液中に接合素子Ａを浸し
、エツチングにより空洞１５を形成する。このエツチン
グ工程において、５ｉａＬ膜１３．５ｔ３Ｎ４膜１２、
ＳＯＣ膜６．５ｉｐＮｎ膜５は、殆どエツチングされず
、多結晶シリコン層４と単結晶シリコン基板１がエツチ
ングされる。多結晶シリコン層４はエッチ速度が速いた
め、５ｉＪｎ膜５下のアンダーカットエツチングが良好
に行われる。また、単結晶シリコン基板１に対しては、
上記のエッチンダ液は異方性エツチングとして機能する
ため、単結晶シリコン基板１には所定形状の空洞１５が
形成される。続いて、エツチング液を除去し接合素子Ａ
を洗浄する。
次に、第１３図に示すように、減圧中で、プラズマＣＶ
ＤでＰ−ＳｉＮ膜１６を結合素子Ａの最表面上に形成し
、エツチング孔１４を封止する。このＰ−ＳｉＮ膜１６
が封止材となる。こうして、空洞１５は真空状態で外界
から遮断されるため、空洞１５の内圧はほぼ０気圧とな
り圧力検出の基串圧が得られる。
その後、通常のＩＣウェハ製造工程により配線層等を形
成し、超小型で感圧層が単結晶シリコンよりなる半導体
圧力検出素子が得られる。上記の構成では、５ｉＪ４膜
１２、ＳＯＧ膜６、ＳｉＪ＜膜５でグイツヤラムが構成
されている。
尚、第１の単結晶シリコン基板１の主面は（１００）面
をを用いているが、（１１０）面であってもよく、Ｐ型
厚電型であってもよい。
上記実施例では、空洞１５を形成するのにエツチングさ
れる体位は比較的小さくなっているので、第１の単結晶
シリコン基板１を有効に使用することができる。このた
め、第１の単結晶シリコン基板１内にピエゾ抵抗素子１
１からの信号を処理する回路を形成する場合に、素子全
体を小型化することができる。また、信号処理回路はピ
エゾ抵抗素子１１を５１３Ｎ４膜１２上に形成する工程
でピエゾ抵抗素子１１と同時に形成してもよい。
また、ピエゾ抵抗素子１１のパターン形成は５１３Ｎ４
膜１２とＳＩ３Ｎ４膜５とを接合した後、ホトリソグラ
フィ、エツチング工程により行ってもよい。
また、アンダーカットエツチングを容易に行うためのエ
ッチ速度の速い中間層は、多結晶シリコンの他、非晶質
シリコン等を用いることができる。
また、上記実施例では中間層は、素子基板、即ち、第１
の単結晶シリコン基板１の主面上に形成しているが、主
面直下の基板をイオン打込により非晶質化させたりして
もよい。
また、３ｉＪ４膜１２と５ｉｓＮ４膜５との接合に、Ｓ
ＯＧ膜６を用いているが、ＰＳＧ膜による接合。
Ｓｉの直接接合等の方法で接合してもよい。
また、素子基板である第１の単結晶シリコン基板１の主
面に形成される絶縁膜の５ｉ−Ｎ、膜５はなくてもよく
、Ｓｉ、Ｎ、膜１２を中間ツの形成された第１の単結晶
シリコン基板１の主面に、陽極接合（アノ−ディックボ
ンディング）により接合してもよい。
また、エッチ孔１４の形状は特に限定されるものではな
く、円形状、角状、溝状であってもよい。
また、絶縁層は５ｉＪ４膜の他５ｉＯ７膜で形成しても
良い。The present invention will be described below based on specific examples. As shown in FIG. 1, for example, the (100) plane is the main surface,
A 5i-N=film 2 is formed by LPC on a first single crystal silicon substrate 1 as an element substrate of N type conductivity type and a specific resistance of 3 to 6 Ωcm.
500 to 2000 by VD method or plasma CVD method
Formed to the thickness of a person. Next, as shown in FIG. 2, 5iJ4[2 in the region 3 where the diaphragm is formed above is removed by a photolithography/etching process to expose the main surface of the silicon substrate 1. Next, as shown in FIG. 3, a polycrystalline silicon layer 4 is formed to a thickness of 0.5 to 2 .mu.m on the region 3 and the 51-N4M2 around it. This polycrystalline silicon becomes an intermediate layer with a high etch rate. Next, as shown in FIG. 4, polycrystalline silicon layers 4 and 5L are formed.
5i=N on the N4 film 2-H, and the film 5 is formed to a thickness of 500 to 2,000 layers. The Si, N4 film 2 and SiJ< film 5 thus formed constitute an insulating layer to be formed on the main surface of the element substrate. Next, as shown in FIG. 5, a second single crystal of N type conductivity type, for example, the (100) plane is the main surface and has a specific resistance of 3 to 6 Ωcm, which is different from the first single crystal silicon substrate 1. Silicon substrate 1
Sin formed in a predetermined pattern on the main surface 10a of 0,
Using the film as a mask, boron is diffused at a high concentration, and the S' of the mask is
The +02 film is removed to form a P+ piezoresistive element 11. This P+ piezoresistive element 11 becomes a pressure sensitive layer. Then, as shown in FIG. 6, a Si, N4 film 12 is formed to a thickness of 500 to 2000 on the main surface 10a of the second single-crystal silicon wood board 10 on which the P+ piezoresistive element 11 is formed. This Si+IN film 12 becomes the first insulating layer. Next, as shown in FIG. 7, the outermost layer of the first single crystal silicon substrate 1, S+3N-Wj! 5 on top, S○G
A (Spin On Glass) film 6 is formed to a thickness of about 1 to 3 μm. Next, as shown in FIG. 8, the 5iJ4 film 12 which is the outermost layer of the second single crystal silicon substrate 10
The first single-crystal silicon substrate 1 and the second single-crystal silicon substrate 10 are aligned and overlapped using an infrared microscope so that they are bonded to the SOG film 6. Then, heat it to 300-400℃ and apply 5-10kg/C.
Apply pressure to RL, 5I3N-membrane 5 and 5isN4W112
That is, the first insulating layer and the second insulating layer are bonded via 5OGII*6. Further, in order to obtain bonding strength, the SOG film 6 is burned at 900 to 1000° C. to obtain a bonded element A. Next, as shown in FIG. 9, most of the second single-crystal silicon substrate 10 in bonding element A is removed from the surface by lapping, and finally the other surface is covered with wax or the like, and ethylenediamine (260 ml) is applied. , pyrocatechol (45
g) Completely remove the substrate portion of the second single-crystal silicon substrate 10 using an etching solution mainly composed of water (120 ml). At this time, the N-type silicon substrate portion is selectively etched, and the P+ piezoresistive element 11 in which boron is diffused at a high concentration remains almost unetched. Next, as shown in FIG. 10, a 5i3114 film 13 with a thickness of 500 to 200
Formed to a thickness of 0A. Next, as shown in FIG. 11, from the outermost surface of the bonding element A, 5iaN< film 13.
An etch hole 14 penetrating the 3N4 film 5 and reaching the polycrystalline silicon layer 4 is formed by photolithography and dry etching. Next, as shown in FIG. 12, the bonding element A is immersed in a potassium hydroxide (KOll) alkaline solution at 80 to 90 DEG C., and a cavity 15 is formed by etching. In this etching step, the 5iaL film 13.5t3N4 film 12,
The SOC film 6.5ipNn film 5 is hardly etched, but the polycrystalline silicon layer 4 and the single crystal silicon substrate 1 are etched. Since the polycrystalline silicon layer 4 has a high etch rate, undercut etching under the 5iJn film 5 can be performed satisfactorily. Furthermore, for the single crystal silicon substrate 1,
Since the etching solution described above functions as an anisotropic etching, a cavity 15 of a predetermined shape is formed in the single crystal silicon substrate 1. Subsequently, the etching solution is removed and the bonding element A is removed.
Wash. Next, as shown in FIG. 13, under reduced pressure, the plasma CV
In step D, a P-SiN film 16 is formed on the outermost surface of the coupling element A, and the etching hole 14 is sealed. This P-SiN film 16
becomes the sealing material. In this way, since the cavity 15 is isolated from the outside world in a vacuum state, the internal pressure of the cavity 15 becomes approximately 0 atmospheres, and the base pressure for pressure detection is obtained. Thereafter, a wiring layer and the like are formed by a normal IC wafer manufacturing process to obtain an ultra-small semiconductor pressure sensing element whose pressure sensitive layer is made of single crystal silicon. In the above configuration, the 5iJ4 film 12, the SOG film 6, and the SiJ< film 5 constitute the guide layer. Although the main surface of the first single crystal silicon substrate 1 is a (100) plane, it may be a (110) plane or a P-type thick dielectric type. In the embodiment described above, the portions etched to form the cavity 15 are relatively small, so the first single crystal silicon substrate 1 can be used effectively. Therefore, the piezoresistive element 1 is placed inside the first single crystal silicon substrate 1.
When forming a circuit that processes signals from 1, the entire device can be miniaturized. Furthermore, the signal processing circuit may be formed simultaneously with the piezoresistive element 11 in the step of forming the piezoresistive element 11 on the 513N4 film 12. Moreover, the pattern formation of the piezoresistive element 11 is 513N4.
After bonding the film 12 and the SI3N4 film 5, photolithography and etching steps may be performed. Further, the intermediate layer having a high etch rate for easily performing undercut etching may be made of amorphous silicon or the like in addition to polycrystalline silicon. Further, in the above embodiment, the intermediate layer is the element substrate, that is, the first layer.
Although it is formed on the main surface of the single crystal silicon substrate 1, the substrate directly under the main surface may be made amorphous by ion implantation. Further, S is added to the junction between the 3iJ4 film 12 and the 5isN4 film 5.
The OG film 6 is used, but the PSG film is used for bonding. The bonding may be performed by a method such as direct bonding of Si. Furthermore, the 5i-N insulating film formed on the main surface of the first single crystal silicon substrate 1, which is the element substrate, and the film 5 may be omitted, and the Si, N, and film 12 may be formed on the main surface of the first single crystal silicon substrate 1, which is the element substrate. It may be bonded to the main surface of the single crystal silicon substrate 1 by anodic bonding. Further, the shape of the etch hole 14 is not particularly limited, and may be circular, angular, or groove-shaped. Further, the insulating layer may be formed of a 5iO7 film instead of a 5iJ4 film.
感圧層は単結晶半導体で構成されているため圧力検出感
度が向上し、圧力検出特性が安定し、素子間での検出特
性が均一化される。また、感圧層はｖＪｌ絶縁層と第２
絶縁層で囲まれているので、高温で使用されてもリーク
電流がなく検出特性が安定する。また、ダイヤプラムは
第１絶縁層で構成され、そのダイヤフラム下の空洞は基
板をアンダーカットエツチングすることにより形成され
ているので、ダイヤフラムの厚さ制御が容易となり、素
子間での検出特性が均一化される。また、ダイヤフラム
の厚さと基板の厚さを薄く構成できるので、検出素子を
小型化できる。さらに、感圧層は単結晶半導体基板に不
純物ドープにより形成されているので、レーザ再結晶化
装置の様な装置を必要としないので素子の製造が安価に
できる。Since the pressure sensitive layer is made of a single crystal semiconductor, pressure detection sensitivity is improved, pressure detection characteristics are stabilized, and detection characteristics are made uniform between elements. In addition, the pressure sensitive layer is a vJl insulating layer and a second
Since it is surrounded by an insulating layer, there is no leakage current and the detection characteristics are stable even when used at high temperatures. In addition, the diaphragm is composed of the first insulating layer, and the cavity under the diaphragm is formed by undercut etching the substrate, making it easy to control the thickness of the diaphragm and ensuring uniform detection characteristics between elements. be converted into Further, since the thickness of the diaphragm and the thickness of the substrate can be made thin, the detection element can be made smaller. Further, since the pressure sensitive layer is formed by doping a single crystal semiconductor substrate with impurities, a device such as a laser recrystallization device is not required, so that the device can be manufactured at low cost.
第１図乃至第１３図は、本発明の実施例に係る半導体圧
力検出素子の製造工程を示した断面図である。
１・・・第１の単結晶シリコン基板 ２・・・５ｉＪ４
膜４ ・多結晶シリコン層 ５・ Ｓｉ、Ｎ、膜 ６・
・・ＳＯＧ膜 １０・・・・第２の単結晶シリコン基板
１１・・ピエゾ抵抗素子 １２−・−３ｉＪＪＩ
１３・・Ｓ＋ｔＮ、膜 １４“・エッチ孔 １５°・′
・空洞 １６パ・Ｓｉ。
Ｎ４膜
特許出願人 日本電装株式会社
第１図
第４図
第１２図
７ 第１３図1 to 13 are cross-sectional views showing the manufacturing process of a semiconductor pressure sensing element according to an embodiment of the present invention. 1...First single crystal silicon substrate 2...5iJ4
Film 4 - Polycrystalline silicon layer 5 - Si, N, film 6 -
...SOG film 10...Second single crystal silicon substrate 11...Piezoresistance element 12--3iJJI
13...S+tN, film 14"・etch hole 15°・'
・Cavity 16 Pa・Si. N4 membrane patent applicant Nippondenso Co., Ltd. Figure 1 Figure 4 Figure 12 Figure 7 Figure 13
Claims (4)
、 前記第１絶縁層のダイヤフラム部上に形成された単結晶
半導体から成る感圧層と、 前記感圧層を覆うように形成された第２絶縁層と、 前記ダイヤフラム部周辺に前記基板に垂直な方向に、前
記第２絶縁層、前記第１絶縁層を貫通して形成されたエ
ッチ孔と、 そのエッチ孔を介して、前記第１絶縁層のダイヤフラム
部下の前記基板をエッチングして形成された空洞と、 前記エッチ孔を封止する封止材と から成る圧力検出素子。(1) a substrate, a first insulating layer with good etch resistance bonded to the main surface of the substrate, a pressure sensitive layer made of a single crystal semiconductor formed on a diaphragm portion of the first insulating layer, and the pressure sensitive layer formed on the diaphragm portion of the first insulating layer; a second insulating layer formed to cover the pressure layer; an etch hole formed around the diaphragm portion in a direction perpendicular to the substrate and penetrating the second insulating layer and the first insulating layer; A pressure sensing element comprising: a cavity formed by etching the substrate below the diaphragm of the first insulating layer through the etching hole; and a sealing material sealing the etching hole.
間層を形成し、 単結晶半導体基板の主面から不純物をドープして感圧層
を形成し、 感圧層の形成された単結晶半導体基板の主面に第１絶縁
層を形成し、 第１絶縁層の形成された単結晶半導体基板の主面と前記
素子基板の主面とを接合し、 素子基板に接合された単結晶半導体基板のうち、前記感
圧層を残して残部の半導体を除去し、前記感圧層を覆う
ように第２絶縁層を形成し、前記中間層の周辺部に前記
素子基板に垂直な方向に、前記第２絶縁層及び前記第１
絶縁層を貫通し前記中間層に至るエッチ孔を形成し、 そのエッチ孔を介して、前記中間層及び中間層下の前記
素子基板の一部をエッチングして空洞を形成し、 前記エッチ孔を封止する ことを特徴とする圧力検出素子の製造方 法。(2) Form an intermediate layer with a high etch rate in a certain area on the main surface of the element substrate, dope impurities from the main surface of the single crystal semiconductor substrate to form a pressure sensitive layer, and then forming a first insulating layer on a main surface of a crystalline semiconductor substrate; bonding the main surface of the single crystal semiconductor substrate on which the first insulating layer is formed and the main surface of the element substrate; and forming a single crystal bonded to the element substrate. The remaining semiconductor of the semiconductor substrate is removed leaving the pressure sensitive layer, a second insulating layer is formed to cover the pressure sensitive layer, and a second insulating layer is formed around the intermediate layer in a direction perpendicular to the element substrate. , the second insulating layer and the first
forming an etch hole that penetrates the insulating layer and reaching the intermediate layer; etching the intermediate layer and a portion of the element substrate under the intermediate layer through the etch hole to form a cavity; A method for manufacturing a pressure sensing element, characterized by sealing it.
とする特許請求の範囲第２項記載の圧力検出素子の製造
方法。(3) The method for manufacturing a pressure sensing element according to claim 2, wherein the intermediate layer is made of polycrystalline silicon.
成した後、その絶縁層の主面と前記単結晶半導体基板に
形成された第１絶縁層の主面とを接合させることを特徴
とする特許請求の範囲第２項記載の圧力検出素子の製造
方法。(4) After forming an insulating layer on the main surface of the element substrate on which the intermediate layer is formed, joining the main surface of the insulating layer to the main surface of the first insulating layer formed on the single crystal semiconductor substrate. A method for manufacturing a pressure sensing element according to claim 2, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8646787A JP2508070B2 (en) | 1987-04-08 | 1987-04-08 | Pressure detecting element and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8646787A JP2508070B2 (en) | 1987-04-08 | 1987-04-08 | Pressure detecting element and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63250865A true JPS63250865A (en) | 1988-10-18 |
| JP2508070B2 JP2508070B2 (en) | 1996-06-19 |
Family
ID=13887762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8646787A Expired - Fee Related JP2508070B2 (en) | 1987-04-08 | 1987-04-08 | Pressure detecting element and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2508070B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095401A (en) * | 1989-01-13 | 1992-03-10 | Kopin Corporation | SOI diaphragm sensor |
| US5177661A (en) * | 1989-01-13 | 1993-01-05 | Kopin Corporation | SOI diaphgram sensor |
| US5296730A (en) * | 1992-01-16 | 1994-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor pressure sensor for sensing pressure applied thereto |
| US5445991A (en) * | 1993-12-24 | 1995-08-29 | Kyungdook National University Sensor Technology Research Center | Method for fabricating a semiconductor device using a porous silicon region |
| US5490034A (en) * | 1989-01-13 | 1996-02-06 | Kopin Corporation | SOI actuators and microsensors |
| JP2003530234A (en) * | 2000-04-07 | 2003-10-14 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Micromechanical structure element and corresponding manufacturing method |
| JP2005246601A (en) * | 2004-03-03 | 2005-09-15 | Robert Bosch Gmbh | Micro-machining type component and suitable manufacturing method |
| USRE40347E1 (en) | 1992-04-27 | 2008-06-03 | Denso Corporation | Acceleration sensor and process for the production thereof |
| WO2012020930A2 (en) * | 2010-08-13 | 2012-02-16 | 전자부품연구원 | Capacitive pressure sensor and method for manufacturing same |
| CN110146177A (en) * | 2019-05-23 | 2019-08-20 | 北京北方高业科技有限公司 | A kind of preparation method of temperature-detecting device |
| WO2020158156A1 (en) * | 2019-01-31 | 2020-08-06 | オムロン株式会社 | Method for forming detection element and detection device |
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-
1987
- 1987-04-08 JP JP8646787A patent/JP2508070B2/en not_active Expired - Fee Related
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5177661A (en) * | 1989-01-13 | 1993-01-05 | Kopin Corporation | SOI diaphgram sensor |
| US5095401A (en) * | 1989-01-13 | 1992-03-10 | Kopin Corporation | SOI diaphragm sensor |
| US5490034A (en) * | 1989-01-13 | 1996-02-06 | Kopin Corporation | SOI actuators and microsensors |
| US5493470A (en) * | 1989-01-13 | 1996-02-20 | Kopin Corporation | SOI diaphragm sensor |
| US5552347A (en) * | 1992-01-16 | 1996-09-03 | Oki Electric Industry Co., Ltd. | Fabrication process for a semiconductor pressure sensor for sensing pressure applied thereto |
| US5296730A (en) * | 1992-01-16 | 1994-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor pressure sensor for sensing pressure applied thereto |
| USRE40561E1 (en) | 1992-04-27 | 2008-11-04 | Denso Corporation | Acceleration sensor and process for the production thereof |
| USRE41047E1 (en) | 1992-04-27 | 2009-12-22 | Denso Corporation | Acceleration sensor and process for the production thereof |
| USRE42083E1 (en) | 1992-04-27 | 2011-02-01 | Denso Corporation | Acceleration sensor and process for the production thereof |
| USRE40347E1 (en) | 1992-04-27 | 2008-06-03 | Denso Corporation | Acceleration sensor and process for the production thereof |
| USRE41213E1 (en) | 1992-04-27 | 2010-04-13 | Denso Corporation | Dynamic amount sensor and process for the production thereof |
| US5445991A (en) * | 1993-12-24 | 1995-08-29 | Kyungdook National University Sensor Technology Research Center | Method for fabricating a semiconductor device using a porous silicon region |
| JP2003530234A (en) * | 2000-04-07 | 2003-10-14 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Micromechanical structure element and corresponding manufacturing method |
| JP2005246601A (en) * | 2004-03-03 | 2005-09-15 | Robert Bosch Gmbh | Micro-machining type component and suitable manufacturing method |
| WO2012020930A2 (en) * | 2010-08-13 | 2012-02-16 | 전자부품연구원 | Capacitive pressure sensor and method for manufacturing same |
| WO2012020930A3 (en) * | 2010-08-13 | 2012-05-03 | 전자부품연구원 | Capacitive pressure sensor and method for manufacturing same |
| KR101215919B1 (en) | 2010-08-13 | 2012-12-27 | 전자부품연구원 | Capacitive type pressure sensor and method for fabricating the same |
| US8754453B2 (en) | 2010-08-13 | 2014-06-17 | Korea Electronics Technology Institute | Capacitive pressure sensor and method for manufacturing same |
| WO2020158156A1 (en) * | 2019-01-31 | 2020-08-06 | オムロン株式会社 | Method for forming detection element and detection device |
| JP2020122747A (en) * | 2019-01-31 | 2020-08-13 | オムロン株式会社 | Detection device |
| CN110146177A (en) * | 2019-05-23 | 2019-08-20 | 北京北方高业科技有限公司 | A kind of preparation method of temperature-detecting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2508070B2 (en) | 1996-06-19 |
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