JP3534034B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device such as an integrated pressure sensor.

[0002]

2. Description of the Related Art Conventionally, JP-A-61-30039 discloses an electrochemical etching method for forming a diaphragm of a diaphragm type silicon pressure sensor. This is done by preparing a silicon substrate consisting of upper and lower two layers having different conductivity types, forming a high-concentration diffusion layer in the inactive region or scribe line region of the silicon substrate to form wiring, and then electrochemically etching the lower conductive layer. The diaphragm is formed by removing the conductive layer (epitaxial layer) on the upper side. In this way, by forming the high-concentration diffusion layer in the inactive region and the scribe line region of the silicon substrate,
A uniform potential can be supplied to the entire silicon substrate (wafer). In this case, in each chip, it plays a role of supplying a potential to a portion (near the thin portion) where the upper conductive layer (epitaxial layer) is etched.

[0003]

However [0007] is to be applied to an integrated pressure sensor having an integrated circuit throughout the chip peripheral area, for forming an integrated circuit in the epitaxial layer, it will not be potential delivery required, electrical There is a problem that chemical etching cannot be performed and the thickness of the thin portion becomes uneven. Therefore, it is necessary to connect the thin portion and the scribe line region to form a wiring that traverses the integrated circuit so that the potential can be distributed. On the other hand, in the same thin portion region, in order to isolate the diffusion resistance, which is a strain gauge formed on the thin portion, from the epitaxial layer,
It is also necessary to connect a wiring for applying a high potential from the integrated circuit to the epitaxial layer. However, when the above-mentioned two wirings are directly connected to the epitaxial layer as they are, during etching, if the etching potential distributed from the scribe line region is applied to the thin-walled region, a current flows to the integrated circuit side through the wiring. May leak, and etching may be stopped from the beginning, or current may leak to the scribe line region side during electrical inspection in a wafer state, and normal measurement may not be performed. Therefore,
An object of the present invention is to provide a semiconductor device having a thin portion and an integrated circuit portion which are formed by electrically controlling etching so that a failure such as a current leak does not occur. To do.

[0004]

According to the present invention, in a semiconductor device having a thin portion and an integrated circuit portion in the same substrate, a first conductivity type first semiconductor layer is formed on the first semiconductor layer. The second conductive type second semiconductor layer, the first conductive type isolation region in the second semiconductor layer, and the first region having the thin portion, and the second conductive layer in the second semiconductor layer. A second region having the integrated circuit portion and separated from the first region by an isolation region
A region and a cathode electrically connected to the first region,
A first diode whose anode is electrically connected to the second region, wherein the thin portion is connected to the first region via the second region and the first diode. The first
A reverse bias is applied to a pn junction formed between the semiconductor layer and the semiconductor layer, and electrochemical etching is performed to remove a part of the first semiconductor layer corresponding to the first region. It is characterized by being a thing.

In a preferred embodiment, the integrated circuit unit has a peripheral circuit, a cathode electrically connected to the first region, and an anode electrically connected to the peripheral circuit. Further, the thin portion may have a reverse bias applied to a pn junction formed between the first region and the first semiconductor layer via the second region and the first diode, and The second diode is formed by removing a part of the first semiconductor layer corresponding to the first region by performing electrochemical etching with a reverse bias applied.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This embodiment is applied to a diaphragm type integrated pressure sensor. Figure 1
12 to 12 show the basic configuration or manufacturing method of the present embodiment. FIG. 1 shows a plan view of a pressure sensor made into a chip. 2 is a sectional view taken along the line AA of FIG. As shown in FIG. 2, this sensor uses a p ^- single-crystal silicon substrate 101 on which an n ^- epitaxial layer 102 is laminated, and as shown in FIG. 3, such a silicon wafer 103 is scribed. A chip is obtained by cutting (dicing) in the region 104.

As shown in FIGS. 1 and 2, a silicon chip 1
A diaphragm portion 106 thinned by electrochemical etching is formed in the central portion of 05, and four strain gauges (p ⁺ diffusion resistance layer) 107 are formed on the surface thereof.
The strain gauges 107 are arranged in the same direction and are folded back a plurality of times to increase the resistance value. These strain gauges 107 are Wheatstone bridge connected.

Further, as shown in FIG. 1, the integrated circuit portion 108 is provided around the diaphragm portion 106 which is a peripheral portion of the chip.
Are formed, and the integrated circuit unit 108 performs signal processing such as amplification of the output signal of the Wheatstone bridge by the strain gauge 107 and temperature compensation. The integrated circuit unit 108 includes the bipolar npn transistor shown in FIG. 4, the base resistor shown in FIG.
And the thin film resistor of FIG. 7 and the like. In the bipolar npn transistor of FIG. 4, an n ⁺ collector region 109, ap ⁺ base region 110, and an n ⁺ emitter region 111 are formed in the n ⁻ epitaxial layer 102. The base resistance of FIG. 5 is n ⁻ epitaxial layer 1
02, the p ⁺ base resistance region 112 is formed and connected by the aluminum wiring 113. The capacitor of FIG.
The structure is such that the iO2 film 114 is sandwiched between a capacitor upper aluminum electrode 115 and a capacitor lower electrode (n ⁺ diffusion layer) 116. The thin film resistor of FIG.
Form a thin film resistor 118 such as CrSi on the
It is connected to the aluminum wiring 120 via a barrier metal 119 such as.

The integrated circuit section 108 is designed to operate with a single power source, and FIG. 1 shows an aluminum wiring pattern for supplying a potential on the surface of the silicon chip 105. That is, the integrated circuit unit 108 includes the isolation high potential aluminum wiring 121 and the isolation low potential aluminum wiring 122.
Is placed and aluminum wiring for isolation high potential 12
1 is directly connected to the power supply line, and the isolation low-potential aluminum wiring 122 is directly connected to the ground line. still,
The rectangular portions 123 and 124 on this wiring pattern are
It is a pad portion for bonding with a wire such as Au or Al.

The integrated pressure sensor of this embodiment (generally,
In the case of Ipolar IC), the elements are isolated from each other.
Therefore, p shown in FIGS.⁺isolation
A region 125 is provided, and an isolator in the chip is provided in this region 125.
Pn connection by connecting the aluminum wiring 122 for low potential
Therefore, the reverse bias is applied. Also, p in FIG.⁺Base
By diffusion of the anti-region 112 and the strain gauge 107 of FIG.
The resistance made is p ⁺In isolation region 125
Multiple units can be placed in the enclosed area (called resistance island).
At this time, it is necessary to further
Aluminum wiring for isolation high potential in the chip on the island
121 is connected. That is, n in FIG. ^-Epitaxia
Ohmic contact n⁺Diffusion layer 126
Is provided, and this n⁺Isolation high voltage to the diffusion layer 126
The aluminum wiring 121 for position is connected. That is, dia
Above the flam section 106 is one resistance island, which is usually
When operating as a product of
⁺Diffusion layer 126 and aluminum wiring for isolation high potential
It is insulated and separated by 121.

The wiring for isolation is usually
It is directly connected to the power supply line and the ground line, but since it is not originally a wiring for passing a large amount of current,
It may be connected via a resistor without being connected to the power supply line or the ground line.

Next, a method of manufacturing the integrated pressure sensor thus constructed will be described with reference to FIGS. As shown in FIG. 8, p ⁻ single crystal silicon substrate (wafer) 101
To prepare. As this silicon substrate (wafer) 101, a crystal axis whose (110) plane or (100) plane is tilted by several degrees (off-angle) is used. Then, the n ⁻ epitaxial layer 102 is formed on the upper surface of the silicon substrate (wafer) 101.

Subsequently, as shown in FIG. 9, a p ⁺ isolation region 125 is formed and each element is isolated by the p ⁺ isolation region 125. further,
A strain gauge (p ⁺ diffusion resistance layer) 107, an ohmic contact n ⁺ diffusion layer 126, and an electrochemical diffusion potential supply n diffusion layer 127 are formed. The electrochemical etching potential supply n ⁺ diffusion layer 127 extends over the chip region and the scribe line region (see FIG. 1).

Similarly, the elements shown in FIGS. 4 to 7 in the integrated circuit portion 108 around the chip are formed between these elements. At this time, the base resistance region 112 of FIG. 5 is simultaneously formed in the base diffusion process of the transistor of FIG.
Further, the capacitor lower electrode (n diffusion layer) 116 of FIG. 6 is simultaneously formed in the transistor emitter diffusion process.
SiO is formed on the silicon surface in these device forming steps.
Two layers 129 are also formed. Furthermore, the thin film resistor 1 of FIG.
18 is formed by a vapor deposition method such as CrSi or TiW or a sputtering method.

Then, as shown in FIG. 10, the isolation high-potential aluminum wiring 12 is formed on the SiO 2 layer 129.
1 and the isolation low potential aluminum wiring 122 is formed. Further, on the scribe line region, an aluminum wiring 128 for supplying an electrochemical etching potential and another aluminum wiring are simultaneously formed. At this time, the electrochemical etching potential supply aluminum wiring 128 and the isolation high potential aluminum wiring 121 in the chip are electrically connected via the electrochemical etching potential supply n ⁺ diffusion layer 127. Thus, n ⁺ for supplying the electrochemical etching potential
By electrically connecting using the diffusion layer 127, it is possible to pass the aluminum wiring 122 on the n ⁺ diffusion layer 127 for supplying the electrochemical etching potential. Next, SiO
The passivation film 130 made of a 2 film or a SiNx film is used as a C
It is formed by a VD method, a sputtering method, or the like. next,
As shown in FIG. 11, the SiNx film 131 is formed on the back surface of the p ⁻ -type single crystal silicon substrate (wafer) 101, and predetermined patterning is performed by photoetching.
Furthermore, a silicon substrate (wafer) 10 is formed with a KOH aqueous solution or the like.
A predetermined area of 1 is electrochemically etched. At this time, a voltage is applied to the aluminum wiring 128 for supplying the electrochemical etching potential to supply the n ⁺ diffusion layer 127 for supplying the electrochemical etching potential, the wiring 121 for isolation high potential, and the n ⁺ diffusion layer for ohmic contact from the aluminum wiring 128. A reverse bias is applied to the pn junction of the silicon substrate (wafer) 101 through 126. Then, after the silicon substrate (wafer) 101 is etched to near the pn junction interface, the etching is stopped. This stop position is defined by a depletion layer extending from the pn junction surface to the substrate (p) side. At this time, each chip is passed through the electrochemical etching potential supply aluminum wiring 128, the electrochemical etching potential supply n ⁺ diffusion layer 127, and the isolation high potential wiring 121 on the scribe lines running vertically and horizontally on the silicon substrate (wafer) 101. Since a potential is supplied to the diaphragm portion 106 to be etched, a uniform potential can be obtained in each chip on the wafer surface, and the etching stop property in each chip becomes good. When the diaphragm portion 106 of the pressure sensor is formed in this manner, the diaphragm thickness is substantially determined by the formation accuracy of the n ⁻ epitaxial layer 102 and the depletion layer width, and thus the diaphragm thickness with higher accuracy is obtained as compared with the diaphragm forming method that does not use this method. It becomes possible to control. Finally, as shown in FIG. 2, dicing is performed on the scribe line, and the chips are cut into a predetermined size. At this time, the electrochemical etching potential supply aluminum wiring 128 is cut by dicing.

As a result, the integrated pressure sensor shown in FIGS. 1 and 2 is manufactured. As described above, in this embodiment, the n ⁻ epitaxial layer 102 as a semiconductor layer is formed on the p ⁻ single crystal silicon substrate (wafer) 101 (first step), and n ⁻
The integrated circuit portion 108 having the isolation high-potential aluminum wiring 121 is formed on the epitaxial layer 102 (second step). Further, an aluminum wiring 128 for supplying electrochemical etching potential is formed in the scribe line region in the n ⁻ epitaxial layer 102, and the aluminum wiring 128 and the aluminum wiring 1 for isolation high potential are formed.
21 (third step), and p ⁻ single crystal silicon substrate (wafer) 101 by electrochemical etching using aluminum wiring 128 for supplying electrochemical etching potential.
Then, a predetermined region is removed to form a diaphragm portion 106 (thin portion) of the ^n- epitaxial layer 102 (fourth step). Finally, the scribe line region was cut into chips (fifth step) to manufacture an integrated pressure sensor. Therefore, the isolation high-potential aluminum wiring 121 originally used by the integrated circuit unit 108 is also used during the electrochemical etching, so that an extra area, that is, an area through which a wide diffusion layer for exclusive use, a metal wiring, or the like is passed is used. It is possible to improve the etching stop property of each chip.

Further, the isolation high potential aluminum wiring 121 and the electrochemical etching potential supply aluminum wiring 128 are used.
Preparative Having electrically connected through electrochemical etching potential supplying n ⁺ diffusion layer 127 can be passed through the aluminum wiring 122 on the electrochemical etching potential supplying n ⁺ diffusion layer 127.

In the above embodiment, the integrated pressure sensor has been described as an example, but it can also be applied to a device having an integrated circuit portion such as an integrated acceleration sensor and manufactured by electrochemical etching as a micromachining technique. Is.

In addition, the integrated circuit section 108 is a bipolar IC.
Although described, other MOSICs may be used. Furthermore
In addition, as shown in FIG.
P ⁺Single crystal silicon substrate 101 and n^-Epitaxial layer
Between n and 102⁺A buried layer 132 may be provided.

Further, the conductivity type may be reversed from that of the above embodiment. Further, the isolation high potential aluminum wiring 121 and the electrochemical etching potential supply aluminum wiring 12
8 and n ⁺ diffusion layer 127 for supplying an electrochemical etching potential
You may connect directly without going through. The wiring is not limited to aluminum wiring. In particular, a diffusion layer may be formed on the scribe line.

Further, the semiconductor layer may be, in addition to the epitaxial layer 102 formed by epitaxial growth, a semiconductor layer formed by another method such as direct wafer bonding.

Next, the addition of the diode, which is a feature of this embodiment, will be described. As shown in FIG. 13, a peripheral circuit (temperature compensation
For the amplifier circuit 133, the peripheral circuit 133 and the p ⁺ isolation region 125 are connected by the isolation low potential aluminum wiring 122, and the peripheral circuit 133 and the isolation high potential aluminum wiring 121 are connected. Then, the leakage current prevention diode 134 may be arranged in the middle of the isolation high-potential aluminum wiring 121. That is, at the time of electrochemical etching, a reverse bias is applied to the pn junction between the n ⁻ epitaxial layer 102 of the diaphragm portion 106 and the p ⁻ single crystal silicon substrate 101, and a current flows until the etching proceeds near the pn junction portion. You need to keep it from flowing. The etching stops when a current flows and the p ⁻ single crystal silicon substrate 101 is anodized. If the peripheral circuit 133
When a current leaks to the p ⁻ single crystal silicon substrate 101 through the p ⁺ isolation region 125, the etching is stopped from the point before reaching the pn junction. However, this is prevented by the leakage current prevention diode 134. Particularly, when the impedance of the peripheral circuit 133 is small or when the peripheral circuit 133 and the isolation high potential aluminum wiring 121 are connected, the leakage current prevention diode 134 is necessary. Further, in FIG. 13, a leakage current prevention diode 135 is arranged in the middle of the isolation high potential aluminum wiring 121. Since the isolation high potential is applied to the isolation high potential aluminum wiring 121, the high potential is applied not only to the ohmic contact n ⁺ diffusion layer 126 but also to the electrochemical etching potential supply n ⁺ diffusion layer 127. Is applied. Then, the pn junction exposed portion D of the chip end surface
Is about to leak. However, the leakage current prevention diode 135 prevents the leakage. Further, the leakage current preventing diode 135 can prevent all chips from being short-circuited via the electrochemical etching potential supply n ⁺ diffusion layer 127 when performing the characteristic test of each chip in a wafer state. . In addition, as shown in FIG. 14 with respect to FIG. 13, the peripheral circuit 133 and p ⁺
Although the isolation region 125 is connected by the isolation low potential aluminum wiring 122, the peripheral circuit 133 and the isolation high potential aluminum wiring 121 may not be connected. When FIG. 14 can be used, n ⁻
Strain gauge (p ⁺ diffusion resistance layer) on the epitaxial layer 102
When forming 107, it was necessary in FIG. 13 to apply a high potential to the n ⁺ diffusion layer 126 for ohmic contact in order to perform resistance separation. However, if each strain gauge (p ⁺ diffusion resistance layer) 107 is in a separate n ⁻ epitaxial layer 102 (island), this high potential application is not necessary and the configuration of FIG. 14 may be used. The function of the leakage current prevention diode 135 in FIG.
This is the same as that described in 3.

[Brief description of drawings]

FIG. 1 is a plan view of an integrated pressure sensor of an embodiment.

FIG. 2 is a view showing a cross section taken along the line AA of FIG.

FIG. 3 is a plan view of a wafer.

FIG. 4 is a sectional view of an element.

FIG. 5 is a sectional view of an element.

FIG. 6 is a sectional view of an element.

FIG. 7 is a sectional view of an element.

FIG. 8 is a diagram showing a manufacturing process of the sensor.

FIG. 9 is a diagram showing a manufacturing process of the sensor.

FIG. 10 is a diagram showing a manufacturing process of the sensor.

FIG. 11 is a diagram showing a manufacturing process of the sensor.

FIG. 12 is a cross-sectional view showing another example.

FIG. 13 is a cross-sectional view showing the present invention.

FIG. 14 is a sectional view showing the present invention.

[Explanation of symbols]

101 ... p ^- as a single-crystal silicon substrate 102 ... semiconductor layer n ^- epitaxial layer 106 ... diaphragm (the thin portion) 108 ... integrated circuit portion 121 ... Aluminum for isolation high-potential wiring 127 ... electrochemical etching potential supplying n ⁺ Diffusion layer 128 ... Electrochemical etching potential supply aluminum wiring 134 ... Leakage current prevention diode 135 ... Leakage current prevention diode

Claims (4)

(57) [Claims] 1. A semiconductor device having a thin portion and an integrated circuit portion on the same substrate, wherein a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer. A second semiconductor layer, a first region in the second semiconductor layer that is partitioned by a first conductivity type isolation region and has the thin portion, and a first region in the second semiconductor layer that is formed by the isolation region. Separated from the integrated circuit part
A second region that, the cathode is electrically connected to the first region, and a first diode whose anode is electrically connected to the second region, wherein the thin portion, the second region and A reverse bias is applied to the pn junction formed between the first region and the first semiconductor layer via the first diode, and electrochemical etching is performed to thereby cause the first region to reach the pn junction. A semiconductor device formed by removing a part of the corresponding first semiconductor layer. Wherein said integrated circuit portion includes a peripheral circuit, the cathode is electrically connected to the first region, further comprising a second diode whose anode is electrically connected to the peripheral circuit, wherein A reverse bias is applied to the thin portion through the second region and the first diode to a pn junction formed between the first region and the first semiconductor layer, and the second diode is provided. The semiconductor according to claim 1, wherein a part of the first semiconductor layer corresponding to the first region is removed by performing electrochemical etching in a state in which a reverse bias is applied to the semiconductor. apparatus. 3. The integrated circuit portion is electrically connected to the first region.
Isolation wiring for high potential connected to
A low potential gate electrically connected to the isolation region.
Isolation wiring, the first region and the eye
An inverse bar is formed in the pn junction formed between the isolation region and
The half according to claim 1, wherein the bias is applied.
Conductor device. 4. The integrated circuit portion has a peripheral circuit , a cathode is electrically connected to the first region and an anode is electrically connected to the peripheral circuit in the middle of a high-potential isolation wiring. by further comprising a second diode, the thin portion, the second region and through the first diode, conversely configured pn junction between said first semiconductor layer and the first region Formed by removing a part of the first semiconductor layer corresponding to the first region by performing electrochemical etching with a bias applied and a reverse bias applied to the second diode. The semiconductor device according to claim 3, which has been manufactured.