JP3503146B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as an integrated pressure sensor.

[0002]

2. Description of the Related Art Conventionally, JP-A-61-30039 discloses an electrochemical etching method for forming a diaphragm of a diaphragm type silicon pressure sensor. This is done by preparing a silicon substrate consisting of upper and lower two layers having different conductivity types, forming a high-concentration diffusion layer in the inactive region or scribe line region of the silicon substrate to form wiring, and then electrochemically etching the lower conductive layer. The diaphragm is formed by removing the conductive layer (epitaxial layer) on the upper side. In this way, by forming the high-concentration diffusion layer in the inactive region and the scribe line region of the silicon substrate,
A uniform potential can be supplied to the entire silicon substrate (wafer). In this case, in each chip, it plays a role of supplying a potential to a portion (near the thin portion) where the upper conductive layer (epitaxial layer) is etched.

[0003]

However, when it is applied to an integrated pressure sensor having an integrated circuit in the entire peripheral area of the chip, the integrated circuit is formed in the epitaxial layer, so that the integrated circuit portion is required for electrochemical etching. The potential supply is obstructed, and in this case, there arises a problem in the uniformity of the thickness of the thin portion in the chip. Therefore, it is conceivable to provide a dedicated wiring for electrochemical etching in the chip, but in this case, an extra area is required in the chip.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which can be thinned while using almost no extra area.

[0005]

The invention according to claim 1 is a method for manufacturing a semiconductor device having a thin portion and an integrated circuit portion having wiring in the same substrate,
A first step of forming or directly joining a second-conductivity-type semiconductor layer on a first-conductivity-type single-crystal semiconductor substrate; and forming an integrated circuit section having isolation wiring in the semiconductor layer , wherein forming a wiring in a scribe line region of the semiconductor layer, and a second step of electrically connecting the wiring for isolation of the integrated circuit portion and its wiring, a voltage to the wiring of the scribe line region
Apply the wiring for isolation of the integrated circuit section.
Through the single crystal semiconductor substrate and the semiconductor layer.
A third step of removing a predetermined region of the single crystal semiconductor substrate to form a thin portion by the semiconductor layer by performing an electrochemical etching so that a reverse bias is applied to the pn junction, and cutting the scribe line region. A semiconductor device manufacturing method including a fourth step of forming into chips is made into a gist. The invention according to claim 2 is the same.
The board has a thin-walled portion and an integrated circuit portion having wiring.
A method for manufacturing a semiconductor device, comprising:
A second conductivity type semiconductor layer on a single crystal semiconductor substrate of the second type.
Forming or directly joining the semiconductor layer and the first step.
Form an integrated circuit part with wiring for isolation
Together with the scribe line region in the semiconductor layer
Wiring on the integrated circuit section and the wiring of the integrated circuit section.
Second step of electrically connecting with the wiring for isolation
And applying a voltage to the wiring in the scribe line area.
Through the wiring for isolation of the integrated circuit part
Pn composed of a single crystal semiconductor substrate and the semiconductor layer
Electrochemical etch with reverse bias on junction
By conducting a predetermined region of the single crystal semiconductor substrate
For removing a thin part by removing the semiconductor layer
A method of manufacturing a semiconductor device having
Of.

[0006]

According to the first aspect of the present invention , the second conductivity type semiconductor layer is formed or the direct junction is laminated on the first conductivity type single crystal semiconductor substrate in the first step . In the second step, the integrated circuit portion having the wiring for isolation is formed in the semiconductor layer, the wiring is formed in the scribe line region in the semiconductor layer , and the wiring and the wiring for isolation of the integrated circuit portion are formed. And are electrically connected. Further, in the third step , a voltage is applied to the wiring in the scribe line region to isolate the integrated circuit part from the isolation.
The single crystal semiconductor substrate and the semiconductor layer
By performing electrochemical etching so that a reverse bias is applied to the formed pn junction, a predetermined region of the single crystal semiconductor substrate is removed and a thin portion made of a semiconductor layer is formed. At this time, since the wiring originally used by the integrated circuit section is also used during the electrochemical etching, the extra area,
That is, the etching stop property is improved without using a dedicated wiring region. Finally, the scribe line region is cut into chips by the fourth step. Claim
According to the invention of Item 2, the first conductivity type is obtained by the first step.
Second conductivity type semiconductor layer is formed on the single crystal semiconductor substrate of
Or a direct bond is laminated. Semiconductor layer by the second step
The integrated circuit part with isolation wiring is
Scribe line in the semiconductor layer
Wiring is formed in the area, and the wiring and the integrated circuit
The wiring for isolation is electrically connected. It
In addition, the wiring in the scribe line area is electrically charged by the third step.
Apply pressure to the wiring for isolation of the integrated circuit
Through a single crystal semiconductor substrate and a semiconductor layer
Electrochemical etch with reverse bias on junction
Removal of the specified area of the single crystal semiconductor substrate
Thus, a thin portion made of the semiconductor layer is formed. At this time,
Electrochemical etching of the wiring originally used by the integrated circuit section
Since it is also used during programming, it is an extra area, that is, dedicated
The etching stop property can be achieved without using the wiring area of
It will be good.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will now be described with reference to the drawings.
Follow the instructions below. This embodiment is a diaphragm type integration.
It is applied to a pressure sensor. Chip in Figure 1
The top view of the done pressure sensor is shown. In addition, in FIG.
The AA sectional view is shown. This sensor, as shown in FIG.
^-N on the single crystal silicon substrate 101 ^-Epitaxial layer
Using a stack of 102 and as shown in FIG.
In addition, the silicon wafer 103 is scribed and dried.
Chip by cutting (dicing) in the area of
It has been transformed.

As shown in FIGS. 1 and 2, a silicon chip 1
A diaphragm portion 106 thinned by electrochemical etching is formed in the central portion of 05, and four strain gauges (p ⁺ diffusion resistance layer) 107 are formed on the surface thereof.
The strain gauges 107 are arranged in the same direction and are folded back a plurality of times to increase the resistance value. These strain gauges 107 are Wheatstone bridge connected.

Further, as shown in FIG. 1, the integrated circuit portion 108 is provided around the diaphragm portion 106 which is a peripheral portion of the chip.
Are formed, and the integrated circuit unit 108 performs signal processing such as amplification of the output signal of the Wheatstone bridge by the strain gauge 107 and temperature compensation. The integrated circuit unit 108 includes the bipolar npn transistor shown in FIG. 4, the base resistor shown in FIG.
And the thin film resistor of FIG. 7 and the like.

The bipolar npn transistor of FIG.
In the n ⁻ epitaxial layer 102, the n ⁺ collector region 109, the p ⁺ base region 110, the n ⁺ emitter region 11
1 is formed. The base resistance shown in FIG. 5 is obtained by forming ap ⁺ base resistance region 112 in the n ⁻ epitaxial layer 102 and connecting it by an aluminum wiring 113. In the capacitor shown in FIG. 6, a SiO ₂ film 114 is used as a capacitor upper aluminum electrode 115 and a capacitor lower electrode (n ⁺ diffusion layer) 11
It has a structure sandwiched between 6. The thin film resistor in Figure 7 is
A thin film resistor 118 made of CrSi or the like is formed on the SiO ₂ film 117 and is connected to an aluminum wiring 120 via a barrier metal 119 such as TiW.

Further, the integrated circuit section 108 is designed to operate with a single power source, and FIG. 1 shows an aluminum wiring pattern for supplying a potential on the surface of the silicon chip 105. That is, the integrated circuit unit 108 includes the isolation high potential aluminum wiring 121 and the isolation low potential aluminum wiring 122.
Is placed and aluminum wiring for isolation high potential 12
1 is directly connected to the power supply line, and the isolation low-potential aluminum wiring 122 is directly connected to the ground line. still,
The rectangular portions 123 and 124 on this wiring pattern are
It is a pad portion for bonding with a wire such as Au or Al.

In the integrated pressure sensor of the present embodiment (generally the same for a bipolar IC), a p ⁺ isolation region 125 shown in FIGS. 2, 4, 5 and 6 is provided in order to insulate elements from each other. An isolation low potential aluminum wiring 122 in the chip is connected to 125, and a reverse bias is applied to the pn junction. Further, a plurality of resistors formed by diffusion such as the p ⁺ base resistance region 112 of FIG. 5 and the strain gauge 107 of FIG. 2 may be arranged in a region surrounded by the p ⁺ isolation region 125 (referred to as a resistance island). At this time, in order to insulate the resistors from each other, the isolation high-potential aluminum wiring 121 in the chip is further connected to the resistor islands. I.e., n in Figure 2 ^- for ohmic contact with the epitaxial layer 102 n ⁺ diffusion layer 126
And the isolation high potential aluminum wiring 121 is connected to the n ⁺ diffusion layer 126. In other words, there is one resistance island on the diaphragm portion 106, and when operating as a normal product, n for ohmic contact is used.
It is insulated and separated by the ⁺ diffusion layer 126 and the isolation high potential aluminum wiring 121.

The wiring for isolation is usually
It is directly connected to the power supply line and the ground line, but since it is not originally a wiring for passing a large amount of current,
It may be connected via a resistor without being connected to the power supply line or the ground line.

Next, a method of manufacturing the integrated pressure sensor thus configured will be described with reference to FIGS. As shown in FIG. 8, p ⁻ single crystal silicon substrate (wafer) 101
To prepare. As this silicon substrate (wafer) 101, a crystal axis whose (110) plane or (100) plane is tilted by several degrees (off-angle) is used. Then, the n ⁻ epitaxial layer 102 is formed on the upper surface of the silicon substrate (wafer) 101.

Subsequently, as shown in FIG. 9, a p ⁺ isolation region 125 is formed and each element is insulated and isolated by the p ⁺ isolation region 125. further,
A strain gauge (p ⁺ diffusion resistance layer) 107, an ohmic contact n ⁺ diffusion layer 126, and an electrochemical etching potential supply n ⁺ diffusion layer 127 are formed. The electrochemical etching potential supply n ⁺ diffusion layer 127 extends over the chip region and the scribe line region (see FIG. 1).

Similarly, the elements shown in FIGS. 4 to 7 in the integrated circuit portion 108 around the chip are formed between these elements. At this time, the base resistance region 112 of FIG. 5 is simultaneously formed in the base diffusion process of the transistor of FIG.
Further, the capacitor lower electrode (n ⁺ diffusion layer) 116 of FIG. 6 is simultaneously formed in the transistor emitter diffusion process. During these element formation steps, S
An iO ₂ layer 129 is also formed. Further, the thin film resistor 118 of FIG. 7 is formed by a vapor deposition method such as CrSi or TiW or a sputtering method.

Then, as shown in FIG. 10, the isolation high potential aluminum wiring 12 is formed on the SiO ₂ layer 129.
1 and the isolation low potential aluminum wiring 122 is formed. Further, on the scribe line region, an aluminum wiring 128 for supplying an electrochemical etching potential and another aluminum wiring are simultaneously formed. At this time, the electrochemical etching potential supply aluminum wiring 128 and the isolation high potential aluminum wiring 121 in the chip are electrically connected via the electrochemical etching potential supply n ⁺ diffusion layer 127. Thus, n ⁺ for supplying the electrochemical etching potential
By electrically connecting using the diffusion layer 127, it is possible to pass the aluminum wiring 122 on the n ⁺ diffusion layer 127 for supplying the electrochemical etching potential.

Subsequently, a passivation film 130 made of a SiO ₂ film or a SiN _x film is formed by the CVD method, the sputtering method or the like. Next, as shown in FIG.
^- Si on the rear surface of the type single crystal silicon substrate (wafer) 101
The N _x film 131 is formed and predetermined patterning is performed by photoetching.

Further, a predetermined region of the silicon substrate (wafer) 101 is electrochemically etched with a KOH aqueous solution or the like. At this time, a voltage is applied to the electrochemical etching potential supply aluminum wiring 128 to supply the electrochemical etching potential supply n ⁺ diffusion layer 127, the isolation high potential wiring 121, and ohmic contact n.
⁺ Silicon substrate (wafer) 101 through diffusion layer 126
A reverse bias is applied to the pn junction of. Then, after the silicon substrate (wafer) 101 is etched to near the pn junction interface, the etching is stopped.
This stop position is defined by a depletion layer extending from the pn junction surface to the substrate (p) side. At this time, each chip is passed through the electrochemical etching potential supply aluminum wiring 128, the electrochemical etching potential supply n ⁺ diffusion layer 127, and the isolation high potential wiring 121 on the scribe lines running vertically and horizontally on the silicon substrate (wafer) 101. Since a potential is supplied to the diaphragm portion 106 to be etched, a uniform potential can be obtained in each chip on the wafer surface, and the etching stop property in each chip becomes good.

When the diaphragm portion 106 of the pressure sensor is formed in this way, the diaphragm thickness is substantially determined by the formation accuracy of the n ⁻ epitaxial layer 102 and the depletion layer width.
As compared with the diaphragm forming method that does not use this method, it is possible to control the diaphragm thickness with high accuracy.

Finally, as shown in FIG. 2, the scribe line is diced and cut into chips of a predetermined size. At this time, the electrochemical etching potential supply aluminum wiring 128 is cut by dicing.

As a result, the integrated pressure sensor shown in FIGS. 1 and 2 is manufactured. As described above, in this embodiment, the n ⁻ epitaxial layer 102 as a semiconductor layer is formed on the p ⁻ single crystal silicon substrate (wafer) 101 (first step), and n
^- forming an integrated circuit portion 108 in the epitaxial layer 102 has an isolation higher potential for aluminum wiring 121
At the same time, an aluminum wire 128 for supplying electrochemical etching potential is formed in the scribe line region in the n ⁻ epitaxial layer 102 , and the aluminum wire 128 and the aluminum wire for isolation high potential 121 are electrically connected ( second). Process), p ⁻ by electrochemical etching using the aluminum wiring 128 for supplying electrochemical etching potential.
A predetermined region of the single crystal silicon substrate (wafer) 101 is removed to form a diaphragm portion 106 (thin portion) of the n ⁻ epitaxial layer 102 ( third step). Finally, the scribe line region was cut into chips ( fourth step) to manufacture an integrated pressure sensor. Therefore, the isolation high-potential aluminum wiring 121 originally used by the integrated circuit unit 108 is also used during the electrochemical etching, so that an extra area, that is, an area through which a wide diffusion layer for exclusive use, a metal wiring, or the like is passed is used. Without
The etching stop property of each chip can be improved.

Further, the isolation high potential aluminum wiring 121 and the electrochemical etching potential supply aluminum wiring 128.
Preparative Having electrically connected through electrochemical etching potential supplying n ⁺ diffusion layer 127 can be passed through the aluminum wiring 122 on the electrochemical etching potential supplying n ⁺ diffusion layer 127.

The present invention is not limited to the above-described embodiment. For example, the integrated pressure sensor has been described as an example in the above embodiment, but the integrated acceleration sensor or the like has an integrated circuit portion and a micro. It is also applicable to devices manufactured by electrochemical etching as a machining technique.

Although the integrated circuit section 108 has been described as a bipolar IC, it may be constituted by a MOSIC. Further, as shown in FIG. 12, an n ⁺ buried layer 132 may be provided between the p ⁻ single crystal silicon substrate 101 and the n ⁻ epitaxial layer 102 in the diaphragm portion 106.

Further, the conductivity type may be reversed from that of the above embodiment. Further, the isolation high potential aluminum wiring 121 and the electrochemical etching potential supply aluminum wiring 12
8 and n ⁺ diffusion layer 127 for supplying an electrochemical etching potential
You may connect directly without going through. The wiring is not limited to aluminum wiring. In particular, a diffusion layer may be formed on the scribe line.

Further, the semiconductor layer may be, in addition to the epitaxial layer 102 formed by epitaxial growth, a semiconductor layer formed by another method such as direct wafer bonding.

Further, as shown in FIG. 13, the peripheral circuit 133 and the p ⁺ isolation region 125 are isolated from the peripheral circuit (temperature compensation / amplification circuit) 133 which is the integrated circuit section 108 in the same chip. The low potential aluminum wiring 122 is connected, and the peripheral circuit 133 and the isolation high potential aluminum wiring 121 are connected. Then, the leakage current prevention diode 134 may be arranged in the middle of the isolation high-potential aluminum wiring 121. That is, during the electrochemical etching, the n ⁻ epitaxial layer 102 and p ⁻ of the diaphragm portion 106 are
It is necessary to apply a reverse bias to the pn junction with the single crystal silicon substrate 101 so that no current flows until the etching proceeds to the vicinity of the pn junction. The etching stops when a current flows and the p ⁻ single crystal silicon substrate 101 is anodized. If the peripheral circuit 13
When a current leaks to the p ⁻ single crystal silicon substrate 101 through the 3 and p ⁺ isolation regions 125, the etching is stopped from the point before reaching the pn junction. However, this is prevented by the leakage current prevention diode 134. Particularly, when the impedance of the peripheral circuit 133 is small or when the peripheral circuit 133 and the isolation high potential aluminum wiring 121 are connected, the leakage current prevention diode 134 is necessary.

Further, in FIG. 13, a leakage current preventing diode 135 is arranged in the middle of the isolation high potential aluminum wiring 121. This is because the isolation high potential is aluminum wiring 121 for isolation high potential.
Therefore, the high potential is applied not only to the ohmic contact n ⁺ diffusion layer 126 but also to the electrochemical etching potential supply n ⁺ diffusion layer 127. Then, a leak is about to occur in the pn junction exposed portion D on the chip end surface. However, the leakage current prevention diode 135
This prevents the leak. Further, the leakage current preventing diode 135 can prevent all chips from being short-circuited via the electrochemical etching potential supply n ⁺ diffusion layer 127 when performing the characteristic test of each chip in a wafer state. .

Further, as shown in FIG. 14 with respect to FIG. 13, the peripheral circuit 133 and the p ⁺ isolation region 125 are connected by the isolation low potential aluminum wiring 122, but the peripheral circuit 133 and the isolation high potential are connected. It may not be connected to the aluminum wiring 121. As a case where FIG. 14 can be used, when forming the strain gauge (p ⁺ diffusion resistance layer) 107 in the n ⁻ epitaxial layer 102, the n ⁺ diffusion layer 12 for ohmic contact is formed to perform resistance separation.
It was necessary to apply a high potential to No. 6 in FIG. However, each strain gauge (p ⁺ diffusion resistance layer) 10
If 7 are in different n ⁻ epitaxial layers 102 (islands), the application of this high potential is unnecessary, and the configuration of FIG. 14 is also acceptable. The function of the leakage current prevention diode 135 in FIG. 14 is the same as that described in FIG.

[0031]

As described above in detail, according to the present invention,
It has an excellent effect that it can be thinned without increasing the size of the chip.

[Brief description of drawings]

FIG. 1 is a plan view of an integrated pressure sensor according to an embodiment.

FIG. 2 is a view showing a cross section taken along the line AA of FIG.

FIG. 3 is a plan view of a wafer.

FIG. 4 is a sectional view of an element.

FIG. 5 is a sectional view of an element.

FIG. 6 is a sectional view of an element.

FIG. 7 is a sectional view of an element.

FIG. 8 is a diagram showing a manufacturing process of the sensor.

FIG. 9 is a diagram showing a manufacturing process of the sensor.

FIG. 10 is a diagram showing a manufacturing process of the sensor.

FIG. 11 is a diagram showing a manufacturing process of the sensor.

FIG. 12 is a cross-sectional view showing another example.

FIG. 13 is a sectional view showing another example.

FIG. 14 is a cross-sectional view showing another example.

[Explanation of symbols]

101 p ^- single crystal silicon substrate 102 n ^- epitaxial layer as semiconductor layer 106 diaphragm portion (thin portion) 108 integrated circuit portion 121 isolation high potential aluminum wiring 127 electrochemical etching potential supply n ⁺ diffusion layer 128 electrochemical etching Aluminum wiring for potential supply

Claims (3)

(57) [Claims] 1. A method for manufacturing a semiconductor device having a thin portion and an integrated circuit portion having wiring in the same substrate, the method comprising: forming a second conductive material on a single crystal semiconductor substrate of a first conductive type. a first step of forming or joining directly type semiconductor layer, the semiconductor layer, thereby forming an integrated circuit portion having a wiring for isolation, to form wiring in a scribe line region in the semiconductor layer, and, A second step of electrically connecting the wiring to the wiring for isolation of the integrated circuit section, and applying a voltage to the wiring in the scribe line region
Through the wiring for isolation of the integrated circuit,
A pn junction composed of a crystalline semiconductor substrate and the semiconductor layer
Electrochemical etching with a reverse bias applied to
By performing, a third step of removing a predetermined region of the single crystal semiconductor substrate to form a thin portion by the semiconductor layer, and a fourth step of cutting the scribe line region into chips. And a method for manufacturing a semiconductor device. 2. A thin portion and wiring are provided in the same substrate.
Method for manufacturing a semiconductor device having an integrated circuit part
And a second conductivity type semiconductor on a single conductivity type single crystal semiconductor substrate.
A first step of forming or directly joining a body layer, and a step of collecting wiring for isolation in the semiconductor layer.
Forming the integrated circuit part and
Wiring is formed in the clevis line area and
Electrically connect the wiring for isolation of the integrated circuit section
The second step of connecting to the wiring, and applying a voltage to the wiring in the scribe line region
Through the wiring for isolation of the integrated circuit,
A pn junction composed of a crystalline semiconductor substrate and the semiconductor layer
Electrochemical etching with a reverse bias applied to
By doing so, a predetermined region of the single crystal semiconductor substrate is removed.
And a third step of forming a thin portion of the semiconductor layer
A method of manufacturing a semiconductor device, comprising: 3. A scribe line in the second step
Area wiring and wiring for integrated circuit isolation
The electrical connection of the through the diffusion layer formed in the semiconductor layer
The semiconductor device according to claim 1 or 2, which is performed.
Production method.