JPS63237481A - Manufacture of capacitance type pressure sensor - Google Patents

Abstract

PURPOSE:To make the thickness of a diaphragm small to increase sensitivity, and make the thickness adjustable, forming one electrode in a recessed part formed on the main surface of a first substrate, forming the other electrode on the main surface of a second substrate, and joining the main surface of the first substrate and that of the second substrate. CONSTITUTION:A recessed part 2 is formed on a substrate 1, by an anisotropic etching using a silicon oxide film formed on a specified region of the single crystal silicon substrate 1 as a mask, and a silicon oxide film 3 is formed. Metal 4 is vapor-deposited and is eliminated by an etching while a specified region is left. A BPSG film 5 formed. On the main surface of a second single crystal substrate 6, a silicon oxide film 7 is formed, and a metal film 8 is vapor- deposited thereon, which is eliminated by an etching while a specified region is lift. On the main surface of a substrate 1, a BPSG film 9 is so arranged that the upper and the lower patterns lap with each other in a prescribed manner, and temporarily fixed. The BPSG films 5 and 9 are fused by heating under a specified pressure, and the substrates 1 and 6 are bonded. Silicon 6 is eliminated by applying anisotropic etching liquid. By making the films 5, 7 and 9 thin, a diaphragm can be formed with extremely thin thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a capacitive pressure sensor that extracts a change in pressure value as a change in capacitance.

(Conventional technology and problems) In conventional capacitive pressure sensors, the diaphragm is formed by anisotropic etching of a silicon wafer, and in order to increase pressure sensitivity it is necessary to reduce the thickness of the diaphragm. In order to reduce the thickness, strict control of etching rate and etching time was required.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a capacitive pressure sensor that can reduce the thickness of the diaphragm, increase sensitivity, and adjust the thickness of the diaphragm. It is in.

(Means for Solving the Problems) The present invention has been made to achieve the above object, and the first invention includes a step of forming a recess on the main surface of a first substrate, and a step of forming a recess on the main surface of the first substrate. , forming one electrode of the capacitor in the recess, forming an insulating layer on the main surface of the second substrate, and subsequently forming a metal layer that will become the other electrode of the capacitor on the insulating layer. a step of joining the main surface of the first substrate and the second main surface,
a capacitive type comprising the step of forming the insulating layer serving as a diaphragm and the other electrode of the capacitor on the upper side of the main surface of the first substrate by etching from the other main surface side of the second substrate. The gist is a method for manufacturing a pressure sensor.

Further, the second invention includes a step of forming a recess on the main surface of the first substrate, a step of forming one electrode of the capacitor in the recess, and a step of forming an insulating layer on the main surface of the second substrate. the main surface of the first substrate, the step of bonding the main surface of the first substrate and the second main surface, and etching from the other main surface side of the second substrate. forming the insulating layer to serve as a diaphragm on the upper side of the surface;
The gist of the present invention is a method of manufacturing a capacitive pressure sensor, which includes a step of forming the other electrode of a capacitor on the diaphragm.

(First Embodiment) A first embodiment embodying the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(1) are cross-sectional views for explaining the same.

A silicon oxide film (Si02) is formed in a predetermined region of the first single-crystal silicon substrate 1 with the (100) plane, and an anisotropic etching solution such as potassium hydroxide (KOH) is applied using this silicon oxide film as a mask. A recess 2 is formed in the first single-crystal silicon substrate 1 by etching, and then the silicon oxide film is removed (FIG. 1 (a)).The substrate used here has a (110) crystal plane. Alternatively, it may be made of Pyrex glass, sapphire, or the like with recesses formed therein.

Subsequently, as shown in FIG. 2B, the first single-crystal silicon substrate 1 is oxidized to form a silicon oxide film 3 on the first single-crystal silicon substrate 1. This step is not necessary if the substrate is an insulating material such as Pyrex glass. Subsequently, as shown in the same figure (C), a metal 4 such as tungsten (W) is deposited and removed by etching leaving a predetermined area.This metal has a melting point higher than the temperature at which the substrate will be bonded later. It is necessary.

Then, as shown in the same figure (d), BPSGIII15 was deposited on the first single crystal silicon substrate 1 on which gold@Im4 was formed.
form.

On the other hand, as shown in FIG. 3E, a silicon oxide film 7 is formed on the main surface of a second single crystal silicon substrate 6 having a (100) or (110) crystal plane.

Then, as shown in FIG. 2F, a metal 8 such as tungsten is deposited thereon and removed by etching, leaving a predetermined area. Like the metal layer 4 formed on the first single-crystal silicon substrate 1, this metal also needs to have a melting point higher than the humidity at the time of bonding the substrates, which will be performed later.

Subsequently, as shown in FIG. 6(g), BPS is deposited on the second single crystal silicon substrate 6 on which the metal layer 8 is formed in this predetermined region.
A G film 9 is formed.

Then, as shown in FIG. 6H, the second single crystal silicon substrate 1 is aligned on the main surface of the first single crystal silicon substrate 1 using, for example, an infrared microscope so that the upper and lower patterns overlap as set. The BPSG film 9 formed on the substrate 6 is placed. Here, in this embodiment, the first. The periphery of the second single crystal silicon substrate 1.6 (or a wafer thereof) is melted and bonded using a laser in the atmosphere at a predetermined pressure (vacuum may also be used) for temporary bonding. After that, the BP
The SG films 5 and 9 are melted and the first. Both second single crystal silicon substrates 1 and 6 are bonded together. At this time, since the bonding between the two is performed under a predetermined pressure (vacuum), the inside of the recess 3, which serves as a reference pressure chamber, is also at a predetermined pressure (vacuum). Further, in this embodiment, a weight is placed on the substrate to ensure complete adhesion.

In addition, B is used as an adhesive (bonding) layer for bonding the two.
Although PSGIIW5.9 is used, other low melting point glasses may be used, and the bonding of the two is not limited to melt bonding of low melting point glasses. Alternatively, direct bonding may be performed in a furnace at a predetermined pressure (vacuum) without temporary fixing. Also, B for adhesion
The PSG films 5 and 9 are the first. Second single crystal silicon substrate 1
, 6. It is not necessary to form it on the whole part, and it may be formed partially only on the adhesive part. Further, the silicon oxide film 3.7 as an insulating film may be a silicon nitride film.

Then, the surface of the first single-crystal silicon substrate 1 on which the recess 2 is not formed is covered with wax or the like, and an anisotropic etching liquid such as KOH is used from the back surface of the second single-crystal silicon substrate 6. The second single crystal silicon 6 is removed by etching. At this time, the etching automatically stops at the silicon oxide film 7. Thereafter, as shown in FIG. 11(1), a wiring layer 10 made of tungsten or the like and a surface protection film (not shown) are formed to form a capacitive pressure sensor.

In the capacitive pressure sensor formed according to this embodiment, in the conventional capacitive pressure sensor, the diaphragm was formed by etching a single crystal silicon substrate, so it was difficult to reduce the diaphragm thickness and increase the sensitivity to pressure. ,
According to this embodiment, the diaphragm thickness is silicon oxide r4
7 and the thickness of the BPSG film 5°9, and the 8 films 5,
By making 7.9 thinner, the diaphragm thickness can be made extremely thin, and the sensitivity can be increased.

In general, the sensitivity can also be adjusted using the silicon oxide film 7 and BPSG.
By appropriately adjusting the thickness of the films 5 and 9, the thickness can be adjusted as desired.

Additionally, in the past, electrical isolation between the single crystal silicon substrate and the capacitor was achieved through a PN junction formed within the single crystal silicon substrate, which resulted in increased leakage current at the PN junction when used at high temperatures. However, in this embodiment, the upper and lower tungsten metal layers 4, which constitute both electrodes of the capacitor,
8, a P-type diffusion layer or N
Since the output can be extracted without passing through the type diffusion layer, it is not affected by leakage current at high temperatures in the PN junction, and operates stably even under high temperature conditions.

Furthermore, conventionally, a metal-semiconductor contact is used to take out the upper layer electrode, and it is difficult to reduce the resistance of the contact surface, but according to this embodiment, the electrode can be taken out using the wiring in a normal semiconductor element. This is the same process as forming the layers, so there is no problem.

In the conventional structure, the potential of the electrode on one side of the capacitor used as a sensor becomes the potential of the substrate, which can cause problems as it limits the circuit configuration of the output processing circuit. There is no limit to the potential of the electrode, and it can be set to any potential.

In addition, in the conventional structure, glass etc. are glued to the surface, which makes it impossible to suppress surface irregularities, which poses a problem in workability. However, according to this example, it is possible to almost eliminate surface irregularities. It is possible to do so without causing any workability problems.

In addition, in the conventional structure, in order to bond glass, etc. to the surface, the wafer is separated into chips, and the glass, etc. is aligned for each chip, which takes time and tends to result in defective products. According to the embodiment, since the upper and lower layers can be aligned and bonded on a wafer-by-wafer basis, it does not take much time, is less likely to produce defective products, and has good accuracy.

In addition, in this example, metals (tungsten>4,
8, but polycrystalline silicon or silicon obtained by recrystallizing polycrystalline silicon using, for example, a laser or an electron beam may also be used.

Further, although omitted in the description of the above embodiment for the sake of simplicity, a circuit for processing the output of the capacitive pressure sensor may be formed in the first single crystal silicon substrate 1.

A known semiconductor processing technique may be used for the formation method.

For example, FIG. 2 shows MO as a component of the output processing circuit.
It is a sectional view showing an SFET, in which the first single crystal silicon substrate 1 is of N type conductivity type, and 12 is the first single crystal silicon substrate.
13.14 is an N+ source diffusion region and drain diffusion region formed in the P-well region 12, 15 is a field insulating film, and 16.17 is a P-well region formed in the single crystal silicon substrate 1. source electrode respectively.

Train electrode, 1B is a gate electrode, 19 is an insulating film, 20
is a protective film.

(Second Embodiment) Next, a second embodiment of the present invention is shown in FIGS. 3(a) to (i).
I will explain based on ゛.

As shown in FIG. 3(a), a recess 22 is formed in the first single crystal silicon substrate 21 in the same manner as in the first embodiment. Subsequently, as shown in FIG. 3(b), impurities having a different conductivity type from the first single crystal silicon substrate 21 are implanted and diffused into a predetermined region including the inside of the recess 22 to form a diffusion layer 23. Subsequently, a BPSG film 24 film type 4 was formed on the same substrate 21.
(Figure 3 (C)).

On the other hand, as shown in FIG. 3(d), a silicon oxide layer 26 is formed on the second single crystal silicon substrate 25, and a B
The PSG film 27 is formed into a film shape 7 (FIG. 3(e)).

Then, as shown in FIG. 3(f), this first single crystal silicon substrate 21 and second single crystal silicon substrate 25 are bonded together in the same manner as in the first embodiment.

Thereafter, as shown in FIG. 3 (C1,), the second single crystal silicon substrate 25 is etched in the same manner as in the first embodiment. Then, as shown in FIG. 3(h), the diffusion layer 2
3 and a wiring hole 28 for connection with a metal layer to be formed later.
A metal such as aluminum is deposited to form an etching wiring layer 29 in a predetermined region. This metal need not be a high melting point metal, such as tungsten, in this second embodiment.

Next, as shown in FIG. 3(i), a protective film 3 is formed on the substrate.
form 0.

In this second embodiment, the diaphragm thickness is
, #a II! 26. ! :BPS(J324.27(7
) The diaphragm thickness can be made extremely thin by making the 8 membranes 24, 26. By appropriately adjusting the thickness of 26.27, the thickness can be adjusted as desired.

Further, the electrode 29 on one side of the capacitor is fixed at the potential of the first single crystal silicon substrate 21, and the material used is the same as that used in the manufacture of ordinary semiconductor products.Therefore, the manufacturing process is simple. Therefore, manufacturing costs can be reduced.

Note that the present invention is not limited to the first and second embodiments described above, and for example, the first embodiment and the second embodiment can be combined. That is, for example, dust oxidation gS7. The second single crystal silicon substrate 6 on which the tungsten metal layer 8 and the BPSG film 9 are formed may be bonded and etched. Further, silicon oxide film 26 and BPSG
The film 27 may be bonded to the second single-crystal silicon substrate 25 to form an etched capacitor electrode.

Effects of the Invention As detailed above, according to the present invention, the diaphragm thickness can be thinned and the sensitivity can be increased, and the diaphragm thickness can be adjusted.

[Brief explanation of drawings]

FIGS. 1(a) to (i) are cross-sectional views showing a first embodiment of the present invention, FIG. 2 is a cross-sectional view similarly showing the first embodiment, and FIGS. 2 is a sectional view showing a second embodiment of the invention. In the figure, 1 is a first single crystal silicon substrate, 2 is a recess, 4 is a tungsten metal layer, 6 is a second single crystal silicon substrate,
7 is a silicon oxide film, 8 is a tungsten metal layer, 21 is a first single crystal silicon substrate, 22 is a recess, 23 is a diffusion layer, 25 is a second single crystal silicon substrate, 26 is a silicon oxide film, 29 is a wiring It is a layer. Patent applicant Nippondenso Co., Ltd. Agent
Patent Attorney On 1) Fu Xuan Figure 3

Claims (1)

[Claims] 1. Forming a recess on the main surface of the first substrate; Subsequently, forming one electrode of the capacitor in the recess; and forming an insulating layer on the main surface of the second substrate. Subsequently, a step of forming a metal layer that will become the other electrode of the capacitor on the insulating layer; and a step of joining the main surface of the first substrate and the second main surface. A step of forming the insulating layer serving as a diaphragm and the other electrode of the capacitor above the main surface of the first substrate by etching from the other main surface side of the second substrate. A method for manufacturing a capacitive pressure sensor. 2. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein one electrode of the capacitor in the recess is a metal layer. 3. The method for manufacturing a capacitive pressure sensor according to claim 1, wherein the first substrate is a semiconductor single crystal substrate, and one electrode of the capacitor in the recess is a diffusion layer into which impurities are implanted. 4. Forming a recess on the main surface of the first substrate; Subsequently, forming one electrode of the capacitor in the recess; Forming an insulating layer on the main surface of the second substrate; A diaphragm is formed above the main surface of the first substrate by bonding the main surface of the first substrate and the second main surface, and etching from the other main surface side of the second substrate. A method for manufacturing a capacitive pressure sensor, comprising the steps of: forming the insulating layer, and forming the other electrode of a capacitor on the diaphragm. 5. The method of manufacturing a capacitive pressure sensor according to claim 4, wherein one electrode of the capacitor in the recess is a metal layer. 6. The method for manufacturing a capacitive pressure sensor according to claim 4, wherein the first substrate is a semiconductor single crystal substrate, and one electrode of the capacitor in the recess is a diffusion layer into which impurities are implanted.