JPH08181330A - Manufacture of semiconductor sensor - Google Patents

Abstract

PURPOSE: To sharply improve the yield of an electrochemical etching process. CONSTITUTION: A circle-shaped opposite conductivity type semiconductor layer 22 which is sandwiched between one conductivity type diffusion regions 20, 21 reaching a one conductivity type semiconductor substrate and which is in an electrically floating state is formed in the outer circumferential part of regions for sensor chips 16 on a semiconductor wafer 15. Pad electrodes 19, for external connection, which are used for an electrochemical etching operation are formed on it via an insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an electrochemical
The present invention relates to a method for manufacturing a semiconductor sensor such as a semiconductor acceleration sensor manufactured by using etching (ECE).

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor sensor will be described with reference to FIGS. 6A to 6G by taking the method of manufacturing a semiconductor acceleration sensor disclosed in Japanese Patent Laid-Open No. 61-95772 as an example. . In the figure, first, in (a), an n-type silicon layer 42 is formed on a p-type silicon substrate 41. An epitaxial layer is usually used as the n-type silicon layer 42, but it may be formed by diffusion. A SiO ₂ film 43 formed by thermal oxidation is formed on the surface of the n-type silicon layer 42. In (b), a p-type isolation diffusion region 44 reaching the p-type silicon substrate 41 is formed in a predetermined region of the n-type silicon layer 42. The p-type isolation diffusion region 44 has a groove portion 52 that determines the shapes of a beam portion 50 and a weight portion 51, which will be described later.
Are formed in the region corresponding to the above and the element isolation region of the bipolar IC structure. In (c), the surface SiO ₂ film 43 is selectively removed, and the p-type piezoresistor 5 is formed in a predetermined region of the beam portion 50.
3 is diffused, and then an n ⁺ region 45 for electrically connecting to the n-type silicon layer 42 is diffused. In (d), the surface SiO ₂ film 43 is selectively used to electrically connect to the n ⁺ region 45 and the p-type piezoresistor 53 for applying a voltage to the n-type silicon layer 42 when performing ECE. Contact holes are formed by etching, and Al is formed on the contact holes.
Etc. to form the electrode wiring 46 (p-type piezoresistor 53
Electrode wiring to (not shown). In (e), an etching resistant mask film 47 made of a SiO ₂ film, a Si ₃ N ₄ film or the like is formed on the back surface of the p-type silicon substrate 41, and the beam portion 50 and the groove portion 52 are partially etched so as to be etched. Done and etch resistant
Beam openings 48 and groove openings 49 are formed in the mask film 47, respectively. As the anti-etch mask film 47, the thermal oxide film formed in the previous steps may be left and used. In (f), the surface of the silicon substrate is protected by a surface protection film 54 such as silicon resin, and n
While applying a positive voltage to the type silicon layer 42, ECE is performed from the back surface with a strongly alkaline anisotropic etchant. Here, the plane orientation of the p-type silicon substrate 41 is (100), and the etching proceeds from the beam opening 48 and the groove opening 49 of the etching resistant mask film 47 to the surface side and reaches the n-type silicon layer 42. Since the n-type silicon layer 42 is biased above the passivation potential, it stops at the pn junction surface. On the other hand, in the groove portion 52 where the p-type element isolation diffusion region 44 is formed, the etching proceeds as it is and reaches the surface. In this way, a structure is formed in which the weight portion 51 having the thickness of the p-type silicon substrate 41 is supported by the beam portion 50 made of the thin n-type silicon layer 42 on the frame portion having the thickness of the silicon substrate. . Next, in (g), the backside etch-resistant mask film 47 and the surface protection film 54 are removed to complete the silicon wafer process. Thereafter, the normally completed silicon wafer is mounted on a pedestal made of Pyrex glass or the like by using a technique such as anodic bonding and then package mounted (not shown).

Next, details of the ECE will be described with reference to FIGS. 7 and 8. FIG. 7 is a top view of the silicon wafer at the time of ECE of FIG. 6F, and the acceleration sensor chips 56 described above are repeatedly arranged vertically and horizontally at the center of the silicon wafer 55. ECE around each chip
An inter-chip connection electrode 57 for interconnecting the wiring electrodes 46 is formed so as to cross the scribe lines between the chips so that the wiring electrodes 46 for biasing can be taken out. Here, the inter-chip connection electrodes 57 are formed on four sides, but it is not necessary to form them on all four sides. The inter-chip connection electrode 57 outside the outermost peripheral chip is electrically connected to the peripheral connection electrode 58 formed so as to surround the chip repeated arrangement area, and the ECE bias wiring for all the chips in the wafer is provided here. The electrode 46 is electrically connected. Four large area ECE pad electrodes 59 for standing the ECE hour-like electrodes 64 are formed outside the outer peripheral connection electrode 58, and are electrically connected to the outer peripheral connection electrode 58. In addition, the n-type silicon layer 4 outside the chip repeating region
2, a p-type diffusion layer 60 reaching the p-type silicon substrate 41 is formed in the same diffusion step as the p-type element isolation diffusion region 44. This is n on the side surface of the edge of the silicon wafer 55.
This is to prevent the type silicon layer 42 and the p-type silicon substrate 41 from short-circuiting.

The silicon wafer 55 thus formed
As shown in FIG. 8, the wafer is assembled in a wafer holder 63, and a needle electrode 64 is set up on the pad electrode 59 for ECE and placed in an etching bath 61 filled with a silicon etching solution 62. Silicon etching solution 6
2 is ethylenediamine / pyrocatechol, KO
A strongly alkaline anisotropic etching solution such as H or hydrazine is used. A counter electrode 64 is placed in the silicon etching solution 62 so as to face the silicon wafer 55, and a power source 65 is connected so that the needle electrode 64 becomes positive. In this way, the n-type silicon layer 42 corresponding to the beam portion of each chip 56 is interconnected by the wiring electrode 46 such as Al,
ECE can be easily performed by drawing out to the ECE pad electrode 59 on the outer peripheral portion of the wafer. Note that FIG.
Then, the two-electrode method was explained.
The three-electrode method in which the potential of the etching solution 62 in the vicinity is monitored by the reference electrode and the potential of the counter electrode 66 is controlled, and the four-electrode method in which the potential of the p-type silicon substrate 41 is further controlled can be similarly performed. .

In such a method of manufacturing a semiconductor acceleration sensor, the basic structure of the acceleration sensor in which the weight portion is supported by the beam portion can be simultaneously formed by one etching.
By using CE, a thin beam that is determined by the thickness of the epitaxial layer, etc. can be formed with high precision, and this has the advantage that sensitivity can be easily increased (the sensitivity of the acceleration sensor is inversely proportional to the square of the beam thickness). To). Further, since the process up to ECE is basically the same as the bipolar process, it is possible to easily realize an integrated acceleration sensor in which a signal processing circuit is built in the same chip as the detection unit.

[0006]

However, in such a conventional method of manufacturing a semiconductor acceleration sensor,
N-type silicon layer 4 for forming the beam portion 50 of each chip
The wiring electrode 46 for applying a voltage to 2 is drawn out to the outer peripheral portion of the chip repeating region in the wafer, and is formed on the outer peripheral p-type diffusion region 60 via the surface SiO ₂ film 43 and has a relatively large area. It is connected to the ECE pad electrode 59, and at the time of ECE, the needle electrode 64 is erected on the ECE pad electrode 59 to bias the silicon wafer. Therefore, the periphery of the wafer is handled by tweezers or the like. The probability of occurrence of pinholes is extremely high. If the pad electrode 59 for ECE has a relatively large area.
Alternatively, if there is a pinhole 67 in the surface SiO ₂ film 43 directly below the connection electrode 58 there, as shown in FIG.
Pad electrode 59 side and p-type silicon substrate 41 are on the outer peripheral portion p.
It is electrically short-circuited via the type diffusion region 60, and an excessive leak current flows during ECE. Therefore, n of each chip 56
Since the potential of the type silicon layer 42 deviates from the set value, the etching does not stop at the pn junction surface depending on the position in the wafer, and as a result, etching control becomes impossible and the wafer stage becomes defective, resulting in a significant decrease in yield. There was a problem.

The present invention has been made by paying attention to such a conventional problem, in which a pad electrode for external connection for electrochemical etching and a one conductivity type semiconductor substrate are formed by a pinhole or the like formed in an insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor sensor, which can reduce the probability of short circuit and can significantly improve the yield of the electrochemical etching process.

[0008]

In order to solve the above-mentioned problems, the invention according to claim 1 forms a semiconductor layer of opposite conductivity type on the main surface of a semiconductor substrate of one conductivity type, and the semiconductor layer of one conductivity type. A step of selectively forming an anti-etching mask film on the back surface of the semiconductor substrate, and using an anisotropic etching solution while applying a positive voltage to the opposite conductivity type semiconductor layer, removing the one conductivity type semiconductor substrate from the back surface. Forming a thin film structure that is displaced according to a mechanical quantity signal from the outside on each sensor chip repeatedly arranged on the semiconductor wafer composed of the one-conductivity-type semiconductor substrate by electrochemical etching. In the method of manufacturing a semiconductor sensor having the one-conductivity-type semiconductor substrate, an outer peripheral portion of a region where the sensor chip is repeatedly arranged in the semiconductor wafer is reached. For forming an electrically conductive floating annular semiconductor layer of opposite conductivity type sandwiched between diffusion regions, and for external connection for the electrochemical etching through an insulating film on the opposite semiconductor layer of opposite conductivity type. The gist is that a pad electrode is formed.

According to a second aspect of the present invention, in the method for manufacturing a semiconductor sensor according to the first aspect, a semiconductor layer of opposite conductivity type is formed around each of the sensor chips in an electrically floating state, and the semiconductor layer is formed around the chip. An inter-chip connection electrode for electrically connecting the opposite conductivity type semiconductor layer in each sensor chip during the electrochemical etching through the insulating film on the surrounding opposite conductivity type semiconductor layer is formed. Use as a summary.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor sensor according to the first or second aspect, the semiconductor sensor has the one conductivity type semiconductor substrate in a region corresponding to a groove portion in the opposite conductivity type semiconductor layer. And a step of forming one conductivity type piezoresistor in a predetermined region corresponding to the beam portion on the surface of the opposite conductivity type semiconductor layer by diffusion. The weight portion formed so that a part of the one conductivity type semiconductor substrate is separated by the groove portion formed in the step, the thick frame portion and the weight portion formed so as to surround the weight portion, The gist of the present invention is to provide a semiconductor acceleration sensor including a thin single or plural beam portions made of the opposite conductivity type semiconductor layer suspended and supported on a frame portion.

The invention according to claim 4 is the above-mentioned claim 1 or 2.
Alternatively, in the method for manufacturing a semiconductor sensor according to the third aspect, the one conductivity type semiconductor substrate is a p-type silicon substrate having a plane orientation of (100), and the opposite conductivity type semiconductor layer is an epitaxial layer of n-type silicon. And

A fifth aspect of the present invention is characterized in that, in the method for manufacturing a semiconductor sensor according to the third aspect, a peripheral circuit formed of a bipolar element is integrated in the frame portion.

[0013]

According to the invention of claim 1, the pad electrode for external connection for electrochemical etching is formed on the electrically conductive ring-shaped opposite conductivity type semiconductor layer through an insulating film to provide insulation. Even if a pinhole is formed in the film, the external connection pad electrode and the one conductivity type semiconductor substrate are not electrically short-circuited, and the electrochemical etching characteristics are not affected at all.

According to the second aspect of the present invention, the inter-chip connecting electrode for electrochemical etching is formed on the electrically conductive semiconductor layer around the chip surrounding the opposite conductivity type via the insulating film, whereby the insulating film is formed. Even if a pinhole is generated, the inter-chip connection electrode and the one-conductivity-type semiconductor substrate will not be electrically short-circuited.

According to the third aspect of the present invention, the semiconductor acceleration sensor having a structure in which the weight portion is supported by the frame portion by the thin beam portion which is determined by the thickness of the semiconductor layer of opposite conductivity type is manufactured with high yield by the electrochemical etching process. To be done.

In the invention of claim 4, the one conductivity type semiconductor substrate is a p-type silicon substrate having a plane orientation of (100), and the opposite conductivity type semiconductor layer is an n-type silicon epitaxial layer. The anisotropic etching of the one-conductivity-type semiconductor substrate is appropriately performed by the etching, and the weight portion, the thin beam, and the like are formed with high accuracy, so that a highly sensitive acceleration sensor can be manufactured.

In the invention described in claim 5, since the manufacturing process of the semiconductor acceleration sensor is basically the same as the bipolar process, a peripheral circuit composed of a bipolar element can be easily integrated in the frame portion by adding a few steps. It becomes possible to do.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are views showing a first embodiment of the present invention. FIG. 1 is a wafer top view at the time of ECE corresponding to FIG. 7, and FIG. 2 is a cross-sectional view of the AA ′ element of FIG.

First, the configuration will be described. The manufacturing process is shown in FIG.
Since it is almost the same as the conventional example shown in FIG. 1 and only the configuration of the peripheral portion of the wafer is different, only the different points will be described below. In FIGS. 1 and 2, 15 is a silicon wafer,
16 is an individual sensor chip, which is a silicon wafer 15
Are repeatedly arranged two-dimensionally in the central part of. In each sensor chip, the n-type silicon layer 2 is formed on the p-type silicon substrate 1 as in the conventional example, and the p-type isolation diffusion region 4 reaching the p-type silicon substrate 1 is formed in the groove 12 and the element isolation region. Then, the p-type isolation diffusion region 4 of the groove 12 is removed by ECE through the back surface etching resistant mask film 7 having the beam opening 8 and the groove opening 9 in the beam 10 and the groove 12, and the weight 11 is thinned. A structure that is supported by the beam portion 10 is formed. A p-type piezoresistor 13 for acceleration detection is formed on the surface of the n-type silicon layer 2 of the beam portion 10, and an n ⁺ diffusion region 5 is formed for voltage application during ECE. n ⁺ diffusion region 5 has a surface Si
The wiring electrodes 6 of Al or the like are connected through the contact holes of the O ₂ film 3, and the wiring electrodes 6 of each sensor chip 16 are connected to all the chips 16 in the wafer 15 vertically and horizontally by the inter-chip connection electrodes 17. The ECE pad electrode 19 is passed through the outer peripheral connection electrode 18 outside the repeated arrangement region.
It is configured to be connected to. A p-type diffusion region 21 around the chip region is formed immediately outside the chip repeated arrangement region, and an n-type silicon layer 22 is left in an annular shape with the outer peripheral p-type diffusion region 20. There is. E on the surface SiO ₂ film 3 of the annular n-type silicon layer 22
A CE pad electrode (external connection pad electrode) 19 and an outer peripheral connection electrode 18 are formed.

The procedure of ECE is almost the same as that of the conventional example, and after the surface protection film 14 is attached to the silicon wafer 15, the wafer
It is attached to a holder and placed in an etching bath as shown in FIG. 8 while positively biasing the pad electrode 19 for ECE and Si.
Anisotropic etching is performed through the backside etching resistant mask film 7 made of an O ₂ film or a Si ₃ N ₄ film. Since the back surface of the wafer outer peripheral portion is covered with the back surface etching resistant mask film 7, the structure of the diffusion layer on the front surface side here basically does not affect the beam structure or the like in the chip repeated arrangement region.

Next, the operation will be described. Generally, in photolithography, pinholes are apt to occur due to dust, scratches, coating unevenness, etc. in the resist coating process, which is one of the causes of lowering the chip yield. The situation is the same in the manufacturing process of the semiconductor acceleration sensor described here, but in the contact etching step immediately before the formation of the wiring electrode for ECE, since the wiring electrodes are all connected within the wafer, the surface SiO ₂ Pinholes in the film affect wafer-level ECE yield. For example, if the wiring electrode and the p-type silicon substrate are short-circuited due to a pinhole, n
In ordinary ECE in which a sufficient positive voltage is applied to the p-type silicon layer, the p-type silicon substrate is also biased above the passivation potential and etching does not proceed. In addition, even when biasing in the middle of the n-type and p-type passivation potentials, the
There are chips in which etching is stopped and chips are not stopped in the type silicon layer, which results in a large decrease in yield in any case.

FIG. 3 is a sectional view of the element at the time of ECE when there are pinholes in the peripheral portion of the wafer in this embodiment. Immediately below the pinhole 30 formed in the surface SiO ₂ film 3 is the outer peripheral p-type diffusion region 20 and the chip region peripheral p-type diffusion region 2.
It is an annular n-type silicon layer 22 sandwiched between 1 and 1. Even if this is short-circuited with the wiring electrode, the annular n-type silicon layer 22 is electrically floating, so that it does not affect the characteristics of the ECE at all. Therefore, in a manufacturing process using ECE such as a semiconductor acceleration sensor, it is possible to significantly improve the yield and reduce the cost.

FIG. 4 shows a second embodiment of the present invention. FIG. 4 is a wafer top view at the time of ECE similar to FIG.
Only the differences from In FIG. 1, a p-type diffusion region 21 around the chip region is formed in a strip shape around the chip repeated arrangement region.
However, in the present embodiment, the p-type diffusion region 21 around the chip region is eliminated, and the p-type separation diffusion region 31 around the chip is provided around each chip 16 to correspond to the scribe line on the outside thereof. The lattice-shaped region is a floating chip peripheral n-type silicon layer 32. With this configuration, the pad electrode 1 for ECE on the outer peripheral portion of the wafer 15
1 in that the 9 and the peripheral connection electrode 18 are not short-circuited to the p-type silicon substrate 1 due to the pinholes in the surface SiO ₂ film 3.
However, the probability that the inter-chip connection electrode 17 is short-circuited to the p-type silicon substrate 1 can be further reduced. In the figure, the entire scribe line is around the chip n
Although the structure is such that the n-type silicon layer 32 is formed, the same effect can be obtained even when only a part of the scribe line is formed as the n-type silicon layer.

FIG. 5 shows a sectional view of the element after completion when the peripheral circuits are integrated in the sensor chip 16 shown in the first and second embodiments. The manufacturing process of the semiconductor acceleration sensor as described above is basically the same as the bipolar process, and the circuit element can be easily formed by adding a few steps. In the figure, for simplicity, a single NP
A sectional view of an N-transistor is shown. Here, 33 is an n ⁺ buried layer, which is formed by Sb diffusion or the like before forming the n-type epitaxial layer 2. The p-type base diffusion layer 35 can use the same diffusion as the p-type piezo diffusion layer 13 or can use different diffusion. n ⁺ emitter diffusion region 34 and n ⁺
The collector diffusion region 36 can be formed simultaneously with the n ⁺ diffusion region 5 because of the ECE bias. The emitter electrode 37, the base electrode 38, and the collector electrode 39 to these diffusion regions can use the same electrode layer as the ECE wiring electrode 6. ECE can be similarly performed when the circuits are integrated. Further, in the figure, the acceleration detection unit is shown as a cantilever structure because it is simple, but it is naturally applicable to a double-supported beam structure as well.

Although the respective embodiments have been described by taking the semiconductor acceleration sensor as an example, the present invention can be applied to all semiconductor sensors such as a pressure sensor and a vibration gyro that form a thin film structure by ECE.

[0026]

As described above, according to the first aspect of the invention, the semiconductor chip is sandwiched by the one conductivity type diffusion regions reaching the one conductivity type semiconductor substrate at the outer periphery of the region where the sensor chips are repeatedly arranged. To form an electrically floating floating semiconductor layer of opposite conductivity type, and to form a pad electrode for external connection for electrochemical etching on the second opposite conductivity type semiconductor layer through an insulating film. Even if a pinhole is formed in the film, the probability of short circuit between the external connection pad electrode and the one conductivity type semiconductor substrate is reduced, and the yield of the electrochemical etching process can be significantly improved.

According to the invention described in claims 2 to 5, in addition to the effects of the invention described in claim 1, the following effects are further provided.

According to the second aspect of the invention, a semiconductor layer of opposite conductivity type around the chip in an electrically floating state is formed around each of the sensor chips, and an insulating film is formed on the semiconductor layer of opposite conductivity type around the chip. Since the inter-chip connection electrode for electrically connecting the opposite conductivity type semiconductor layers in each of the sensor chips during the electrochemical etching is formed, the inter-chip connection electrode is formed even if a pinhole is formed in the insulating film. The probability of short-circuiting with the one-conductivity-type semiconductor substrate is reduced even in the area (1), and the yield of the electrochemical etching step can be further improved significantly.

According to the third aspect of the present invention, the semiconductor sensor has a step of forming one conductivity type separation diffusion region reaching the one conductivity type semiconductor substrate in a region corresponding to the groove in the opposite conductivity type semiconductor layer. A step of diffusing and forming a piezoresistor of one conductivity type in a predetermined region corresponding to a beam on the surface of the semiconductor layer of the opposite conductivity type, the one conductivity type semiconductor being formed by the groove formed in the step of the electrochemical etching. A weight portion formed so that a part of the substrate is separated, a thick frame portion formed so as to surround the weight portion, and the opposite conductivity type semiconductor layer suspending and supporting the weight portion on the frame portion. Since the semiconductor acceleration sensor is equipped with a single or multiple thin beam part made of, the weight is determined by the thickness of the opposite conductivity type semiconductor layer made of an epitaxial layer or the like. The semiconductor acceleration sensor of the supported to the frame portion at the beam portion of the thin structure can be manufactured with good yield by electrospray chemical etching process.

According to the invention of claim 4, the one conductivity type semiconductor substrate is a p-type silicon substrate having a plane orientation of (100), and the opposite conductivity type semiconductor layer is an n-type silicon epitaxial layer. Anisotropic etching of a single conductivity type semiconductor substrate is appropriately performed by electrochemical etching using an anisotropic etching liquid to form a thin film structure such as a thin beam portion with high accuracy, and a highly sensitive semiconductor sensor is obtained. It can be manufactured.

According to the fifth aspect of the present invention, the manufacturing process of the semiconductor acceleration sensor is basically the same as the bipolar process. Therefore, by adding a few steps, a peripheral circuit including a bipolar element is added to the frame portion. It can be easily integrated.

[Brief description of drawings]

FIG. 1 is a top view of a semiconductor wafer during ECE in a first embodiment of a method for manufacturing a semiconductor sensor according to the present invention.

FIG. 2 is a sectional view of a sensor element at the time of ECE in the first embodiment.

FIG. 3 is a sectional view of an element for explaining a countermeasure against pinholes in a surface SiO ₂ film in the first embodiment.

FIG. 4 is a top view of a semiconductor wafer during ECE in the second embodiment of the present invention.

FIG. 5 is an element cross-sectional view showing an example in which peripheral circuits are integrated in the sensor chip in the first and second embodiments.

FIG. 6 is a process chart showing a method of manufacturing a conventional semiconductor acceleration sensor.

FIG. 7 is a top view of a semiconductor wafer during ECE in the above conventional example.

FIG. 8 is a configuration diagram showing an ECE device.

FIG. 9 is a diagram for explaining a short circuit due to a pinhole in a surface SiO ₂ film in the above conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 p-type silicon substrate 2 n-type silicon layer 3 surface SiO ₂ film (insulating film) 4 p-type isolation diffusion region 6 wiring electrode 7 backside etching resistant mask film 8 beam opening 9 groove opening 10 beam 11 weight 12 groove 13 p-type piezoresistive 15 silicon wafer 16 sensor chip 17 inter-chip connection electrode 19 ECE pad electrode (external connection pad electrode) 20 outer peripheral p-type diffusion region 21 chip region surrounding p-type diffusion region 22 annular n-type silicon layer 31 p-type separation diffusion region around chip 32 n-type silicon layer around chip

Claims (5)

[Claims] 1. A step of forming an opposite conductivity type semiconductor layer on a main surface of a one conductivity type semiconductor substrate, a step of selectively forming an etching resistant mask film on a back surface of the one conductivity type semiconductor substrate, On the semiconductor wafer composed of the one-conductivity-type semiconductor substrate by electrochemical etching in which the one-conductivity-type semiconductor substrate is etched from the back surface using an anisotropic etching solution while applying a positive voltage to the opposite-conductivity-type semiconductor layer. In a method of manufacturing a semiconductor sensor, which comprises a step of forming a thin film structure that is displaced in accordance with a mechanical quantity signal from the outside in each sensor chip that is repeatedly arranged,
An annular opposite conductivity type semiconductor layer in an electrically floating state is formed by being sandwiched between one conductivity type diffusion regions reaching the one conductivity type semiconductor substrate on the outer peripheral portion of the region where the sensor chips are repeatedly arranged in the semiconductor wafer. A method of manufacturing a semiconductor sensor, comprising: forming an external connection pad electrode for the electrochemical etching on the annular opposite conductivity type semiconductor layer through an insulating film. 2. A semiconductor layer of opposite conductivity type around the chip in an electrically floating state is formed around each of the sensor chips, and an electroconductive etching is performed on the semiconductor layer of opposite conductivity type around the chip via an insulating film. The method for manufacturing a semiconductor sensor according to claim 1, further comprising: forming inter-chip connection electrodes for electrically connecting the opposite conductivity type semiconductor layers in each of the sensor chips. 3. In the semiconductor sensor, a step of forming one conductivity type isolation diffusion region reaching the one conductivity type semiconductor substrate in a region corresponding to a groove portion in the opposite conductivity type semiconductor layer, and a surface of the opposite conductivity type semiconductor layer. A step of diffusing and forming a one-conductivity type piezoresistor in a predetermined region corresponding to the beam portion, and a part of the one-conductivity type semiconductor substrate is separated by the groove formed in the electrochemical etching step. A thin portion or a plurality of thin-walled portions composed of a weight portion formed as described above, a thick frame portion formed so as to surround the weight portion, and the opposite conductivity type semiconductor layer that suspends and supports the weight portion on the frame portion. The method of manufacturing a semiconductor sensor according to claim 1, wherein the semiconductor acceleration sensor includes a beam portion. 4. The plane direction of the one conductivity type semiconductor substrate is (1
4. The method for manufacturing a semiconductor sensor according to claim 1, wherein the semiconductor sensor is a p-type silicon substrate (00), and the semiconductor layer of opposite conductivity type is an epitaxial layer of n-type silicon. 5. A peripheral circuit formed of a bipolar element is integrated in the frame portion.
A method for manufacturing the semiconductor sensor described above.