JP3129851B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art Conventionally, JP-A-59-13377 discloses an electrochemical etching method for forming a diaphragm of a diaphragm type silicon pressure sensor. This is to form a diaphragm by electrochemical etching. An HF-based etchant is used as an etchant at this time. When the HF-based etchant is used, the voltage is supplied to the area to be etched and the current does not flow, so that the etching proceeds, and the fact that the current has flowed is detected to terminate the etching.

[0003]

However, when a KOH-based etchant is used, if current does not flow through the area to be etched, the etching proceeds by a chemical reaction between KOH and silicon, and after the etching is completed. Also, the minute current continued to flow due to the anodic oxidation of silicon, and it was difficult to clearly detect the end point of etching.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of ending electrochemical etching at an optimum time.

[0005]

SUMMARY OF THE INVENTION The present invention provides a first step of forming a thin film of a second conductivity type single crystal semiconductor film on a first conductivity type single crystal semiconductor substrate; a second step of forming a conductive material, said in KOH etchant wherein while immersing a single crystal semiconductor substrate single crystal half
Perform electrochemical etching through the conductive material to a plurality of areas of the conductor substrate, wherein in each of said regions a single
The plane of the thickness of the single crystal semiconductor substrate including the crystal semiconductor film
By terminating the electrochemical etching at the inflection point of the constant current peak <br/> after click to draw a gentle curve of the energizing current produced by the fabric, a plurality of the territory of the single crystal semiconductor substrate
Remove different amounts in the area,
The corresponding predetermined regions of the single crystal semiconductor film are substantially the same.
A third step of leaving a thickness, and a fourth step of cutting the single crystal semiconductor substrate to obtain a plurality of chips including any of the plurality of regions of the single crystal semiconductor substrate removed by the electrochemical etching. A gist is a method for manufacturing a semiconductor device having the same.

In addition, the completion of the etching in the third step is
The after a predetermined time after the peak to draw a gentle curve of the energizing current it may be regarded as a point of inflection.

[0007]

In the present invention, a thin film of a second conductivity type single crystal semiconductor film is formed on a first conductivity type single crystal semiconductor substrate in a first step, and a conductive film is formed on the single crystal semiconductor film in a second step. wood is formed, wherein while immersing the single crystal semiconductor substrate by the third process in KOH etchant
Electrochemical etching is performed on the plurality of regions of the single crystal semiconductor substrate through the conductive material, and each of the regions is subjected to electrochemical etching .
Of the single crystal semiconductor substrate including the single crystal semiconductor film
Slow curve of current flow caused by thickness distribution
By terminating the electrochemical etching at the inflection point of the constant current after the peak draw, different amounts in a plurality of the regions of the single crystal semiconductor substrate is removed, the individual
A predetermined region of the single crystal semiconductor film corresponding to the region of
It is left at substantially the same thickness . At this time, the electrochemical etching is terminated at an optimum time based on the inflection point. In other words, the etching ends, the single crystal semiconductor in the individual regions
Etching in all chips can be time ended by considering the surface distribution of the thickness of the single-crystal semiconductor material substrate comprising a body membrane.

Further, in the fourth step, a single-crystal semiconductor substrate
By cutting the plate, the electrochemical etching
Therefore, what is removed in the plurality of regions of the single crystal semiconductor substrate
A plurality of chips containing these are obtained.

[0009]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view of a semiconductor acceleration sensor. FIG. 2 is a plan view of the semiconductor acceleration sensor.
FIG. 3 shows an AA cross section of FIG. This sensor is used for an ABS system of a vehicle.

As shown in FIG. 1, a square plate-shaped silicon chip 2 is arranged on a square plate-shaped pedestal 1 made of Pyrex glass. As shown in FIG. 2, the silicon chip 2 has a rectangular frame-shaped first
The first supporting portion 3 is formed using four sides of the silicon chip 2. Four through holes 4a, 4b, 4c, 4d penetrating vertically are formed inside the first support portion 3 of the silicon chip 2, and the four thin movable portions 5, 6, 7, 8 are thick. Are connected to each other. Further, in the inside of the first support portion 3 of the silicon chip 2, a through hole 1 penetrating vertically
0 is formed so as to surround the through holes 4a, 4b, 4c, 4d. The through-hole 10 defines a thick U-shaped second support portion 11 and a thick connecting portion 12.

That is, the second support portion 11 is extended from the thick first support portion 3 to be joined to the pedestal 1, and the second support portion 11 is extended.
And the movable parts 5 to 8 having a small thickness are extended. Further, the first support portion 3 and the second support portion 1 are formed by the through holes 10.
1 has a structure connected by a connection portion 12. Further, the second support portion 11 and the weight portion 9 are connected by the movable portions 5 to 8 as described above. The thickness of each of the movable parts 5 to 8 is about 5 μm, and each of the two piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1
6a and 16b are formed. As shown in FIG. 3, a concave portion 17 is formed at the center of the upper surface of the pedestal 1 so as to prevent contact when the acceleration portion is applied and the weight portion 9 is displaced.

FIG. 4 shows a wiring pattern made of aluminum on the surface of the silicon chip 2. In this embodiment, a wiring 18 for grounding, a wiring 19 for applying a power supply voltage, a wiring 20 for outputting a potential difference according to acceleration,
21 are formed. Another one for these wirings
A set of four wires is provided. That is, the ground wiring 22, the power supply voltage applying wiring 23, and the output wirings 24 and 25 for extracting a potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the power supply voltage application wiring 19, and the ground wiring 18 is arranged on the impurity diffusion layer 26 via a silicon oxide film in an intersecting state. . Similarly,
The power supply voltage application wiring 23 is connected to the power supply voltage application wiring 19 via the impurity diffusion layer 27, the ground wiring 22 is connected to the ground wiring 18 via the impurity diffusion layer 28, and The output wiring 24 is the impurity diffusion layer 2
9 is connected to an output wiring 20. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wiring 1
Connection using 8 to 21 is performed.

Then, as shown in FIG. 5, each of the piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1
6a and 16b are electrically connected so that a Wheatstone bridge circuit is formed. Here, the terminal 31 is a ground terminal, the terminal 32 is a power supply voltage application terminal, and the terminals 33 and 34 are output terminals for extracting a potential difference according to the acceleration.

Next, a method of manufacturing the sensor will be described. FIG.
26 to 26 show the manufacturing process of the sensor. First, as shown in FIG. 6, a p-type single crystal silicon wafer 35 is prepared,
An n-type epitaxial layer 36 is formed on the surface. Then, as shown in FIG. 7, ap ⁺ diffusion layer 37 is formed in the piezoresistive layer forming region of the epitaxial layer 36, and an n ⁺ diffusion layer 38 is formed on the scribe line. Further, the through holes 4a, 4b, 4c, 4 shown in FIG.
An n ⁺ diffusion layer 39 is formed in the region where d and 10 are formed. Thereafter, aluminum 40 is arranged on n ⁺ diffusion layer 38 and a pad is extended from a part of aluminum 40. Furthermore, n
⁺ Aluminum 41 as a metal thin film is arranged on diffusion layer 39.

Here, the wiring structure of the aluminum 40 will be described in detail. FIG. 8 shows a plane at the intersection of the aluminum 40 on the substrate. FIG. 9 shows a cross section taken along line DD of FIG. As shown in FIG. 9, the aluminum 40 is disposed in a scribe area, and a notch 65 for passing a blade 66 of a dicing cut is formed in the center thereof. That is, the width W1 of the notch 65 is equal to the blade 66 of the dicing cut.
Is slightly wider than the width W2. That is, when the blade 66 of the dicing cut passes through the notch 65 of the aluminum 40, the blade 66 of the dicing cut does not contact the aluminum 40.

As shown in FIG. 8, a notch 65 for passing the dicing cut blade 66 is not formed at the intersection of the aluminum 40. This is to reduce the resistance of a current supply line for performing an electrochemical etching described later.

In FIG. 9, 67 is a silicon oxide film, 68 is an aluminum wiring, and 69 is a passivation film. Subsequently, as shown in FIG. 10, a plasma nitride film (P-SiN) 52 is formed on the back surface of the single crystal silicon wafer 35, and predetermined patterning is performed by photoetching. Then, a current is supplied to the pad of aluminum 40 to perform electrochemical etching using the n ⁺ diffusion layer 38 as an electrode.

Here, the electrochemical etching will be described in detail. As shown in FIG. 11, a KOH aqueous solution (33 wt.
%, 82 ° C.) 76 and dipped the single-crystal silicon wafer 35 in a Pt (platinum) electrode plate 7 in a KOH aqueous solution.
0 is arranged to face the single crystal silicon wafer 35. Then, a constant voltage power supply (2 volts) 71, an ammeter 72, and a contact 73 are connected in series between the aluminum 40 of the single crystal silicon wafer 35 and the Pt electrode plate 70. Also, the controller 7
4, a start switch 75, an ammeter 72 and a contact 73 are connected. The controller 74 detects the start of etching based on a signal from the start switch 75 and also detects a supplied current based on a signal from the ammeter 72. Further, the controller 74 drives the contact 73 to open and close. The controller 74 is mainly composed of a microcomputer.

The controller 74 executes the processing shown in FIGS. This processing will be described with reference to the time chart of FIG. Note that the vertical axis in FIG. 14 indicates the current value. First, when the controller 74 inputs an etching start signal from the start switch 75, the controller 74 starts the processing in FIG. The controller 74 determines in step 101 that the contact 73
Is closed, and the flag F is set to “0” in step 102. Further, the controller 74 determines in step 103 that the ammeter 7
Reads the current of the current value I _i by 2, step 104
And the difference ΔI _i between the current value I _i and the previous value I _i-1 (= I _i −I
_i-1 ) is calculated.

Then, the controller 74 executes step 1
At 05, it is determined whether or not the change rate ΔI _i of the conduction current has been inverted from positive to negative. That is, it is determined whether or not the energizing current value has reached a peak in FIG. 14 (timing of tp in FIG. 14). The controller 74 returns to step 103 if the change rate ΔI _i of the energizing current has not inverted from positive to negative. If the change rate ΔI _i of the energizing current has inverted from positive to negative, the controller 74 sets the flag F to “1” in step 106. Set.

The controller 74 executes the interrupt process shown in FIG. 13 every predetermined time. The controller 74 determines in step 201 whether the flag F is “1”, and F = 0
Then return. On the other hand, the controller 74 determines that F = 1
When the change rate [Delta] I _i of the electric current is determined whether it is "0" at step 202, the process returns so [Delta] I _i ≠ 0 becomes [Delta] I _i is negative, during a period tp -t2 in Fig. Then, the controller 74 determines the rate of change ΔI
_{When i} becomes "0" (timing t2 in FIG. 14), the contact 73 in FIG. 11 is opened in step 203 to terminate the energization. Immediately after completion of the energization, the single crystal silicon wafer 35 is taken out of the KOH aqueous solution 76 and the single crystal silicon wafer 35 is washed with water. Thus, the electrochemical etching ends.

The behavior of the energizing current value in FIG. 14 will be described. In the first region after the energization starts, the etching of the single crystal silicon wafer 35 progresses due to the chemical reaction between KOH and silicon. This is because the voltage is supplied to the aluminum 40, but no current is supplied to the single crystal silicon wafer 35 by the PN junction formed by the single crystal silicon wafer 35 and the epitaxial layer 36. The second region has a peak current, and in the same region, anodization proceeds due to an electrochemical reaction of the single crystal silicon wafer. This is because the single crystal silicon wafer 35 is etched, the PN junction disappears, and the epitaxial layer 36 to which the voltage is supplied comes into contact with the KOH aqueous solution, so that a current flows and silicon on the surface of the epitaxial layer 36 is oxidized. It is. Furthermore, the reason why the second region has a gentle peak is due to the thickness distribution (variation in thickness) of the single crystal silicon wafer 35.

In the next third region, the current value decreases again but becomes larger than the current value in the first region. This is because silicon oxide is etched even though the etching rate is low, so that the etching of oxide and the oxidation of silicon maintain an equilibrium state. More specifically, since the etching rate of the silicon oxide with the KOH aqueous solution is about 100 times smaller than that of silicon, the etching of silicon is almost completed.

In this manner, the inflection point to the equilibrium current due to the silicon oxide film after the peak of the conduction current value in the second region is the end point of the etching. In FIG. 11, the diameter of the single-crystal silicon wafer 35 is 10 cm, and the total value of the etched portions (the portions indicated by L in FIG. 11) is 17.4 cm ² .

When performing this electrochemical etching, FIG.
As shown in FIG. 0, since the n ⁺ diffusion layer 39 is present in a predetermined region of the epitaxial layer 36 in the chip, the current supplied from the n ⁺ diffusion layer 38 is sufficiently supplied without being impaired by the lateral resistance. It can be supplied to the chemically etched surface. In other words, the lateral resistance of the epitaxial layer 36 is reduced, and a sufficient current is supplied to a portion at a distance from the voltage supply unit, an anodic oxide film is formed, and the etching is easily stopped.

Here, as shown in FIGS. 15 and 16, ap ⁺ diffusion layer 54 reaching the single crystal silicon wafer 35 is formed at the outer peripheral portion of the chip formation region in the epitaxial layer 36, and the electric potential shown in FIG. The part where the PN junction leaks at the outermost periphery of the wafer during chemical etching (B in FIG. 17)
) And the portion to be etched are electrically insulated, thereby preventing the occurrence of leakage and forming a uniform thin portion with high precision. That is, when the p ⁺ diffusion layer 54 is not formed, since the potential at the outermost peripheral portion of the epitaxial layer 36 is the same as the potential at the central portion of the epitaxial layer 36, leakage occurs at the portion B in FIG. On the other hand, by forming the p ⁺ diffusion layer 54, the outermost peripheral portion of the epitaxial layer 36 has the same potential as the silicon wafer 35, and no leak occurs.

Incidentally, the high-concentration diffusion layer for preventing leakage may be formed as follows. First, as shown in FIG. 18, after forming ap ⁺ buried layer 55 on the surface of a p-type single crystal silicon wafer 35, an n-type epitaxial layer 3 is formed on the wafer surface.
6 is formed. Then, as shown in FIG. 19, ap ⁺ diffusion layer 56 is formed in the epitaxial layer 36 by a heat treatment in an oxygen atmosphere, and the two layers 55 and 56 are overlapped with each other. Thereafter, electrochemical etching is performed as shown in FIG. This method is advantageous in that the time for deeply diffusing the p ⁺ diffusion layer down to the silicon wafer can be reduced particularly when the epitaxial layer is thick.

Further, at the time of electrochemical etching, FIG.
As shown in FIG. 22, a platinum ribbon 59 is sandwiched between an alumina support substrate 57 and a silicon wafer 58, and the silicon wafer 58 and the support substrate 57 are fixed with a resin (for example, heat-resistant wax) 60. The resin 60 causes the silicon wafer 58 and the platinum ribbon 59 to etch with an etchant (eg,
33 wt% KOH solution, 82 ° C) protected from 61. As shown in FIGS. 22 and 23, the platinum ribbon 59 has a band-like shape, and its tip side has a waveform. The thickness of the corrugated portion of the platinum ribbon 59 is W when no external force is applied.
When fixed between the silicon wafer 58 and the silicon wafer 58, the thickness of the corrugated portion of the platinum ribbon 59 is compressed to W or less, and a force for spreading the silicon wafer 58 and the support substrate 57 is applied. Therefore, in this state, the platinum ribbon 5
9 and the silicon wafer 58 are surely kept in electrical contact. After the electrochemical etching, as shown in FIG. 24, the silicon wafer 58 or the like is immersed in a solvent (for example, trichloroethane) 62 to dissolve the resin 60 and take out the silicon wafer 58. During the immersion of the silicon wafer 58, the corrugated portion of the platinum ribbon 59 exerts a force for expanding the silicon wafer 58 and the support substrate 57, so that the gap between the silicon wafer 58 and the support substrate 57 is widened. Therefore, in this portion, the speed at which the solvent 62 circulates by the stirrer 64 is increased, and fresh solvent 62 is supplied to the stripping portion, thereby shortening the stripping time.
In other words, if the platinum ribbon 59 is not made into a corrugated shape and is compressed, but a flat platinum ribbon is used, the gap between the support substrate 57 and the silicon wafer 58 becomes narrow due to the weight of the silicon wafer 58 during the step of removing the resin 60. However, by arranging the platinum ribbon 59 in a waveform in a compressed state, the peeling time can be reduced.

By such electrochemical etching, as shown in FIG. 10, a predetermined region of the single crystal silicon wafer 35 is removed to form a groove 42 and a predetermined region of the epitaxial layer 36 remains. Parts 5,6
7, 8 (see FIG. 2) are formed.

Then, as shown in FIG. 25, a predetermined region (a region including the n ⁺ diffusion layer 39) of the epitaxial layer 36 is removed to communicate with the groove 42. As a result, the through holes 4a,
4b, 4c, 4d, and 10 (see FIG. 2) are formed. Thereafter, the silicon wafer 35 is anodically bonded to the base 1 made of Pyrex glass.

Finally, as shown in FIG. 26, the scribe line is diced and cut, and the silicon wafer 35 and the pedestal 1 are cut into predetermined sizes as shown in FIG. At this time, as shown in FIG.
When the blade 66 of the dicing cut passes through the notch 65, the blade 66 of the dicing cut does not contact the aluminum 40. That is, since the blade 66 of the dicing cut passes through the cutout portion of the aluminum 40, no chips are generated.

As described above, in the present embodiment, a thin n-type epitaxial layer 36 (second-conductivity-type single-crystal semiconductor wafer) is formed on a p-type single-crystal silicon wafer 35 (first-conductivity-type single-crystal semiconductor substrate). (First step), aluminum 40 (conductive material) is formed on the epitaxial layer 36 (second step), and the single crystal silicon wafer 35 is placed in a KOH aqueous solution 76.
Is immersed, electrochemical etching is performed through the aluminum 40, and the electrochemical etching is terminated at an inflection point to a constant current after the peak of the conduction current, thereby removing a plurality of regions of the single crystal silicon wafer 35, Epitaxial layer 3
6 (third step), and the single crystal silicon wafer is left.
By cutting the c 35, the electrochemical etching
Of a plurality of regions of the single crystal silicon wafer 35 removed by
A plurality of chips containing any one of them was obtained (fourth step) . I I, it becomes possible to terminate the electrochemical etching to the optimum time.

[0034] Also, with the aluminum 40 and the n ⁺ diffusion layer 38 is disposed in a region to be a scribe cutting portion, since the n ⁺ diffusion layer 39 is disposed in the through hole forming area, aluminum 40, n ⁺ diffusion layer Due to the arrangement of 38 and 39, the area inside the chip does not increase.

As an application of the present embodiment, it may be determined in step 105 in FIG. 12 whether a predetermined time T (shown in FIG. 14) has elapsed. That is, the time T at which the inflection point changes to a constant current after the peak of the conduction current is experimentally obtained in advance, and the time T after the peak is obtained.
The electrochemical etching may be terminated when (for example, 5 minutes) has elapsed.

In FIG. 8, the notch 65 for passing the dicing cut blade 66 is not provided at the intersection of the aluminum 40, but the notch 65 for passing the dicing cut blade 66 is also provided at the intersection of the aluminum 40. May be provided. By doing so, the resistance is increased as compared with the above embodiment, but the dicing cut blade 66 is also formed at the intersection of the aluminum 40.
And the aluminum 40 do not come into contact with each other, thereby completely preventing the generation of chips.

Further, as shown in FIG. 27, the piezoresistive layers 13a and 13a of FIG.
3b, 14a, 14b, 15a, 15b, 16a, 16
An n ⁺ diffusion layer 43 may be formed in a region other than the region where b is formed, and the n ⁺ diffusion layer 39 and the aluminum 40 may be electrically connected. Further, as shown in FIG.
6, the piezoresistive layers 13a, 13 of FIG.
b, 14a, 14b, 15a, 15b, 16a, 16b
The aluminum 44 may be arranged in the region excluding the region where the wirings 18 and the region where the wirings 18 to 30 are formed to electrically connect the aluminum 41 and the aluminum 40. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

FIGS. 29 to 35 show the manufacturing process of the sensor. First, as shown in FIG. 29, an n ⁺ diffusion layer 46 is formed on a p-type single crystal silicon wafer 45 by a thermal diffusion method or an ion implantation method. After that, an n-type epitaxial layer 47 is formed on the single crystal silicon wafer 45.

Then, as shown in FIG. 30, ap ⁺ diffusion layer 48 is formed in the piezoresistive layer forming region of the epitaxial layer 47, and an n ⁺ diffusion layer 49 is formed on the scribe line. Further, aluminum 50 is arranged on n ⁺ diffusion layer 49. At this time, in the first embodiment, FIG.
As shown by 9, an aluminum 50 (metal thin film) having a cutout 65 for passing a dicing cut blade 66 is formed on a scribe line in the epitaxial layer 47.

Then, as shown in FIG. 31, a plasma nitride film (P-SiN)
53 is formed and predetermined patterning is performed by photoetching. And n on the scribe line
^{Using the} diffusion layer 49 as an electrode, a predetermined region of the single crystal silicon wafer 45 is removed by electrochemical etching to form a groove 51.
Is formed, and predetermined regions of the epitaxial layer 47 and the n ⁺ diffusion layer 46 are left.

The electrochemical etching at this time is also performed as shown in FIGS. 11, 12, 13, and 14 in the first embodiment. That is, electrochemical etching is performed through the aluminum 50 in a state where the single crystal silicon wafer 45 is immersed in an aqueous KOH solution, and the electrochemical etching is terminated at an inflection point to a constant current after the peak of the conduction current, thereby completing the single etching. A predetermined region of the crystalline silicon wafer 45 is removed so that a predetermined region of the epitaxial layer 47 remains.

Further, at the time of this electrochemical etching,
As shown in FIG. 31, since n ⁺ diffusion layer 46 exists between single crystal silicon wafer 45 and epitaxial layer 47, the current supplied from n ⁺ diffusion layer 49 is not impaired by the lateral resistance. It can be sufficiently supplied to the electrochemically etched surface. In other words, the lateral resistance of the epitaxial layer 47 is reduced, and a sufficient current is supplied to a portion at a distance from the voltage supply unit, and an anodic oxide film is formed.
Etching tends to stop.

Here, as shown in FIG. 32, when ap ⁺ diffusion layer 63 reaching the single crystal silicon wafer 45 is formed in the outer peripheral portion of the chip formation region in the epitaxial layer 47, the electrochemical etching shown in FIG. Sometimes, the PN junction leak generating portion (indicated by B in FIG. 33) on the outermost peripheral portion of the wafer and the portion to be etched are electrically insulated, thereby preventing the occurrence of leak and forming a uniform thin portion with high precision.

The high-concentration diffusion layer for preventing leakage is formed after the p ⁺ buried layer is formed on the p-type single-crystal silicon wafer 45 as described with reference to FIGS. 18 to 20 in the first embodiment. In the above, ap ⁺ diffusion layer may be formed on the n-type epitaxial layer 47 and may be formed by overlapping each other.

After that, as shown in FIG. 34, predetermined regions of the epitaxial layer 47 and the n ⁺ diffusion layer 46 are removed to communicate with the trench 51. Then, as shown in FIG. 35, a silicon wafer 4 is placed on a base 1 made of Pyrex glass.
5 is anodically bonded. Finally, the silicon wafer 45 and the pedestal 1 are formed into chips by cutting the scribe line.

At this time, as shown in FIG. 9 in the first embodiment, when the blade 66 of the dicing cut passes through the notch 65 of the aluminum 50, the blade 66 of the dicing cut
And the aluminum 50 do not contact.

As an application of this embodiment, the n ⁺ diffusion layer 4
6 is not formed on the single crystal silicon wafer 45,
The epitaxial layer may have a two-layer structure, an n ⁺ layer may be formed below the two layers, and the upper layer may be an n-type layer.

[0048]

As described in detail above, according to the present invention,
The end of etching is determined for each region to be etched.
In consideration of the surface distribution (thickness variation) of the thickness of the single crystal semiconductor substrate including the single crystal semiconductor film, it can be determined that the etching has been completed for all the chips, thereby completing the electrochemical etching at an optimum time. Can be done.

[Brief description of the drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plan view of a semiconductor acceleration sensor.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a plan view of a silicon chip showing a wiring pattern.

FIG. 5 is an electrical connection diagram showing connection of a resistance layer.

FIG. 6 is a sectional view illustrating a manufacturing process of the sensor according to the first embodiment.

FIG. 7 is a sectional view showing a manufacturing process of the sensor.

FIG. 8 is a plan view of an intersection of aluminum.

FIG. 9 is a sectional view taken along line DD of FIG. 8;

FIG. 10 is a sectional view showing a manufacturing process of the sensor.

FIG. 11 is a schematic view showing an electrochemical etching apparatus.

FIG. 12 is a flowchart for explaining an electrochemical etching operation.

FIG. 13 is a flowchart for explaining an electrochemical etching operation.

FIG. 14 is a time chart for explaining an electrochemical etching operation.

FIG. 15 is a plan view of a silicon wafer.

FIG. 16 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 17 is a cross-sectional view illustrating a manufacturing process of the sensor.

FIG. 18 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 19 is a sectional view showing a manufacturing process of the sensor.

FIG. 20 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 21 is a cross-sectional view for explaining electrochemical etching.

22 is a view as viewed in the direction of the arrow C in FIG. 21.

FIG. 23 is a side view of a platinum ribbon.

FIG. 24 is a sectional view showing a manufacturing process of the sensor.

FIG. 25 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 26 is a sectional view showing a manufacturing process of the sensor.

FIG. 27 is a sectional view showing an application example of the first embodiment.

FIG. 28 is a sectional view showing an application example of the first embodiment.

FIG. 29 is a sectional view illustrating a manufacturing process of the sensor according to the second embodiment.

FIG. 30 is a sectional view showing a manufacturing process of the sensor.

FIG. 31 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 32 is a cross-sectional view showing a manufacturing process of the sensor.

FIG. 33 is a cross-sectional view showing a manufacturing step of the sensor.

FIG. 34 is a cross-sectional view showing a manufacturing step of the sensor.

FIG. 35 is a cross-sectional view showing a manufacturing step of the sensor.

[Explanation of symbols]

35 p-type single crystal silicon wafer as first conductivity type single crystal semiconductor substrate 36 n-type epitaxial layer as second conductivity type single crystal semiconductor film 40 aluminum 76 KOH aqueous solution as conductive material

Claims (2)

(57) [Claims] A first step of forming a thin-film second-conductivity-type single-crystal semiconductor film on a first-conductivity-type single-crystal semiconductor substrate; and a second step of forming a conductive material on the single-crystal semiconductor film. performs a process, an electrochemical etching through the conductive material to a plurality of regions of the single crystal semiconductor substrate in a state where said immersing the single crystal semiconductor substrate in KOH etchant, the in each of said regions a single By terminating electrochemical etching at an inflection point to a constant current after a peak that draws a gentle curve of a conduction current caused by the plane distribution of the thickness of the crystal semiconductor substrate, in the plurality of regions of the single crystal semiconductor substrate , So as to leave a predetermined region of the single crystal semiconductor film
Having said predetermined region of the single crystal semiconductor film, wherein the single crystal semiconductor substrate is etched, corresponding to each of the regions
A third step of forming a thin portion; and cutting the single crystal semiconductor substrate to form the single bond.
A fourth step of obtaining a plurality of chips including any of the plurality of regions of the crystalline semiconductor substrate . 2. The semiconductor device according to claim 1, wherein the end of the etching in the third step is regarded as an inflection point after a lapse of a predetermined time after a peak that forms a gentle curve of the conduction current. Manufacturing method.