JP2876899B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art Conventionally, JP-A-61-30039 discloses an electrochemical etching method for forming a diaphragm in a diaphragm type silicon pressure sensor. This involves preparing a silicon substrate consisting of upper and lower two layers of different conductivity types, forming a high concentration diffusion layer on the surface of the silicon substrate as an electrode, removing the lower conductive layer by electrochemical etching, and removing the upper conductive layer. The diaphragm is formed while leaving the layer.

[0003]

However, when the chip is small, it is effective to improve the uniformity of the thickness of the thinned portion in the substrate. However, when the chip is large, the thickness within the chip is reduced. A problem occurs in the uniformity of the thickness. This problem becomes remarkable particularly when an attempt is made to use a thin epitaxial layer to form a thinner thin portion. This is because the lateral resistance of the upper conductor layer is increased, and a sufficient current is supplied to a portion distant from the voltage supply portion (for example, the center portion of the chip when an electrode is formed on the scribe line). This makes it difficult to form an anodic oxide film, and the etching does not stop.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the lateral resistance inside a chip during electrochemical etching.

[0005]

According to the first aspect of the present invention, there is provided the following:
A first step of forming a second conductivity type epitaxial layer on a conductivity type single crystal semiconductor substrate, and forming a second conductivity type high concentration diffusion layer on a scribe line in the epitaxial layer; the high concentration diffusion layer of the second conductivity type formed in a predetermined region of the epitaxial <br/> Le layers,
Outer peripheral portion of chip formation region in the epitaxial layer
In the first conductivity type leading to the single crystal semiconductor substrate.
A second step of forming a high-concentration diffusion layer for preventing cracking, and using the high-concentration diffusion layer on the scribe line as an electrode, removing a predetermined region of the single crystal semiconductor substrate by electrochemical etching, and removing a predetermined region of the epitaxial layer. a third step of leaving, by cutting the scribe line above is to its gist a method for manufacturing a semiconductor device and a fourth step of chips.

[0006] According to a second aspect of the invention, the first conductivity type monocrystalline semiconductor substrate, a first step of forming a second conductivity type epitaxial layer through the high-concentration layer of the second conductivity type, said epitaxial the high concentration diffusion layer of the second conductivity type formed on the scribe lines in the layer, put in the epitaxial layer
The single crystal semiconductor substrate at an outer peripheral portion of the chip forming region.
A second step of forming a high-concentration diffusion layer for preventing leakage of the first conductivity type reaching the plate, and using the high-concentration diffusion layer on the scribe line as an electrode by electrochemical etching of the single-crystal semiconductor substrate. The gist of the present invention is a method of manufacturing a semiconductor device including a third step of removing a predetermined region and leaving a predetermined region of the epitaxial layer, and a fourth step of cutting the scribe line to form a chip.

[0007]

According to the first aspect of the present invention, the first step is performed by the first step.
The conductivity type of the single crystal semiconductor substrate, is formed an epitaxial layer of a second conductivity type, the second step, high-concentration diffusion layer of the second conductivity type on the scribe line in the epitaxy <br/> turbocharger Le layer together are formed, high concentration diffusion layer of the second conductivity type is formed in a predetermined region of the epitaxial <br/> Takisharu layer within the chip, the chip formed territory in said epitaxial layer
A first conductor reaching the single crystal semiconductor substrate at an outer peripheral portion of the region.
A high-concentration diffusion layer for preventing electric leakage is formed. Then, as the electrode a high concentration diffusion layer on the scribe line by the third step, a predetermined region of the single crystal semiconductor substrate is removed by electrochemical etching, a predetermined region of the epitaxial layer is left. At this time, since the second conductivity type high concentration diffusion layer of the present in a given region of the epitaxial layer in the chip, sufficient current also lateral resistance is a distance from it a voltage supply unit lower portion of the epitaxial layer Supplied, an anodic oxide film is formed, and the etching is easily stopped.
In addition, the outside of the epitaxial layer during electrochemical etching
The periphery has the same potential as the single crystal semiconductor substrate, preventing leakage
Is done.

Further, the scribe line is cut into chips by a fourth step. In the invention according to claim 2, an epitaxial layer of the second conductivity type is formed on the single-crystal semiconductor substrate of the first conductivity type via the high-concentration layer of the second conductivity type in the first step . Forming a second conductive type high concentration diffusion layer on a scribe line in the epitaxial layer, forming a chip in the epitaxial layer;
A first portion extending to the single crystal semiconductor substrate at an outer peripheral portion of the region;
A conductive type high concentration diffusion layer for preventing leakage is formed. Then, as the electrode a high concentration diffusion layer on the scribe line by the third step, a predetermined region of the single crystal semiconductor substrate is removed by electrochemical etching, a predetermined region of the epitaxial layer is left. At this time, since the high concentration layer of the second conductivity type between the single crystal semiconductor substrate and the epitaxial layer is present, lateral resistance is also part of the distance from it a voltage supply unit low enough current epitaxial layer Supplied, an anodic oxide film is formed, and the etching is easily stopped.
In addition, the outside of the epitaxial layer during electrochemical etching
The periphery has the same potential as the single crystal semiconductor substrate, preventing leakage
Is done.

Further, the scribe line is cut into chips by a fourth step.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view of a semiconductor acceleration sensor. FIG. 2 is a plan view of the semiconductor acceleration sensor.
FIG. 3 shows an AA cross section of FIG. This sensor is used for an ABS system of a vehicle.

As shown in FIG. 1, a square plate-like silicon chip 2 is arranged on a square plate-like base 1 made of Pyrex glass. As shown in FIG. 2, the silicon chip 2 has a rectangular frame-shaped first
The first supporting portion 3 is formed using four sides of the silicon chip 2. Four through holes 4a, 4b, 4c, 4d penetrating vertically are formed inside the first support portion 3 of the silicon chip 2, and the four thin movable portions 5, 6, 7, 8 are thick. Are connected to each other. Further, in the inside of the first support portion 3 of the silicon chip 2, a through hole 1 penetrating vertically
0 is formed so as to surround the through holes 4a, 4b, 4c, 4d. The through-hole 10 defines a thick U-shaped second support portion 11 and a thick connecting portion 12.

That is, the second support portion 11 extends from the thick first support portion 3 joined to the pedestal 1, and the second support portion 11
And the movable parts 5 to 8 having a small thickness are extended. Further, the first support portion 3 and the second support portion 1 are formed by the through holes 10.
1 has a structure connected by a connection portion 12. Further, the second support portion 11 and the weight portion 9 are connected by the movable portions 5 to 8 as described above. The thickness of each of the movable parts 5 to 8 is about 5 μm, and each of the two piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1
6a and 16b are formed. As shown in FIG. 3, a concave portion 17 is formed in the center of the upper surface of the pedestal 1 so that when the acceleration is applied and the weight portion 9 is displaced, no contact is made.

FIG. 4 shows a wiring pattern made of aluminum on the surface of the silicon chip 2. In this embodiment, a wiring 18 for grounding, a wiring 19 for applying a power supply voltage, a wiring 20 for outputting a potential difference according to acceleration,
21 are formed. Another one for these wirings
A set of four wires is provided. That is, the ground wiring 22, the power supply voltage applying wiring 23, and the output wirings 24 and 25 for extracting a potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the power supply voltage application wiring 19, and the ground wiring 18 is arranged on the impurity diffusion layer 26 in a crossed state via a silicon oxide film. . Similarly,
The power supply voltage application wiring 23 is connected to the power supply voltage application wiring 19 via the impurity diffusion layer 27, and the ground wiring 22 is connected to the ground wiring 18 via the impurity diffusion layer 28. The output wiring 24 is the impurity diffusion layer 2
9 and connected to an output wiring 20. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wiring 1
Connection using 8 to 21 is performed.

Then, as shown in FIG. 5, each of the piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1
6a and 16b are electrically connected so that a Wheatstone bridge circuit is formed. Here, the terminal 31 is a ground terminal, the terminal 32 is a power supply voltage application terminal, and the terminals 33 and 34 are output terminals for extracting a potential difference according to the acceleration.

Next, a method of manufacturing the sensor will be described. FIG.
20 to 20 show the manufacturing process of the sensor. First, as shown in FIG. 6, a p-type single crystal silicon wafer 35 is prepared,
An n-type epitaxial layer 36 is formed on the surface. Then, as shown in FIG. 7, ap ⁺ diffusion layer 37 is formed in the piezoresistive layer forming region of the epitaxial layer 36, and an n ⁺ diffusion layer 38 is formed on the scribe line. Further, the through holes 4a, 4b, 4c, 4 shown in FIG.
An n ⁺ diffusion layer 39 is formed in the region where d and 10 are formed. Thereafter, aluminum 40 is arranged on n ⁺ diffusion layer 38 and a pad is extended from a part of aluminum 40. Furthermore, n
⁺ Aluminum 41 is arranged on diffusion layer 39.

Subsequently, as shown in FIG. 8, a plasma nitride film (P-SiN)
52 is formed, and predetermined patterning is performed by photoetching. Then, a current is supplied to the pad of aluminum 40 to perform electrochemical etching using the n ⁺ diffusion layer 38 as an electrode. At this time, since the n ⁺ diffusion layer 39 exists in a predetermined region of the epitaxial layer 36 in the chip,
The current supplied from the n ⁺ diffusion layer 38 can be sufficiently supplied to the electrochemically etched surface without being damaged by the lateral resistance. That is, the epitaxial layer 36
, The lateral resistance decreases, and a sufficient current is supplied to a portion at a distance from the voltage supply unit, an anodic oxide film is formed, and the etching is easily stopped.

Here, as shown in FIGS. 9 and 10, when ap ⁺ diffusion layer 54 reaching the single crystal silicon wafer 35 is formed at the outer peripheral portion of the chip formation region in the epitaxial layer 36, the electric potential shown in FIG. During chemical etching, the PN junction leak generating portion (indicated by B in FIG. 11) on the outermost periphery of the wafer and the portion to be etched are electrically insulated, preventing the occurrence of leak and forming a uniform thin portion with high precision. . That is, when the p ⁺ diffusion layer 54 is not formed, since the potential at the outermost peripheral portion of the epitaxial layer 36 is the same as the central portion of the epitaxial layer 36, leakage occurs at the portion B in FIG. On the other hand, by forming the p ⁺ diffusion layer 54, the outermost peripheral portion of the epitaxial layer 36 has the same potential as the silicon wafer 35, and no leak occurs.

Incidentally, the high-concentration diffusion layer for preventing leakage may be formed as follows. First, as shown in FIG. 12, ap ⁺ buried layer 55 is formed on the surface of a p-type single crystal silicon wafer 35, and then an n-type epitaxial layer 3 is formed on the surface of the wafer.
6 is formed. Then, as shown in FIG. 13, ap ⁺ diffusion layer 56 is formed in the epitaxial layer 36 by heat treatment in an oxygen atmosphere, and the two layers 55 and 56 are overlapped with each other. Thereafter, electrochemical etching is performed as shown in FIG. This method is advantageous in that the time for deeply diffusing the p ⁺ diffusion layer down to the silicon wafer can be reduced particularly when the epitaxial layer is thick.

Further, at the time of electrochemical etching, FIG.
As shown in FIG. 16, a platinum ribbon 59 is sandwiched between a support substrate 57 made of alumina and a silicon wafer 58, and the silicon wafer 58 and the support substrate 57 are fixed with a resin (for example, heat-resistant wax) 60. The resin 60 causes the silicon wafer 58 and the platinum ribbon 59 to etch with an etchant (eg,
33 wt% KOH solution, 82 ° C) protected from 61. As shown in FIG. 17, the platinum ribbon 59 has a band-like shape, and its distal end has a waveform. The thickness of the corrugated portion of the platinum ribbon 59 is W when no external force is applied. However, when the platinum ribbon 59 is fixed between the support substrate 57 and the silicon wafer 58 shown in FIG. The thickness of the corrugated portion is compressed to W or less, and a force acts to push the silicon wafer 58 and the support substrate 57 apart. Therefore, in this state, electrical contact between the platinum ribbon 59 and the silicon wafer 58 is reliably ensured. After the electrochemical etching, the silicon wafer 58 or the like is immersed in a solvent (for example, trichloroethane) 62 to dissolve the resin 60 as shown in FIG.
Take out 8. During the immersion of the silicon wafer 58, the corrugated portion of the platinum ribbon 59 causes the silicon wafer 58
And the support substrate 57 is being spread.
The gap between the silicon wafer 58 and the support substrate 57 is widened. Therefore, in this part, the solvent 6
The circulation speed of 2 is increased, and fresh solvent 62 is supplied to the stripped portion, so that the stripping time can be shortened. In other words, if a platinum ribbon having a flat plate shape is used instead of making the platinum ribbon 59 into a corrugated state by making a waveform, the support substrate 57 will be weighted by the weight of the silicon wafer 58 during the step of removing the resin 60.
The gap between the silicon wafer 58 and the silicon wafer 58 becomes narrower, but the peeling time can be reduced by arranging the platinum ribbon 59 in a corrugated state in a waveform.

By such electrochemical etching, as shown in FIG. 8, a predetermined region of the single crystal silicon wafer 35 is removed to form a groove 42 and a predetermined region of the epitaxial layer 36 remains. Parts 5,6
7, 8 (see FIG. 2) are formed.

Then, as shown in FIG. 19, a predetermined region (n ⁺ diffusion layer 39) of the epitaxial layer 36 is removed to communicate with the groove 42. As a result, the through holes 4a, 4b, 4
c, 4d, and 10 (see FIG. 2) are formed. Thereafter, the silicon wafer 35 is anodically bonded to the base 1 made of Pyrex glass. Finally, as shown in FIG. 20, dicing cuts are made on the scribe line, and the silicon wafer 35 and the pedestal 1 are cut into predetermined sizes as shown in FIG.

As described above, in the present embodiment, the n-type epitaxial layer 36 is formed on the p-type single-crystal silicon wafer 35 (first-conductivity-type single-crystal semiconductor substrate) (first step). An n ⁺ diffusion layer 38 (second conductivity type high concentration diffusion layer) is formed on the scribe line at 36, and an n ⁺ diffusion layer 39 (second conductivity type high concentration diffusion layer) is formed in a region where the epitaxial layer 36 is removed in the chip. Concentration diffusion layer), and the chip in the epitaxial layer 36 is formed.
Single crystal silicon wafer 35 at the outer peripheral portion of the
To form a p ⁺ diffusion layer 54 reaching the (second step). Then, using the n ⁺ diffusion layer 38 on the scribe line as an electrode, the single crystal silicon wafer 3 is electrochemically etched.
The predetermined region of No. 5 was removed to leave a predetermined region of the epitaxial layer 36 (third step), and the scribe line was cut to form a chip (fourth step).

As a result, in the third step, since the n ⁺ diffusion layer 39 is present in a predetermined region of the epitaxial layer 36 in the chip, the lateral resistance of the epitaxial layer 36 is reduced, and the portion located at a distance from the voltage supply unit is reduced. Current is also supplied sufficiently to form an anodic oxide film, and the etching is easily stopped.

Also, n⁺When the diffusion layer 38 is
And n ⁺Diffusion layer 39 penetrates
Since it is arranged in the hole forming area, n⁺Diffusion layer 38,3
9 does not increase the chip area.
No.

As an application example of this embodiment, as shown in FIG. 21, the piezoresistive layers 13a, 13b, 14a, 14b, 1b of FIG.
An n ⁺ diffusion layer 43 may be formed in a region excluding the regions where 5a, 15b, 16a, and 16b are formed, and n ⁺ diffusion layer 39 and aluminum 40 may be electrically connected. Further, as shown in FIG. 22, the piezoresistive layers 13a, 13b, 14a, 14b, 15b of FIG.
a, 15b, 16a, 16b forming region and wiring 1
The aluminum 44 may be arranged in a region excluding the formation regions 8 to 30 to electrically connect the aluminum 41 and the aluminum 40. (Second Embodiment) Next, a second embodiment will be described focusing on differences from the first embodiment.

FIGS. 23 to 29 show a manufacturing process of the sensor. First, as shown in FIG. 23, an n ⁺ diffusion layer 46 is formed on a p-type single crystal silicon wafer 45 by a thermal diffusion method or an ion implantation method. After that, an n-type epitaxial layer 47 is formed on the single crystal silicon wafer 45.

Then, as shown in FIG. 24, ap ⁺ diffusion layer 48 is formed in the piezoresistive layer forming region of the epitaxial layer 47, and an n ⁺ diffusion layer 49 is formed on the scribe line. Further, aluminum 50 is arranged on n ⁺ diffusion layer 49. Then, as shown in FIG. 25, a plasma nitride film (P-S
iN) 53 is formed and predetermined patterning is performed by photoetching. Using the n ⁺ diffusion layer 49 on the scribe line as an electrode, a predetermined region of the single crystal silicon wafer 45 is removed by electrochemical etching to form a groove 51, and a predetermined region of the epitaxial layer 47 and the n ⁺ diffusion layer 46 are formed. Leave.

At this time, since the n ⁺ diffusion layer 46 exists between the single crystal silicon wafer 45 and the epitaxial layer 47, the current supplied from the n ⁺ diffusion layer 49 can be sufficiently prevented from being impaired by the lateral resistance. Can be supplied to the electrochemically etched surface. In other words, the lateral resistance of the epitaxial layer 47 is reduced, and a sufficient current is supplied to a portion at a distance from the voltage supply unit, an anodic oxide film is formed, and the etching is easily stopped.

Here, as shown in FIG. 26, when ap ⁺ diffusion layer 63 reaching the single crystal silicon wafer 45 is formed in the outer peripheral portion of the chip formation region in the epitaxial layer 47, the electrochemical etching shown in FIG. Sometimes, the PN junction leak generating portion (indicated by B in FIG. 27) at the outermost portion of the wafer and the portion to be etched are electrically insulated, thereby preventing the occurrence of leak and forming a uniform thin portion with high precision.

The high-concentration diffusion layer for preventing leakage is formed after the p ⁺ buried layer is formed on the p-type single crystal silicon wafer 45 as described with reference to FIGS. 12 to 14 in the first embodiment. In the above, ap ⁺ diffusion layer may be formed on the n-type epitaxial layer 47 and may be formed by overlapping each other.

After that, as shown in FIG. 28, predetermined regions of the epitaxial layer 47 and the n ⁺ diffusion layer 46 are removed to communicate with the trench 51. Then, as shown in FIG. 29, a silicon wafer 4 is placed on a base 1 made of Pyrex glass.
5 is anodically bonded. Finally, the silicon wafer 45 and the pedestal 1 are formed into chips by cutting the scribe line.

As described above, in this embodiment , the n ⁺ diffusion layer 46 (the second conductivity type high concentration layer) is formed on the p type single crystal silicon wafer 45 (the first conductivity type single crystal semiconductor substrate). To form an n-type epitaxial layer 47 (first step), and n ⁺
A diffusion layer 49 (a second-conductivity-type high-concentration diffusion layer) is formed .
In the outer peripheral portion of the chip formation region in the
P ⁺ diffusion layer 63 reaching single crystal silicon wafer 47
Was formed ( second step). Then, using n ⁺ diffusion layer 49 on the scribe line as an electrode, a predetermined region of single crystal silicon wafer 45 is removed by electrochemical etching, and a predetermined region of epitaxial layer 47 and n ⁺ diffusion layer 46 is left (third step). Then, the scribe line was cut into chips (fourth step).

As a result, in the third step, since the n ⁺ diffusion layer 46 exists between the single crystal silicon wafer 45 and the epitaxial layer 47, the lateral resistance of the epitaxial layer 47 is reduced, and the distance from the voltage supply unit is reduced. A sufficient current is supplied to a certain portion, an anodic oxide film is formed, and the etching is easily stopped.

As an application of this embodiment, the n ⁺ diffusion layer 4
6 is not formed on the single crystal silicon wafer 45,
The epitaxial layer may have a two-layer structure, an n ⁺ layer may be formed below the two layers, and the upper layer may be an n-type layer.

In each of the above embodiments, the conductivity type may be reversed.

[0037]

As described in detail above, according to the present invention,
An excellent effect of reducing the lateral resistance inside the chip during electrochemical etching is exhibited.

[Brief description of the drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plan view of a semiconductor acceleration sensor.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a plan view of a silicon chip showing a wiring pattern.

FIG. 5 is a diagram showing connection of a resistance layer.

FIG. 6 is a diagram illustrating a manufacturing process of the sensor according to the first embodiment.

FIG. 7 is a diagram showing a manufacturing process of the sensor.

FIG. 8 is a diagram showing a manufacturing process of the sensor.

FIG. 9 is a plan view of a silicon wafer.

FIG. 10 is a diagram showing a manufacturing process of the sensor.

FIG. 11 is a diagram showing a manufacturing process of the sensor.

FIG. 12 is a diagram showing a manufacturing process of the sensor.

FIG. 13 is a diagram showing a manufacturing process of the sensor.

FIG. 14 is a diagram showing a manufacturing process of the sensor.

FIG. 15 is a diagram for explaining electrochemical etching.

16 is a view as viewed in the direction of the arrow C in FIG.

FIG. 17 is a view showing a platinum ribbon.

FIG. 18 is a diagram showing a manufacturing process of the sensor.

FIG. 19 is a diagram showing a manufacturing process of the sensor.

FIG. 20 is a diagram showing a manufacturing process of the sensor.

FIG. 21 is a sectional view showing an application example of the first embodiment.

FIG. 22 is a sectional view showing an application example of the first embodiment.

FIG. 23 is a diagram illustrating a manufacturing process of the sensor according to the second embodiment.

FIG. 24 is a diagram showing a manufacturing process of the sensor.

FIG. 25 is a diagram showing a manufacturing process of the sensor.

FIG. 26 is a diagram showing a manufacturing process of the sensor.

FIG. 27 is a diagram showing a manufacturing process of the sensor.

FIG. 28 is a diagram illustrating a manufacturing process of the sensor.

FIG. 29 is a diagram illustrating a manufacturing process of the sensor.

[Explanation of symbols]

35 p-type single crystal silicon wafer (first conductivity type single crystal semiconductor substrate) 36 n-type epitaxial layer (second conductivity type epitaxial layer) 38 n ⁺ diffusion layer (second conductivity type high concentration diffusion layer) 39 n ⁺ diffusion layer (second conductivity type high concentration diffusion layer) 45 p-type single crystal silicon wafer (first conductivity type single crystal semiconductor substrate) 46 n ⁺ diffusion layer (second conductivity type high concentration layer) 47 n-type epitaxial layer (second conductivity type epitaxial layer) 49 n ⁺ diffusion layer (second conductivity type high concentration diffusion layer)

Claims (2)

(57) [Claims] 1. A first step of forming a second conductivity type epitaxial layer on a first conductivity type single crystal semiconductor substrate; and forming a second conductivity type high concentration diffusion layer on a scribe line in the epitaxial layer. and forming, to form a high-concentration diffusion layer of the second conductivity type in a predetermined region of the epitaxial layer in the chip, Ji in said epitaxial layer
In the outer peripheral portion of the tip formation region, the single crystal semiconductor substrate
Forming a first conductivity type high concentration diffusion layer for preventing leakage, and a high concentration diffusion layer on the scribe line as an electrode.
Electrochemical etching by removing a predetermined region of the single crystal semiconductor substrate, comprising: the third step to leave a predetermined region of the epitaxial layer, and a fourth step of chips by cutting the scribe line on Manufacturing method of a semiconductor device. To 2. A first conductivity type monocrystalline semiconductor substrate, a first step of forming a second conductivity type epitaxial layer through the high-concentration layer of the second conductivity type, a scribe line on in the epitaxial layer the high concentration diffusion layer of the second conductivity type formed in said epitaxial
The single crystal at the outer periphery of the chip forming region in the layer
High-concentration diffusion for preventing leakage of the first conductivity type reaching the semiconductor substrate
A second step of forming a layer, and using a high concentration diffusion layer on the scribe line as an electrode.
A third step of removing a predetermined area of the single crystal semiconductor substrate by electrochemical etching to leave a predetermined area of the epitaxial layer; and a fourth step of cutting the scribe line to form a chip. Manufacturing method of a semiconductor device.