JP3337110B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for mass production and capable of reducing the manufacturing cost, and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 21 is an explanatory view of the structure of a conventional semiconductor device generally used in the prior art, which is disclosed, for example, in Japanese Patent Application Laid-Open No. Hei 5-288624. In this case, the semiconductor device is used as a sensor part of a differential pressure measuring device. 22 is a sectional view taken along line AA of FIG. 21, and FIG. 23 is a sectional view taken along line BB of FIG.

In FIG. 1, reference numeral 21 denotes a first chamber formed of a predetermined gap for forming a diaphragm 23 in a silicon substrate 22, and is formed of a gap with a very small interval. Reference numeral 24 denotes a first communication hole provided in the silicon substrate 22 and having one end communicating with the first chamber 21.

[0004] Reference numeral 25 denotes a concave portion provided on the surface of the diaphragm 23 opposite to the surface on which the first chamber 21 is provided, and has a very small depth. Reference numeral 26 denotes a ring-shaped chamber provided on the silicon substrate 22 and communicating with the concave portion 25 and surrounding the diaphragm 23 in a ring shape except for the first communication hole 24.

Reference numeral 27 denotes a strain detecting element provided on the concave portion 25 side of the diaphragm 23. 28 is the silicon substrate 2
One surface is connected to the surface provided with the two concave portions 25 and the concave portion 25 is formed.
And a support substrate constituting the second chamber 29.

As shown in FIG. 24, reference numeral 31 denotes a wiring composed of a conductor formed by mixing impurities on the bonding surface of the silicon substrate 22 with the supporting substrate 28 and having one end connected to the strain detecting element 27. 32 is a supporting substrate 28 as shown in FIG.
The electrode is provided on the side of the bonding surface with the silicon substrate 22 and has one end connected to the wiring 31.

Reference numeral 33 denotes a groove provided near the electrode 32 on the silicon substrate 22, as shown in FIG. Groove 3
3 imparts an appropriate spring property to a contact portion of the silicon substrate 22 with the electrode 32, and stably maintains the contact between the electrode 32 and the wiring 31.

[0010] As shown in FIG. 25, reference numeral 41 denotes a first substrate provided on the silicon substrate 22 for removing dust in a fluid as a pressure medium.
This is a filter section for preventing the mixture into the chamber 21 or the second chamber 29. In this case, two are provided.

The gap d of the filter portion 41 is formed sufficiently small by a semiconductor process to prevent dust from entering. That is, the gap d of the filter section 41 is configured to satisfy d ≦ AB when the gap between the first chambers 21 is A and the displacement of the diaphragm 23 is B.

One of the filter portions 41 is provided with the first communication hole 2.
4 is connected. The other of the filter unit 41 is the second
It communicates with the second chamber 29 through the communication hole 42. 51
Is a first pressure guiding hole which is provided on the support substrate 28, communicates with one of the filter portions 41, and has the other end open to the atmosphere.

Reference numeral 52 denotes a second pressure guiding hole which is provided on the support substrate 28, communicates with the other side of the filter section 41, and has the other end open to the atmosphere. 53 is an overhang connected to the ring-shaped chamber 26. When a high pressure is applied, the overhang 53 receives a high pressure at the overhang 53 and
The structure is such that a large stress does not occur at the joint between the substrate and the support substrate 28.

In the above configuration, the high pressure side measurement pressure is applied to the first chamber 21 and the low pressure side measurement pressure is applied to the second chamber 29. As a result, the silicon diaphragm 23 is distorted in accordance with the pressure difference between the high pressure side and the low pressure side, and the amount of this distortion is electrically detected by the distortion detecting element 27, and a signal is taken out to the outside via the wiring 31 and the electrode 32. Then, the differential pressure is measured.

[0013] When an excessive pressure is applied to the first chamber 21, the diaphragm 23 is backed up by the wall of the second chamber 29. On the other hand, when an excessive pressure is applied to the second chamber 29, the diaphragm 23 is backed up by the wall of the first chamber 21.

Such an apparatus is manufactured as shown in FIGS. (1) As shown in FIG. 26, a required portion 102 of an SOI wafer 101 is etched by RIE to etch silicon 104, and a silicon oxide 10 is etched by hydrofluoric acid-based etchant.
3 is etched to form silicon oxide 103 and silicon 1
04 is etched. In this case, silicon oxide 10
3 about 1 μm, silicon 104 about 0.5 μm thick
m, the thickness of the silicon of the substrate is about 600 μm. FIG.
FIG. 27 is a plan view of FIG. 26.

(2) As shown in FIG. 28, the SOI wafer 1
On the surface of No. 01, an epitaxial growth layer 105 is grown. In this case, the thickness of epitaxial growth layer 105 is about 70 μm.

(3) As shown in FIG. 29, the surface of the epitaxial growth layer 105 is mirror-polished by polishing. In this case, about 50 μm is removed. This step determines the thickness of the diaphragm 23. (4) As shown in FIG. 30, the epitaxial growth layer 105
Is etched by RIE etching to form a recess 106. The gap of the second chamber 29 that determines the movable range of one side of the diaphragm 23 is determined by the recess 106.

(5) As shown in FIG.
A hole 107 for etching the silicon oxide 103 is formed.
It is formed by RIE etching or etching with potassium hydroxide.

(6) As shown in FIG. 32, the silicon oxide 103 is etched with a hydrogen fluoride aqueous solution or a hydrogen fluoride gas. (7) As shown in FIG. 33, the silicon substrate 22 is anodically bonded to the Pyrex glass support substrate.

As a result, (1) Since the outside of the differential pressure sensor may be at atmospheric pressure, a special pressure-resistant container is not required. (2) A high-withstand-voltage hermetic seal terminal for extracting an electric signal to the outside is unnecessary.

(3) Since the silicon wafer can be processed from one side, the forming process is simplified. (4) Since the sensor itself has an overpressure protection mechanism,
No extra pressure protection mechanism is required.

(5) Since the diaphragm 23 is surrounded by the first chamber 21, the second chamber 29 and the ring-shaped chamber 26, it is possible to effectively prevent disturbance distortion from being transmitted to the diaphragm 23. A semiconductor differential pressure measuring device having good noise resistance can be obtained.

[0022]

However, in such a semiconductor device and its manufacturing method, since the electrode 32 from the silicon substrate 22 needs to be provided on the support substrate 28, the electrode 32 between the silicon substrate 22 and the support substrate 28 must be provided. It is necessary to increase the area of the support substrate 28 at the bonding surface by changing the size of the area at the bonding surface.

In this case, the silicon substrate 22 and the support substrate 2
If each is cut into chips and then individually anodically bonded, mass productivity is poor and the cost is high. If the silicon substrate 22 and the support substrate 28 can be anodically bonded to each other in a wafer state and cut out into individual chips by dicing, the semiconductor process can be used to the end, mass productivity can be improved, and manufacturing costs can be reduced. .

The present invention solves this problem. An object of the present invention is to provide a semiconductor device suitable for mass production and capable of reducing the manufacturing cost, and a method for manufacturing the same.

[0025]

In order to achieve this object, the present invention provides a semiconductor device comprising: (1) a semiconductor substrate on which a semiconductor element is formed; and one surface of the semiconductor substrate having an area larger than that of the semiconductor substrate. A semiconductor device comprising: a joined support substrate; and an electrode for external connection of the semiconductor element, which is provided on the one surface of the support substrate outside a joint portion between the support substrate and the semiconductor substrate. A semiconductor wafer composed of a set of substrates, a support substrate original plate composed of an aggregate of a plurality of the support substrates, one surface of which is joined to one surface of the semiconductor wafer, and the electrode provided on the one surface of the support substrate original plate; A bonding prevention groove provided on the semiconductor wafer opposite to the electrode, and a direction perpendicular to the bottom surface of the bonding prevention groove along both edges of the bonding prevention groove and facing the electrode, respectively. Intersection between the deep groove and the shallow groove provided at predetermined intervals on the semiconductor wafer
After a plurality of electrode dicing prevention grooves formed of continuous grooves are provided, only the semiconductor wafer is diced along the electrode dicing prevention grooves, and the electrode facing portions of the semiconductor wafer facing the electrodes are removed. And a semiconductor device formed by dicing into individual chips. (2) and the semiconductor substrate which is built semiconductor devices, semiconductive
Is joined to one surface of the body substrate with one surface having an area larger than the one surface.
Support substrate, and a joint between the support substrate and the semiconductor substrate
The semiconductor element provided on the one surface of the support substrate
Of a semiconductor device having an external connection electrode
In the manufacturing method, it has the following steps
A method for manufacturing a semiconductor device. (A) forming a plurality of the semiconductor substrates on a semiconductor wafer;
A semiconductor substrate forming step. (B) forming a junction preventing groove at a predetermined position on the semiconductor wafer;
Bonding preventing groove forming step. (C) along both edges of the joint preventing groove and
Provided on each of the semiconductor wafers in a direction perpendicular to the bottom surface
From a continuous groove of alternating deep and shallow grooves at predetermined intervals.
To form an electrode dicing prevention groove formed
Polar dicing prevention groove forming step. (D) The electrode dicing prevention groove is formed on one surface of the support substrate original plate.
Electrode forming process to form electrodes so as to face each other
About. (E) the electrode dicing prevention groove is provided on each of the electrodes.
The semiconductor wafer is placed on one surface of the supporting substrate original plate so as to face the same.
A joining step of joining the surfaces of the EHA on the side of the joining preventing grooves. (F) removing the semiconductor wafer from the semiconductor wafer side;
In the deep groove part, the electrode dicing prevention groove is reached and the shallow groove part is reached.
In order to avoid the electrode dicing prevention groove,
Semiconductor dicing process. (G) Removal for removing the electrode facing portion of the semiconductor wafer
Process. (H) removing the semiconductor wafer from the support base plate;
Dicing the central part of the
Support substrate original plate dicing for separating into semiconductor devices
About. It was adopted.

[0026]

In the above configuration and manufacturing method, a plurality of semiconductor substrates are formed on a semiconductor wafer. A bonding prevention groove is formed at a predetermined position on the semiconductor wafer. Electrode dicing prevention grooves provided on the semiconductor wafer are formed along both edges of the bonding prevention groove and in a direction perpendicular to the bottom surface of the bonding prevention groove.

Electrodes are formed on one surface of the original supporting substrate so as to face the electrode dicing prevention grooves. The surface of the semiconductor wafer on the bonding prevention groove side is joined to one surface of the supporting substrate original plate such that the electrode dicing prevention grooves face the electrodes.

The semiconductor wafer is diced from the semiconductor wafer side to the electrode dicing prevention groove. The portion of the semiconductor wafer facing the electrode in the joint preventing groove is removed. Almost the central portion of the supporting substrate original plate from which the semiconductor wafer has been removed is diced to separate each chip into semiconductor devices of the present invention. Hereinafter, a detailed description will be given based on embodiments.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a main part of an embodiment of the present invention. In the figure, the configuration of the same symbol as in FIG. 21 represents the same function. Hereinafter, only differences from FIG. 21 will be described.

Reference numeral 61 denotes a set of a plurality of semiconductor substrates 22a, and in this case, a semiconductor wafer using an SOI wafer. Reference numeral 62 denotes one surface of the semiconductor wafer 6.
1 is a support substrate original plate which is anodically bonded to one surface and is composed of a set of a plurality of support substrates 28a.

Reference numeral 63 denotes an electrode for external connection of the semiconductor element 27, which is arranged on one surface of the support substrate original plate 62. The semiconductor element 27, in this case, a piezoresistive element as a strain detecting element is used.

The semiconductor element 27 may use a vibrating beam used as a strain detecting element. Also, a semiconductor element such as an IC circuit may be used. in short,
Any semiconductor element may be used. Numeral 64 denotes bonding prevention grooves provided on the semiconductor wafer 61 so as to face the electrodes 63, respectively. In the portion of the joining prevention groove 64, the support substrate original plate 62
Bonding between the semiconductor wafer 61 and the semiconductor wafer 61 is prevented.

Numeral 65 is along both edges of the joint preventing groove 64,
Further, there are a plurality of electrode dicing prevention grooves provided on the semiconductor wafer 61 in a direction orthogonal to the bottom surface of the bonding prevention groove 64, respectively, facing the electrodes 63.

Reference numeral 60 denotes an individual chip after the semiconductor wafer 61 is diced 71 along the electrode dicing prevention groove 65 and the portion of the semiconductor wafer 61 facing the electrode 63 facing the electrode 63 is removed. Is a semiconductor device of the present invention formed by dicing 72 in FIG.

FIG. 2 is an explanatory view of a single structure of the semiconductor device 60 of the present invention. In the figure, reference numeral 65a denotes a depression caused by the electrode dicing prevention groove 65.

Such an apparatus is manufactured as shown in FIGS. In this case, the portion used as the sensor portion of the differential pressure measuring device shown in the conventional example shown in FIG. 21 is also manufactured in parallel, but the formation of the sensor portion of the differential pressure measuring device is as follows. The conventional example shown in FIG. 21 has already been described, and will not be described here.

(A) As shown in FIG.
In step 1, a plurality of predetermined semiconductor elements are formed. (B) As shown in FIG. 4, the silicon 203 and the insulator 204 on the insulator of the SOI wafer 201 are removed by etching, leaving a predetermined portion 202 of the SOI wafer 201.

(C) As shown in FIG. 5, the SOI wafer 20
The epitaxial growth layer 205 is grown on the surface of the substrate 1. (D) As shown in FIG. 6, the surface of the epitaxial growth layer 205 is flattened.

(E) As shown in FIG. 7, a junction preventing groove 206 is formed at a predetermined position on the surface of the epitaxial growth layer 205. (F) As shown in FIG. 8, along both edges of the joint preventing groove 206 and in a direction orthogonal to the bottom surface of the joint preventing groove 206,
The electrode dicing prevention grooves 207 provided on the SOI wafer 201 are formed so as to reach the insulator 204 of the SOI wafer.

In this case, the electrode dicing prevention groove 207 is used.
As shown in FIG. 9, which is a cross section taken along the line EE in FIG. 8, the groove is formed by alternately continuous grooves of a deep groove 2071 and a shallow groove 2072 at a predetermined interval. In this case, the depths of the shallow groove 2072 and the junction preventing groove 206 are the same.

(G) As shown in FIG. 10, the insulator 204 of the SOI wafer is removed by etching via the electrode dicing prevention groove 207. (H) As shown in FIG. 11, the electrodes 302 are formed on one surface of the support substrate original plate 301 so as to face the electrode dicing prevention grooves 207, respectively.

(I) As shown in FIG.
The SOI wafer 201 is placed on one surface of the support substrate original plate 301 such that the electrode dicing prevention grooves 207 face each other.
Are bonded together on the side of the bonding prevention groove 206. In this case, anodic bonding is employed.

(J) As shown in FIG. 13, the SOI wafer 2
01 is diced 401 from the SOI wafer 201 side until it reaches the electrode dicing prevention groove 207. In this case, in the deep groove 2071 portion, the electrode dicing prevention groove 2 is formed.
In the shallow groove 2072, dicing 401 is performed so as not to reach the electrode dicing prevention groove 207.

In this case, as shown in FIG. 14 which is a cross section taken along line FF of FIG.
1 and cut.

On the other hand, the dicing 40
1, the part is cut, and the hatched part remains without being cut. In this portion, the silicon piece is barely connected to the portion joined to the support substrate original plate 301. That is, it is in a perforated state. By doing so, it is possible to prevent the silicon piece from being cut off during the dicing 401 and damaging the blade.

(K) As shown in FIG.
Opposing portions 2 of electrodes 302 of six SOI wafers 201
011 is removed. That is, after the silicon dicing 401, the silicon piece portion connected by the shallow groove portion 2072 can be easily broken and removed by applying a small force.

In this case, the burrs H remain in the portions connected by the shallow groove portions 2072. However, as shown in FIG. 16, this portion is previously formed on individual chips such as between a chip and a chip. It should be set at a place where it does not affect. In this case, the reliability of the electrical insulation can be ensured.

That is, such burrs H
This is because, if it comes into contact with 2, it may cause a short circuit or the like.
FIG. 17 is an overall view of the wafer, and FIG. 18 is an enlarged view of a two-dot chain line portion I in FIG. Deep groove portion 2071 shown in FIG.
The shallow groove portion 2072 corresponds to the deep groove portion 2071 and the shallow groove portion 2072 in FIG.

(L) As shown in FIG.
01, the part 2011 from which the SOI wafer 201 has been removed
Is divided by dicing 402 into semiconductor devices of the present invention for each chip.

[0050]

[0051]

[0052]

[0053] As a result, since the depth of the electrode dicing preventing groove 65 of alternating continuous groove between the deep groove 2071 and the shallow groove 2072 at a predetermined interval, when it reaches the deep groove 2071, if stopped semiconductor dicing 71 As a result, a semiconductor device in which the dicing depth can be easily controlled is obtained, and a perforated structure is provided.
A semiconductor device from which 011 can be easily removed is obtained.

[0054]

FIG. 20 is an explanatory view of a main part configuration of another embodiment of the present invention. In the present embodiment, the electrode dicing prevention groove 81 extends over the buried silicon oxide layer 204,
Furthermore, it is a deeply constructed one. When the electrode dicing prevention groove 81 is composed of the deep groove 811 and the shallow groove 812,
Since the step between the deep groove 811 and the shallow groove 812 can be increased, the margin of the depth of the semiconductor dicing 71 can be increased, and the depth of the semiconductor dicing 71 can be easily controlled.

[0056]

[0057]

[0058]

[0059]

As described [Effect Invention above in detail, according to the present invention, the electrode dicing groove preventing. Thus of alternating continuous groove between the deep groove and the shallow groove at predetermined intervals, has reached the deep groove at that point, since the semiconductor dicing may be stopped, dicing depth control easy semiconductor device is obtained, and, since the perforation structure, dicing
In the middle of the ring 401, the silicon piece is cut off,
Thus, a semiconductor device that can prevent damage to the electrode and can easily remove the electrode-facing portion can be obtained.

[0060]

[0061]

Therefore, according to the present invention, it is suitable for mass production,
A semiconductor device and a method for manufacturing the same that can reduce the manufacturing cost can be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a main part configuration of an embodiment of the present invention.

FIG. 2 is an explanatory view of a single structure of a semiconductor device of the present invention.

FIG. 3 is an explanatory view of a semiconductor substrate forming step of FIG. 1;

FIG. 4 is an explanatory view of an etching step in FIG. 1;

FIG. 5 is an explanatory view of an epitaxial growth step of FIG. 1;

FIG. 6 is an explanatory view of a flattening step of FIG. 1;

FIG. 7 is an explanatory view of a bonding prevention groove forming step of FIG. 1;

FIG. 8 is an explanatory diagram of an electrode dicing prevention groove forming step of FIG. 1;

FIG. 9 is a sectional view taken along the line EE in FIG. 8;

FIG. 10 is an explanatory view of the insulator etching removing step of FIG. 1;

FIG. 11 is an explanatory diagram of the electrode forming step of FIG. 1;

FIG. 12 is an explanatory view of a joining step in FIG. 1;

FIG. 13 is an explanatory view of the semiconductor dicing step of FIG. 1;

FIG. 14 is a sectional view taken along line FF of FIG. 13;

FIG. 15 is an explanatory diagram of a step of removing an electrode-facing portion in FIG. 1;

FIG. 16 is an explanatory diagram of FIG.

FIG. 17 is an explanatory diagram of FIG.

FIG. 18 is an explanatory diagram of FIG.

FIG. 19 is an explanatory diagram of a dicing step of the support substrate original plate of FIG. 1;

FIG. 20 is an explanatory diagram of a main part configuration of another embodiment of the present invention.

FIG. 21 is an explanatory diagram of a configuration of a conventional example generally used in the related art.

FIG. 22 is a sectional view taken along line AA of FIG. 21.

FIG. 23 is a sectional view taken along line BB of FIG. 21;

FIG. 24 is a detailed explanatory diagram of a main part of FIG. 21;

FIG. 25 is a detailed explanatory view of a main part of FIG. 21;

26 is an explanatory view of the etching step in FIG. 21;

FIG. 27 is a plan view of FIG. 26;

FIG. 28 is an explanatory diagram of the step of forming the epitaxial growth layer 105 in FIG. 21.

FIG. 29 is an explanatory view of a polishing step of the epitaxial growth layer 105 of FIG. 21.

30 is an explanatory view of a step of forming a concave portion 106 in FIG. 21. FIG.

FIG. 31 is an explanatory view of a step of forming a hole 107 in FIG. 21;

32 is an explanatory view of the silicon oxide 103 etching step in FIG. 21. FIG.

FIG. 33 is an explanatory view of a bonding step in FIG. 21.

[Explanation of symbols]

 Reference Signs List 21 First chamber 22 Semiconductor substrate 22a Semiconductor substrate 23 Diaphragm 24 First communication hole 25 Depression 26 Ring-shaped chamber 27 Strain detection element 27 Strain detection element 28 Support substrate 28a Support substrate 29 Second chamber 31 Wiring 32 Electrode 41 Filter part 42 First 2 communicating holes 51 first pressure guiding hole 52 second pressure guiding hole 53 overhanging part 60 semiconductor device 61 semiconductor wafer 62 support substrate original plate 63 electrode 64 bonding prevention groove 65 electrode dicing prevention groove 66 electrode facing portion 71 dicing 72 dicing 81 electrode dicing Prevention groove 811 Deep groove 812 Shallow groove 101 SOI wafer 102 Required location 103 Silicon oxide 104 Silicon 105 Epitaxial growth layer 106 Depression 107 Hole 201 SOI wafer 2011 Electrode facing portion 202 Required location 203 Silicon 204 Insulation Body 205 Epitaxial growth layer 206 Junction preventing groove 207 Electrode dicing preventing groove 2071 Deep groove 2072 Shallow groove 301 Supporting substrate original plate 302 Electrode 401 Dicing 402 Dicing

Claims (2)

(57) [Claims] A semiconductor substrate on which a semiconductor element is formed; a support substrate joined to one surface of the semiconductor substrate on one surface having an area larger than the one surface; and an outer portion of a joint between the support substrate and the semiconductor substrate. A semiconductor wafer comprising a set of a plurality of said semiconductor substrates; and a surface comprising a set of a plurality of said support substrates, comprising: a semiconductor wafer comprising: a set of a plurality of said semiconductor substrates; A supporting substrate original plate bonded to one surface of the semiconductor wafer, the electrodes provided on the one surface of the supporting substrate original plate, and bonding prevention grooves provided on the semiconductor wafer to face the electrodes, respectively. alternating deep groove and the shallow groove with a predetermined interval provided in the semiconductor wafer and in a direction perpendicular to the bottom surface of the joint preventing grooves facing to each of the electrodes along the edges of the joint preventing grooves Continued
And a plurality of electrode dicing prevention grooves comprising a groove formed, and after the semiconductor wafer alone is diced along the electrode dicing prevention grooves and an electrode facing portion of the semiconductor wafer facing the electrodes is removed, each individual dicing prevention groove is formed. A semiconductor device formed by dicing a chip. (2) A semiconductor substrate in which a semiconductor element is formed.
Plate and one side of the semiconductor substrate on one side having an area larger than the one side.
The combined support substrate and the support outside the joint between the support substrate and the semiconductor substrate
For external connection of the semiconductor element provided on the one surface of the substrate
Method for manufacturing a semiconductor device comprising:
Te, semiconductor devices, comprising the steps of
Production method. (A) forming a plurality of the semiconductor substrates on a semiconductor wafer;
A semiconductor substrate forming step. (B) forming a junction preventing groove at a predetermined position on the semiconductor wafer;
Bonding preventing groove forming step. (C) along both edges of the joint preventing groove and
Respectively before Symbol semiconductor wafer in a direction perpendicular to the bottom surface
From a continuous groove of alternating deep and shallow grooves at predetermined intervals.
To form an electrode dicing prevention groove formed
Polar dicing prevention groove forming step. (D) The electrode dicing prevention groove is formed on one surface of the support substrate original plate.
Electrode forming process to form electrodes so as to face each other
About. (E) the electrode dicing prevention groove is provided on each of the electrodes.
The semiconductor wafer is placed on one surface of the supporting substrate original plate so as to face the same.
A joining step of joining the surfaces of the EHA on the side of the joining preventing grooves. (F) removing the semiconductor wafer from the semiconductor wafer side;
In the deep groove part, the electrode dicing prevention groove is reached and the shallow groove part is reached.
In order to avoid the electrode dicing prevention groove,
Semiconductor dicing process. (G) Removal for removing the electrode facing portion of the semiconductor wafer
Process. (H) removing the semiconductor wafer from the support base plate;
Dicing the central part of the
Support substrate original plate dicing for separating into semiconductor devices
About.