KR100904994B1 - Method for fabricating pressure sensor and structure of the same - Google Patents

Abstract

The present invention relates to a pressure sensor manufacturing method and a structure thereof, the pressure sensor manufacturing method according to the present invention, the first silicon layer, the first insulating layer, and the second silicon layer structure of the SOI semiconductor substrate sequentially stacked Preparing; Forming a piezoresistor in a portion of the silicon layer by using a diffusion or ion implantation process and forming a sensor circuit including an electrode connected to the piezoresistor; and a lower surface of the first silicon layer as a lower surface of the semiconductor substrate. Forming a diaphragm by dry etching a portion of the portion to form a recess through the first silicon layer to expose the first insulating layer. According to the present invention, process reliability is improved and the sensitivity of the sensor is improved.

Dry, Bosch, Diaphragm, Pressure Sensor, Piezoresistive

Description

Method for fabricating pressure sensor and structure of the same

1 is a process cross-sectional view of a conventional diaphragm,

2 to 5 are process cross-sectional views sequentially showing a pressure sensor manufacturing process according to an embodiment of the present invention,

6 is a graph showing output characteristics of the pressure sensor manufactured by FIGS. 2 to 5.

* Description of the symbols for the main parts of the drawings *

112: second silicon layer 114: first insulating layer

116a: frame 118: second insulating layer

122: photoresist 150: recess

160: diaphragm

The present invention relates to a pressure sensor manufacturing method and a structure thereof, and more particularly to a pressure sensor manufacturing method and a structure that can simplify the process and reduce the chip size of the sensor.

Recently, with the development of microprocessor and robot industry, various industrial systems have developed into automation trends, and more sensitive control, high sensitivity, high performance and high performance sensing functions are urgently needed.

The pressure sensor is a device that measures the magnitude of pressure by detecting pressure, which is one of the basic physical quantities, and converting it into an electric signal, and is used for large-scale system control of home appliances, automotive engine control, biomedical medical devices, industrial robots, and industrial equipment. Such pressure sensors are classified into semiconductor diaphragm type pressure sensors and metal diaphragm type pressure sensors depending on materials.

In particular, semiconductor diaphragm type pressure sensor is used single crystal or polycrystalline silicon, pressure sensor using single crystal silicon is divided into capacitive pressure sensor and piezoresistive pressure sensor. The capacitive pressure sensor uses a change in capacitance depending on the degree of deflection of the diaphragm by an external pressure, and the piezoresistive pressure sensor uses a resistor in which a resistance formed on the diaphragm changes in response to stress. While the capacitive pressure sensor has a low temperature coefficient but poor linearity and difficult signal processing, the piezoresistive pressure sensor has a high linearity and easy signal processing but has a disadvantage in poor temperature characteristics.

Among the above-mentioned pressure sensors, the piezoresistive semiconductor pressure sensor using the excellent elastic properties of single crystal silicon is made possible to produce small size, light weight, and mass production due to the rapid development of silicon integrated manufacturing technology and micro machining technology. It is widely used in a wide range of fields, from the control of large-scale systems to medical devices such as biotechnology and industry.

In the conventional manufacturing process of the pressure sensor as described above, wet etching is mainly used to manufacture a diaphragm. For example, the diaphragm is formed by forming a recess in the lower surface of the semiconductor substrate through wet etching using etching solutions KOH and TMAH. This is shown in FIG.

As shown in FIG. 1, a diaphragm 60 is formed by forming a recess 50 in a semiconductor substrate. However, the conventional manufacturing method has a problem in that the diaphragm length B of the sensor is increased due to the inclination of about 55 ° as the wet etching method is used when the recess 50 is formed. In general, before the diaphragm 60 is formed, a signal processing circuit portion such as piezoresistive is formed on the upper surface of the semiconductor substrate. The signal processing circuit part is often damaged by the etching solution which is damaged when the wet etching is performed. The process or technology for protecting the signal processing circuit portion is very difficult to cause a problem of lowering the reliability of the etching process and increase in manufacturing cost.

Accordingly, it is an object of the present invention to provide a pressure sensor manufacturing method and a structure that can overcome the above-mentioned conventional problems.

Another object of the present invention to provide a pressure sensor manufacturing method and its structure that can reduce the size of the sensor.

Still another object of the present invention is to provide a pressure sensor manufacturing method and a structure which can improve the reliability of the manufacturing process.

Another object of the present invention to provide a pressure sensor manufacturing method and its structure that can reduce the manufacturing cost.

Another object of the present invention is to provide a pressure sensor manufacturing method and a structure that can increase the sensitivity of the sensor.

According to an embodiment of the present invention for achieving some of the technical problems described above, the pressure sensor manufacturing method according to the present invention, the first silicon layer, the first insulating layer, and the second silicon layer of the SOI structure of the stacked structure sequentially Preparing a semiconductor substrate; Forming a piezo resistor in a portion of the silicon layer by using a diffusion or ion implantation process and forming a sensor circuit unit including an electrode connected to the piezo resistor; Forming a diaphragm by dry etching a portion of the bottom surface of the first silicon layer, which is a bottom surface of the semiconductor substrate, to form a recess through the first silicon layer to expose the first insulating layer; Equipped.

The etching for forming the recess may be used as the etch delay layer, and the dry etching may be performed by Bosch using Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE). A bosch process can be used. And forming a second insulating layer for protecting the piezoresistor after forming the piezoresistor before forming the sensor circuit unit, and before etching to form the recess, to protect the sensor circuit unit. The method may further include forming a photoresist on the second insulating layer, and at the time of forming the diamond frame, a process of cutting a scribe line of the semiconductor substrate for device isolation may be simultaneously performed.

The first silicon layer may be an n-type silicon layer, the first insulating layer may be a silicon oxide film, and the second silicon layer may be a p-type silicon layer, and the first silicon layer, the first insulating layer, and the first silicon layer may be p-type silicon layers. The thickness ratio of the two silicon layers may have a ratio of 7: 0.5: 525.

According to another embodiment of the present invention for achieving some of the technical problems described above, the pressure sensor formed on the SOI semiconductor substrate in which the first silicon layer, the first insulating layer, and the second silicon layer according to the present invention are sequentially stacked The structure includes: a piezoresistor formed on the second silicon; A frame having a vertical structure surrounding a recess having a structure exposing the first insulating layer through the inside of the first silicon layer from a lower surface of the first silicon layer; And a diaphragm formed of a second silicon layer on the recess.

The width of the bottom surface of the first silicon layer of the recess and the width of the exposed surface of the first insulating layer may be the same.

According to the above configuration, the process reliability is improved and the sensitivity of the sensor is improved.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

2 to 5 are process cross-sectional views sequentially showing a pressure sensor manufacturing process according to an embodiment of the present invention.

As shown in FIG. 2, piezoresistors are formed on a silicon on insulator (SOI) semiconductor substrate.

The SOI semiconductor substrate 110 is mainly known as a Separation by Implanted Oxygen (SIMOX) wafer, a Silicon on Sapphire (SOS) wafer, and a Silicon Direct Bonding (SDB) wafer.

A SIMOX wafer is an SOI substrate obtained by implanting oxygen ions into a single crystal silicon substrate, annealing the substrate, and chemically reacting these oxygen ions with silicon atoms to form an oxide layer buried on the substrate. In the SIMOX wafer formation method described above, oxygen ions are implanted to form an SOI substrate, a heat treatment process is performed, and then a local oxidation method (LOCOS) or a trench oxide film or the like must be formed for device isolation. This is complicated and the manufacturing cost is high.

SOS wafers are SOI substrates obtained by growing single crystal sapphire (Al ₂ O ₃ ) on a single crystal silicon substrate by epitaxial processes and growing single crystal silicon on a single crystal sapphire layer.

On the other hand, an SDB wafer is a board | substrate obtained by joining two single crystal silicon wafers through an oxide layer, and thinning one of the two wafers by chemical and mechanical methods. The SDB method has been actively studied in recent years because not only has excellent insulation properties with a single crystal silicon thin film, but also a large area SOI substrate can be manufactured, and the electrical and mechanical characteristics of the single crystal silicon can be used.

The SOI semiconductor substrate 110 has a structure in which a first silicon layer 116, a first insulating layer 114, and a second silicon layer 112 are sequentially stacked. The SOI semiconductor substrate 110 may be manufactured by the above-described SOI substrate manufacturing method. For example, the SOI semiconductor substrate 110 may be manufactured by the SDB method. In this case, the first silicon layer 116 is an n-type silicon layer, and the first insulating layer 114 is silicon. The oxide film SiO ₂ may have a thickness of 0.5 μm, and the second silicon layer 112 may have a thickness of 525 μm as a p-type silicon layer.

In order to manufacture the pressure sensor using the SOI semiconductor substrate 110, first, a piezoresistor 120 is formed on a portion of the surface of the second silicon layer 112. The piezoresistive 120 is formed using a diffusion or ion implantation process.

For example, when an ion implantation process is used, boron of '1 * 10 ¹⁹ cm ^-3 ' is injected into a portion of the second silicon layer 112 to form a p-type piezoresistive. Here, an oxide layer (not shown) of about 1 μm may be formed by a wet oxidation process to be used as a mask in an ion implantation process and a subsequent process before the ion implantation process. The piezoresistor 120 may have a size of 50 × 60 × 0.6 μm ³ , and the piezoresistor 120 may be disposed in a 45 ° direction at an edge of a diaphragm known to exhibit maximum sensitivity.

As shown in FIG. 3, a passivation film layer 118 that is a second insulating layer is formed on the second silicon layer 112 on which the piezoresistive 120 is formed. The passivation layer 118 may be formed by depositing a silicon oxide layer (SiO ₂ ) having a thickness of 0.5 μm by a tetraethoxy silane (TEOS) process.

Next, the electrode 130 is connected to the piezoresistive 120. The electrode 130 may be formed to have a thickness of approximately '0.5 μm' using aluminum spurs. Other additional circuitry is formed to complete the sensor circuitry associated with sensor operation.

The pressure sensor employing the piezoresistive 120 has a structure in which a single-element four-terminal piezoresistor is disposed at the edge of a diaphragm of a square structure formed in a subsequent process. Can have In general, unlike the method of configuring four piezoresistors with a Wheatstone bridge circuit, four terminals for power and output are connected to one piezoresistor.

As shown in FIG. 4, a photoresist film 132 is coated on the second silicon layer 112 and the passivation layer 118 on which the piezoresistive 120 and the sensor circuit part are formed. The photoresist film 132 is for protecting the sensor circuit part during an etching process in a subsequent process. Since the etching process performed in the subsequent process is a dry etching process, a complex protective film as in the case of wet etching is not required, and generally, the circuit part can be protected only by applying a photoresist used in the photolithography process. In addition, since the removal is easy after the process, the reliability of the process can be improved.

Thereafter, an etching pattern 122 is formed on the bottom surface of the first silicon layer 116 by a photolithography process. The photoresist 122 used to form the etching pattern on the back surface of the wafer, that is, the bottom surface of the first silicon layer 116 is used as an etching mask without removing the wafer.

Next, a portion of the first silicon layer 116 is dry-etched using the etching pattern to form the recess 150.

In the dry etching, an Inductively Coupled Plasma-Reactive Ion Etching (ICP-RIE) method may be used. In particular, the recess 150 may be formed by a bosch process using inductively coupled plasma reactive ion etching.

In general, the Bosch process is known as a dry etching method that can dramatically increase the aspect ratio of a structure produced by alternating an etching process and a passivation process. For example, after etching silicon with SF ₆ gas for a predetermined time, an etching protective film is formed on the side and bottom surfaces of the etched structure using C ₄ F ₈ gas. During the next cycle of silicon etching, only the bottom protective film is removed by the directional ions. While the silicon is etched repeatedly, the sides of the structure continue to be protected from etching, allowing for anisotropic processing with good aspect ratios.

Bosch process conditions for forming the recess 150 is 17.5 seconds in one cycle including the etching and protection process, the etching rate may be about 3㎛ / min. In addition, a two-layer structure of a photoresist and a silicon oxide layer (SiO ₂ ) may be used as the etching protection layer of the Bosch process. Here, the etching selectivity may be 1:80 of the photoresist and silicon, 1: 220 of the silicon oxide film and silicon.

Accordingly, as shown in FIG. 2, the diaphragm length of the sensor manufactured by using dry etching is about 1.4T (T: etching depth) smaller than the sensor diaphragm length B produced by the conventional wet etching method of FIG. 1. It is possible. The recess 150 may be formed such that the size of the formed diaphragm 160 may be '1000x1000x7 μm ³ '.

The etching for forming the recess 150 may use the first insulating layer 114 as an etch delay layer.

In general, when etching silicon using inductively coupled plasma reactive ion etching, there is a problem in that the silicon etching surface is not uniform due to a loading effect. The loading effect is generated because the etching speed of the center portion of the etching surface is fast when the etching area is narrow, and the etching speed of the edge part is fast when the etching area is wide. Therefore, the first insulating layer 114 may be used as an etching retardation layer to prevent or minimize this and to obtain a uniform etching surface.

The delay technique using the etch delay layer uses an etch selectivity between the first silicon layer 116 and the first insulating layer 114 (eg, Si: SiO ₂ = 220: 1). By using the insulation layer 114 as an etching delay layer, it is possible to reduce the thickness variation of the etching surface that may occur due to the loading effect. Therefore, the diaphragm 160 of uniform thickness can be manufactured.

The diaphragm 160 and the frame 116a are formed by forming the recess 150 using the above-described dry etching process. The frame 116a is manufactured vertically because the Bosch process is used. That is, the width of the bottom surface of the first silicon layer 116 of the recess 150 and the width of the exposed surface of the first insulating layer 114 may be the same.

When etching to form the recess 150, it is possible to simultaneously scribe lines for separating devices. In this case, the wafer cutting process for separating the element after the end of the process can be omitted.

As shown in FIG. 5, after the diaphragm 160 and the frame 116a are formed, the pressure sensor is completed by removing the remaining photoresist 122 and 132 using a cleaner.

The pressure sensor completed by the above-described process includes a frame 116a vertically formed and a diaphragm 160 having a uniform thickness. That is, it is possible to form a uniform diaphragm 160 having a thickness of 7 μm of the second silicon layer 112. When the diaphragm 160 is connected to the frame 116a formed vertically, the size of the sensor may be reduced, and the stress generated at the edge of the diaphragm 160 may not be distributed to the frame 116a by the applied pressure. Since the concentration is concentrated at the edges, the sensitivity of the sensor can be increased.

6 is a graph showing the output characteristics of the pressure sensor produced by the above-described process.

As shown in FIG. 6, when a 3 V DC voltage is used as the power source, the pressure sensitivity of the sensor is 3.5 mV / V · kPa in the 1 kPa pressure range as shown in graph (a) and as shown in graph (b). In the 0.1kPa pressure range, it can be seen that it is very excellent at 4mV / V · kPa. In addition, the measurable resolution did not exceed 20 Pa, and the nonlinearity of the sensor was 0.5% F.S.O or less in the 1 kPa pressure range, and the maximum pressure that could be measured was 100 kPa or more.

The pressure sensor may be used for low pressure that can be used in the 0.1 kPa pressure range, and may be applicable to semiconductor process equipment control and medical equipment.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention.

As described above, according to the present invention, since the diaphragm of the pressure sensor is manufactured only by dry etching, the process is very simple and the pressure sensor and the signal processing circuit can be integrated on the same chip in a relatively simple process. In addition, the thin and uniform thickness of the diaphragm can be manufactured and the chip size of the sensor can be reduced. In addition, the reliability of the process is improved and the sensitivity of the sensor can be increased.

Claims (9)

In the pressure sensor manufacturing method: Preparing an SOI semiconductor substrate having a structure in which a first silicon layer, a first insulating layer, and a second silicon layer are sequentially stacked; Forming a piezoresistor in a part of the silicon layer by using a diffusion or ion implantation process; Forming a second insulating layer for protecting the piezoresistive; Forming a sensor circuit unit including an electrode connected to the piezoresistor; Forming a photoresist film on the second insulating layer to protect the sensor circuit part in a subsequent etching process; A part of the lower surface of the first silicon layer, which is a lower surface of the semiconductor substrate, is dry-etched through a bosch process using inductively coupled plasma reactive ion etching (ICP-RIE) to penetrate the first silicon layer. And forming a diaphragm having a frame having a vertical structure by forming a recess for exposing the first insulating layer. The method of claim 1, Etching for forming the recess is a pressure sensor manufacturing method characterized in that using the first insulating layer as an etching delay layer. delete delete The method of claim 2, And a scribe line cutting process of the semiconductor substrate for device isolation at the time of forming the diaphragm. The method of claim 1, And the first silicon layer is an n-type silicon layer, the first insulating layer is a silicon oxide film, and the second silicon layer is a p-type silicon layer. The method of claim 6, The thickness ratio of the first silicon layer, the first insulating layer, and the second silicon layer has a ratio of 7: 0.5: 525. In the structure of a pressure sensor formed on an SOI semiconductor substrate in which a first silicon layer, a first insulating layer, and a second silicon layer are sequentially stacked: Piezoresistive formed on the second silicon; A frame having a vertical structure surrounding a recess having a structure exposing the first insulating layer through the inside of the first silicon layer from a lower surface of the first silicon layer; It is provided with a diaphragm formed of a second silicon layer on the recess, And a width of a lower surface of the first silicon layer of the recess and a width of the exposed surface of the first insulating layer are the same. delete

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