JP2737256B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2737256B2
JP2737256B2 JP15163689A JP15163689A JP2737256B2 JP 2737256 B2 JP2737256 B2 JP 2737256B2 JP 15163689 A JP15163689 A JP 15163689A JP 15163689 A JP15163689 A JP 15163689A JP 2737256 B2 JP2737256 B2 JP 2737256B2
Authority
JP
Japan
Prior art keywords
film
photoresist
scribe line
pattern
patterning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP15163689A
Other languages
Japanese (ja)
Other versions
JPH0314257A (en
Inventor
誠 富永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15163689A priority Critical patent/JP2737256B2/en
Publication of JPH0314257A publication Critical patent/JPH0314257A/en
Application granted granted Critical
Publication of JP2737256B2 publication Critical patent/JP2737256B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に反射率の
高い膜のパターンを形成する方法に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pattern of a film having a high reflectance.

〔従来の技術〕[Conventional technology]

従来の高反射率の膜をパターン加工する方法として
は、半導体基板表面の高反射率の膜上に反射防止膜を形
成し、その上にフォトレジストを塗布し、マスク露光し
てこのフォトレジストをパターニングし、パターニング
されたこのフォトレジストをマスクとして、反射防止膜
と下層の高反射率の膜を同時にエッチング加工する工程
からなっていた。
As a conventional method of patterning a high-reflectance film, an anti-reflection film is formed on the high-reflectance film on the surface of the semiconductor substrate, a photoresist is applied thereon, and the photoresist is exposed by mask exposure. Using a patterned photoresist as a mask, the step of simultaneously etching the antireflection film and the underlying high-reflectance film was performed.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の高反射率の膜をパターン加工する方法
では、スクライブ線領域等の段差底部でのレジストの膜
厚が、形成すべきパターンを有する領域に比べて厚くな
っているために、スクライブ線領域等の段差底部のレジ
ストを完全に露光・現像で除去するためには、パターン
を形成すべき領域の最適露光量よりもはるかに大きな露
光量を必要とする。従って形成されたパターンは、マス
クからの寸法細りが目立ち、線幅制御が困難になるとい
う欠点がある。
In the above-described conventional method of patterning a film having a high reflectivity, the thickness of the resist at the bottom of the step, such as the scribe line region, is thicker than the region having the pattern to be formed. In order to completely remove the resist at the bottom of the step such as the region by exposure and development, an exposure amount much larger than the optimum exposure amount in the region where the pattern is to be formed is required. Therefore, the formed pattern has a drawback that the dimension from the mask is conspicuous and line width control becomes difficult.

〔課題を解決するための手段〕 本発明の半導体装置の製造方法は、半導体基板上に形
成された高反射率を有する膜上に反射防止膜を形成する
工程と、少くともスクライブ線領域内の反射防止膜を選
択的にエッチング除去したのちこの反射防止膜と前記高
反射率を有する膜を同時にパターニングする工程とを含
んで構成される。
[Means for Solving the Problems] A method of manufacturing a semiconductor device according to the present invention includes a step of forming an antireflection film on a film having a high reflectance formed on a semiconductor substrate, and at least a step of forming an antireflection film in a scribe line region. Selectively etching and removing the anti-reflection film, and then simultaneously patterning the anti-reflection film and the film having high reflectance.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例を説明するための半導
体チップの断面図である。
FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

まず第1図(a)に示すように、半導体基板10上にフ
ィールド酸化膜7とゲートポリシリコン6を形成したの
ち、第1層間膜4を形成する。次で第2ポリシリコン5
を形成したのち第2層間膜3を形成する。次に第2層間
膜3をパターン加工した後、配線材料、例えばアルミ合
金膜2を形成し、パターニングする際、表面の反射率が
高いためその散乱光がフォトレジストのパターンにノッ
チが入る等の悪影響を及ぼすことが考えられる。そこで
アルミ合金膜2の表面に反射防止膜1として、例えばス
パッタSi膜あるいはプラズマ酸化膜を形成する。
First, as shown in FIG. 1A, after forming a field oxide film 7 and a gate polysilicon 6 on a semiconductor substrate 10, a first interlayer film 4 is formed. Next is the second polysilicon 5
Is formed, a second interlayer film 3 is formed. Next, after patterning the second interlayer film 3, a wiring material, for example, an aluminum alloy film 2 is formed, and when patterning, the scattered light is notched in the photoresist pattern due to a high surface reflectance. It may have an adverse effect. Therefore, a sputtered Si film or a plasma oxide film, for example, is formed on the surface of the aluminum alloy film 2 as the antireflection film 1.

次に第1図(b)に示すように、あらかじめスクライ
ブ線領域9の反射防止膜1をエッチング除去するための
フォトレジスト8のパターニングを行ない、段差部だけ
反射防止膜1を除去する。
Next, as shown in FIG. 1B, patterning of a photoresist 8 for etching and removing the anti-reflection film 1 in the scribe line region 9 is performed in advance, and the anti-reflection film 1 is removed only at the step portion.

次に第1図(c)に示すように、フォトレジスト8を
剥離したのち、再びフォトレジスト8Aからなるマスクを
形成し配線材料2及び反射防止膜1をパターニングして
配線を形成する。
Next, as shown in FIG. 1 (c), after removing the photoresist 8, a mask made of the photoresist 8A is formed again, and the wiring material 2 and the antireflection film 1 are patterned to form wiring.

その際、やはり大きな段差を有するスクライブ線領域
9のレジスト膜厚はパターンを形成すべき領域よりおよ
そ1μm以上厚くなるが、その部分では反射防止膜がな
く、反射率の高い配線材料2がむき出しになっているた
め、一括に全面を露光しても反射防止膜1が表面を覆っ
ている領域よりも、およそ2倍〜3倍以上の光量をフォ
トレジストは吸収するので、マスク寸法がフォトレジス
ト寸法に再現する露光量で配線パターンを形成する際、
スクライブ線領域9にフォトレジストが残存する心配が
ない。こうして形成したフォトレジストのパターンをマ
スクに反射防止膜と配線材料を同時にエッチングできる
ので、マスク寸法を再現性よく転写することができる。
At this time, the resist film thickness of the scribe line region 9 also having a large step is about 1 μm or more thicker than the region where the pattern is to be formed, but the portion has no antireflection film and the wiring material 2 having high reflectivity is exposed. Therefore, even if the entire surface is exposed at once, the photoresist absorbs approximately two to three times more light than the region where the antireflection film 1 covers the surface. When forming a wiring pattern with an exposure amount that reproduces
There is no fear that the photoresist remains in the scribe line region 9. Since the antireflection film and the wiring material can be simultaneously etched using the photoresist pattern thus formed as a mask, the mask dimensions can be transferred with good reproducibility.

第2図は本発明の第2の実施例を説明するための半導
体チップの断面図である。
FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

第1図(a)に示した第1の実施例と同様の処理を行
ったのち、第2図に示すようにスクライブ線領域9の反
射防止膜1及び配線材料2も同時にエッチングし除去す
る。
After performing the same processing as in the first embodiment shown in FIG. 1A, the antireflection film 1 and the wiring material 2 in the scribe line region 9 are simultaneously etched and removed as shown in FIG.

このように、第2の実施例では、スクライブ線領域等
の段差部における厚い配線材料をもあらかじめエッチン
グしてしまうことにより、配線パターンのエッチングの
際のオーバーエッチング量を極めて小さく抑えることが
できるという利点がある。
As described above, in the second embodiment, since the thick wiring material in the step portion such as the scribe line region is also etched in advance, the amount of over-etching in the etching of the wiring pattern can be extremely reduced. There are advantages.

また、段差部の配線材料が配線パターンのパターニン
グの際にすでにエッチング除去されているので、段差部
にフォトレジストが残っていても無視でき、第1の実施
例と同様に、フォトレジストパターンでのマスク寸法の
再現が容易になる。
Further, since the wiring material of the step portion has already been removed by etching at the time of patterning of the wiring pattern, even if the photoresist remains on the step portion, it can be ignored. Reproduction of the mask dimensions becomes easy.

尚、上記実施例においてはスクライブ線領域の反射防
止膜を除去した場合について説明したが、これに限定さ
れるものではなく、スクライブ線領域と形成すべきパタ
ーンがない領域の反射防止膜を除去してもよい。
In the above embodiment, the case where the anti-reflection film in the scribe line area is removed has been described. However, the present invention is not limited to this, and the anti-reflection film in the area where there is no pattern to be formed with the scribe line area is removed. You may.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、少くともスクライブ線
領域における反射防止膜のエッチングを先に施した後、
高反射率を有する膜からなる配線パターンのパターニン
グを行なうことにより、レジストパターニングからエッ
チングに至るリソグラフィー工程におけるマスク寸法か
らの寸法細りがなくなり、寸法再現性の良いパターン加
工ができるという効果がある。
As described above, the present invention performs etching of the antireflection film at least in the scribe line region first,
By patterning a wiring pattern made of a film having a high reflectivity, there is an effect that a dimension is reduced from a mask dimension in a lithography process from resist patterning to etching, and pattern processing with good dimension reproducibility can be performed.

【図面の簡単な説明】[Brief description of the drawings]

第1図及び第2図は本発明の第1及び第2の実施例を説
明するための半導体チップの断面図である。 1……反射防止膜、2……配線材料、3……第2層間
膜、4……第1層間膜、5……第2ポリシリコン、6…
…ゲートポリシリコン、7……フィールド酸化膜、8…
…フォトレジスト、9……スクライブ線領域、10……半
導体基板。
FIGS. 1 and 2 are cross-sectional views of a semiconductor chip for explaining the first and second embodiments of the present invention. DESCRIPTION OF SYMBOLS 1 ... Anti-reflection film, 2 ... Wiring material, 3 ... Second interlayer film, 4 ... First interlayer film, 5 ... Second polysilicon, 6 ...
... gate polysilicon, 7 ... field oxide film, 8 ...
... photoresist, 9 ... scribe line area, 10 ... semiconductor substrate.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に形成された高反射率を有す
る膜上に反射防止膜を形成する工程と、少くともスクラ
イブ線領域内の反射防止膜を選択的にエッチング除去し
たのちこの反射防止膜と前記高反射率を有する膜を同時
にパターニングする工程とを含むことを特徴とする半導
体装置の製造方法。
An anti-reflection film is formed on a film having a high reflectance formed on a semiconductor substrate, and at least the anti-reflection film in a scribe line region is selectively removed by etching. Patterning a film and a film having high reflectivity at the same time.
JP15163689A 1989-06-13 1989-06-13 Method for manufacturing semiconductor device Expired - Lifetime JP2737256B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15163689A JP2737256B2 (en) 1989-06-13 1989-06-13 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15163689A JP2737256B2 (en) 1989-06-13 1989-06-13 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0314257A JPH0314257A (en) 1991-01-22
JP2737256B2 true JP2737256B2 (en) 1998-04-08

Family

ID=15522879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15163689A Expired - Lifetime JP2737256B2 (en) 1989-06-13 1989-06-13 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2737256B2 (en)

Also Published As

Publication number Publication date
JPH0314257A (en) 1991-01-22

Similar Documents

Publication Publication Date Title
JPH09251988A (en) Intermediate layer lithography method for removing part of intermediate layer
JPH06216024A (en) Method of forming metal pattern film
JPH09237777A (en) Intermediate layer lithography method by which a part of top coat is eliminated
JP3326709B2 (en) Pattern formation method
JP2737256B2 (en) Method for manufacturing semiconductor device
JP3047832B2 (en) Method for manufacturing semiconductor device
US4612274A (en) Electron beam/optical hybrid lithographic resist process in acoustic wave devices
US6200886B1 (en) Fabricating process for polysilicon gate
JP3032089B2 (en) Photomask forming method
JPH0738386B2 (en) Etching method
JP2570709B2 (en) Etching method
US5897376A (en) Method of manufacturing a semiconductor device having a reflection reducing film
JPH06132286A (en) Semiconductor device and manufacture thereof
JPH08107112A (en) Method of forming interconnection semiconductor device
JPH02138751A (en) Manufacture of semiconductor device
JP2569336B2 (en) Method for manufacturing semiconductor device
KR0138963B1 (en) Forming method of metal line
JPH07240421A (en) Wiring forming method of semiconductor device
JPH0294439A (en) Manufacture of semiconductor device
JPH0258212A (en) Manufacture of semiconductor device
JPS63221619A (en) Manufacture of semiconductor device
JPH0590418A (en) Manufacture of semiconductor device
JPH0574951A (en) Manufacture of semiconductor device
JPH08264407A (en) Pattern forming method
JPH05308102A (en) Manufacture of semiconductor device