JP2009016575A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in a highly insulating copper wiring structure. <P>SOLUTION: In the semiconductor device having a damascene wiring structure, the wiring layer of the semiconductor device has wiring copper and an insulation film between wires. The insulation film between the wires is composed of a lamination structure using a plurality of insulation films having different etching rates. At least one insulation film is composed of resin having copper diffusion resistance. The plurality of insulation films are composed of a combination where compression stress operates on a conductor at a via section. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a damascene wiring structure having an organic resin having copper diffusion resistance in a wiring layer.

  In recent years, large-scale integrated circuits (LSIs) have been increasingly improved in integration degree and operation speed. As the degree of integration increases, semiconductor elements such as transistors constituting an integrated circuit are downsized. With this miniaturization, the operation speed of the semiconductor element is improved. The delay time due to the wiring determines the operating speed of the large scale integrated circuit. The delay time due to this wiring depends on the wiring resistance and the wiring capacitance. Therefore, reduction of wiring resistance and wiring capacity is required.

  The reduction of the wiring resistance is achieved by changing the wiring material from Al to Cu having a low resistivity.

  However, since Cu has the property of easily diffusing into the insulating film of the fine wiring, it is necessary to protect the wiring copper (Cu) with a high resistance barrier metal.

  However, with the progress of miniaturization, the width of the wiring copper (Cu) is reduced, and the film thickness of the barrier metal must be reduced. Nevertheless, there is a limit to the miniaturization of the thickness of the barrier metal in order to prevent the diffusion of copper (Cu) and ensure the insulation reliability. That is, if the thickness of the barrier metal is reduced, copper (Cu) diffusion cannot be prevented and the insulation reliability is lowered.

  From this point of view, development of a low dielectric constant material having copper diffusion resistance in the insulating film itself has been required. Various organic materials have been proposed as low dielectric constant materials having copper diffusion resistance.

For example, a wiring structure using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) has been reported (Non-Patent Document 1). Further, it has been reported that fine processing was performed using a borazine-siloxane polymer material (Non-patent Document 2).
M. Tada, et al., 2001 Symp. VLSI Technol. Dig. (2001) P13-14 The Society of Polymer Science (2004) “Polymer Materials in Microelectronics” P67-68

  However, the previously proposed materials do not meet the requirements of the manufacturing process due to insufficient heat resistance, generate gas that hinders pattern drawing, and use of chemically amplified resist reduces the sensitivity of the resist Is left.

  Accordingly, a first problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure with high insulation.

  A second problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure with improved insulation reliability.

  A third problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure in which wiring resistance is suppressed.

  A fourth problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure in which the formation of stress-induced voids is suppressed.

  A fifth problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure to which a coating type barrier insulating film is applied.

  A sixth problem to be solved by the present invention is to provide a semiconductor device having a copper wiring structure at a low cost.

In the semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
It is provided by stacking,
In addition, the invention is solved by a semiconductor device characterized in that an insulating film material is selected such that stress toward the lower wiring layer side acts on the connection copper of the via layer.

For example, in a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
It is provided by stacking,
And (thermal expansion coefficient of the inter-wiring insulating film (thermal expansion coefficient in the film thickness direction)) − (thermal expansion coefficient of the insulating film for connecting copper (thermal expansion coefficient in the film thickness direction)) is 10 to 100 ppm / ° C. This is solved by a semiconductor device characterized in that it is selected and configured.

In particular, in a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
It is provided by stacking,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
In addition, the connection copper insulating film is configured by selecting an insulating film material that applies a stress toward the lower wiring layer side with respect to the connection copper of the via layer. Solved by the device.

For example, in a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
It is provided by stacking,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
And (thermal expansion coefficient of the inter-wiring insulating film (thermal expansion coefficient in the film thickness direction)) − (thermal expansion coefficient of the insulating film for connecting copper (thermal expansion coefficient in the film thickness direction)) is 10 to 100 ppm / ° C. This is solved by a semiconductor device characterized in that it is selected and configured.

Further, in a semiconductor device having a damascene wiring structure comprising an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connection copper insulating film are provided by being laminated,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
The connecting copper insulating film is formed by a semiconductor device having an etching rate different from that of the inter-wiring insulating film.

Further, in a semiconductor device having a damascene wiring structure comprising an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
Provided in layers,
Further, (thermal expansion coefficient of the insulating film between the wirings (thermal expansion coefficient in the film thickness direction)) − (thermal expansion coefficient of the insulating film for connecting copper (thermal expansion coefficient in the film thickness direction)) is 10 to 100 ppm / ° C. Selected and configured to be
Moreover, the inter-wiring insulating film is made of a resin having copper diffusion resistance,
In addition, the semiconductor device is characterized in that the connection copper insulating film is formed with an etching rate different from the etching rate of the inter-wiring insulating film.

Among them, in a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connection copper insulating film are provided by being laminated,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
The connecting copper insulating film is formed of at least one selected from the group consisting of SiC and SiCN, and is solved by a semiconductor device.

In particular, in a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connection copper insulating film are provided by being laminated,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
The connection copper insulating film is composed of at least one selected from the group consisting of SiC and SiCN,
The resin having copper diffusion resistance has an etching rate different from that of the connection copper insulating film, and a thermal expansion coefficient (thermal expansion coefficient in the film thickness direction) of the resin for connection copper. This is solved by a semiconductor device characterized in that it is 10 to 100 ppm / ° C. larger than the thermal expansion coefficient (thermal expansion coefficient in the film thickness direction).

  Further, in the above semiconductor device, the resin having copper diffusion resistance is an organic resin having N atoms having a heat resistant temperature of 400 ° C. or higher and a dielectric constant of 3.0 or lower. Is done. Above all, the problem is solved by a semiconductor device characterized in that the resin having copper diffusion resistance is polybenzoxazole.

  In addition, the above-described semiconductor device is solved by the semiconductor device characterized in that the connection copper insulating film is composed of at least one selected from the group of SiC and SiCN.

  Further, the above semiconductor device is solved by the semiconductor device characterized in that Ti is provided at the interface between copper and the insulating film.

  The semiconductor device of the present invention configured as described above has high insulation of the copper wiring structure. In addition, the insulation reliability has been improved. And since the high resistance barrier metal is not provided, wiring resistance is suppressed. Moreover, the formation of stress-induced voids is suppressed. In addition, since a coating type barrier insulating film is applied, the semiconductor device is inexpensive.

  The semiconductor device of the present invention is a semiconductor device having a damascene wiring structure including an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer. There are a plurality of wiring layers. Therefore, it is not limited to two layers, and may be three layers, four layers, five layers, and so on. The wiring layer (upper wiring layer and lower wiring layer) includes wiring copper for signal transmission and an inter-wiring insulating film provided around the wiring copper. The via layer includes connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for connection copper provided around the connection copper. The inter-wiring insulating film and the connecting copper insulating film are provided by being laminated. The inter-wiring insulating film and the connecting copper insulating film are materials that are selected in such a way that the insulating film material is selected so that stress is applied to the connecting copper of the via layer toward the lower wiring layer side. Composed. For example, materials having different etching rates are selected as the different materials. Or it is comprised with the material from which a thermal expansion coefficient differs. For example, (expansion coefficient of insulating film between wirings in upper wiring layer (thermal expansion coefficient in film thickness direction)) − (expansion coefficient of insulating film in via layer (thermal expansion coefficient in film thickness direction)) is 10 to 100 ppm / ° C. Each material is selected so as to be (preferably 20 to 80 ppm / ° C.) to form each insulating film. In general, the fact that the coefficient of thermal expansion is different means that the etching rate is also different, and therefore materials having different etching rates and thermal expansion coefficients are selected (particularly, materials having different physical properties as described above). . That is, by adopting such a configuration, a stress toward the lower wiring layer side acts on the connection copper of the via layer. The inter-wiring insulating film is preferably made of a resin having copper diffusion resistance. In particular, N atoms having a heat resistant temperature of 400 ° C. or higher (preferably 450 ° C. or higher) and a dielectric constant of 3.0 or lower (preferably 2.7 or lower, and practically 1.9 or higher) are used. Consists of organic resin with copper diffusion resistance. Among these organic resins, polybenzoxazole (PBO) is preferable. As the insulating film for connecting copper, SiC and SiCN are particularly preferable. Furthermore, Ti is preferably provided at the interface between copper and the insulating film.

  One major feature of the present invention is that a barrier layer against copper diffusion is eliminated by using an organic resin insulating film having copper diffusion resistance. This is because, in the process of evaluating various insulating films containing organic resin materials, an organic resin such as polybenzoxazole as shown in the copper diffusion evaluation result by the TDDB (time-dependent dielectric breakdown) test shown in FIG. Is based on the finding that it has copper diffusion resistance. The organic resin insulating material can be expected to have a certain degree of copper diffusion resistance. For example, an organic resin insulating material such as PBO or BCB (PolyBenzocyclobuten) can be expected to have copper diffusion resistance. However, among them, PBO was found to be excellent in heat resistance. Furthermore, the dielectric constant was also found to be superior to polyimide. In addition, it has also been found that the fine workability is superior to SiC and SiCN that have been used as insulating materials. Therefore, by using PBO as an inter-wiring insulating film in the wiring layer, it becomes unnecessary to use a high-resistance barrier metal, and an effect of reducing the wiring resistance can be obtained, and a high dielectric constant barrier insulating film is used. The effect of reducing the effective dielectric constant can be obtained.

  In order to clarify the features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

  FIG. 2 is a sectional view showing a first embodiment in which the present invention is applied to a copper / low dielectric constant insulating film damascene wiring structure. In FIG. 2, 1 is a base SiO film, 2 is a barrier insulating film made of SiC (or SiCN), 3 is a low dielectric constant inter-wiring insulating film made of PBO, 4 is a lower wiring copper (Cu), and 5 is a PBO film. 3 is a cap film made of SiC (or SiCN) formed on the surface of 3, 6 is a barrier insulating film made of SiC (or SiCN) provided on the surface of the lower wiring copper 4 and the cap film 5 (PBO film 3), 7 Is a low dielectric constant inter-wiring insulating film made of PBO, 8 is an upper wiring copper (Cu), 9 is a connection copper for electrically connecting the lower wiring copper 4 and the upper wiring copper 8, and 10 is the surface of the PBO film 7 A cap film made of SiC (or SiCN), 11 is a barrier insulating film made of SiC (or SiCN), and 12 is a protective film made of SiO. As can be seen from FIG. 2, the lower wiring layer is composed of an insulating film 3 between PBO wirings, a lower wiring copper 4 and a cap film 5. However, the cap film 5 may not be provided. The upper wiring layer includes an inter-PBO wiring insulating film 7, an upper wiring copper 8, and a cap film 10. However, the cap film 10 may not be provided. The via layer is made of a barrier insulating film 6 and connection copper 9.

  As can be seen from FIG. 2, since the insulating film material (PBO) having copper diffusion resistance is used, the copper diffusion preventing metal layer is not provided. That is, since a high resistance copper diffusion preventing metal layer such as Ta does not exist at the boundary between the lower wiring copper 4 and the connection copper 9, the resistance reduction in the via layer can be remarkably improved. This is because, conventionally, a copper diffusion preventing metal (for example, Ta) layer provided on the bottom of the via, that is, on the surface of the lower wiring copper 4 divides the wiring copper. These problems are solved.

  Furthermore, by using a plurality of insulating materials having different thermal expansion coefficients, that is, PBO and SiC (SiCN), it is possible to effectively use the internal stress generated by the difference in the thermal expansion coefficients of the respective insulating materials. The thermal expansion coefficient (thermal expansion coefficient in the film thickness direction) of the PBO film is 86 ppm / ° C., and the thermal expansion coefficient (thermal expansion coefficient in the film thickness direction) of the SiC film is 1 to 10 ppm / ° C. The thermal expansion coefficient is 1-10 ppm / ° C. That is, according to the combination of insulating materials as described above, the copper atoms in the wiring layer (lower wiring copper 4) are subjected to stress in a direction in which the copper atoms are pressed downward at the via bottom. Incidentally, in the case of a laminated structure (hybrid structure) using SiC as the barrier insulating film 6 in the via layer and PBO as the inter-wiring insulating film 7 in the upper wiring layer, the copper atoms in the wiring layer (lower wiring copper 4) are transferred to the bottom of the via. And pressed downward with a force of 50 MPa or more. FIG. 3 shows a structure in which stress-induced voids are easily generated. FIG. 5 shows a simulation result of stress at the via bottom of a multilayer wiring structure in which a wiring having a width of 5 μm is provided in the first wiring layer M1 and the second wiring layer M2 in FIG. 3 and a via having a diameter of 130 nm is provided in the via layer. In the case where both insulating films have the same type of SiOC structure, the downward stress is 0 to several MPa, whereas the insulating film of the wiring layer is PBO and the insulating film of the via layer is a hybrid of SiC. In the structure, the downward stress is 150 MPa or more, which is about two orders of magnitude greater. Therefore, it can be seen that the wiring structure has a high reliability and hardly causes disconnection. In addition, a hybrid structure using materials with different etching rates for the insulating material of the wiring layer and the insulating material of the via layer has been adopted, so the number of processes compared to single damascene and dual damascene manufacturing methods using the same type of film. Can be reduced.

  In addition, while copper diffusion prevention insulating materials such as SiC and SiCN have a high dielectric constant, when an organic resin such as PBO is used for the inter-wiring insulating film, it has a low dielectric constant. The effect of rate reduction is obtained.

  FIG. 4 is a process diagram for forming the wiring structure of the present invention. In addition, the manufacturing conditions in this process can use the conditions in the case of forming a normal damascene wiring structure, and a new economic burden does not increase in terms of process and equipment. Since the manufacturing process is different only in the insulating film material, a simple description will be given below.

  FIG. 4A shows a SiC film (barrier insulating film) 6 formed by CVD on a lower wiring layer (lower wiring copper 4, PBO inter-wiring insulating film 3 and cap film 5), and via etching by photoetching technology. This shows a stage in which the PBO solution is applied and then the PBO inter-wiring insulating film 7 is provided.

  Thereafter, as shown in FIG. 4B, a SiC film (cap film) 10 is provided by CVD, and a window process for wiring grooves is performed on the SiC film 10 by a photoetching technique.

  Then, as shown in FIG. 4C, the PBO wiring insulating film 7 is removed using the cap film 10 with the window formed as a hard mask, and the via (hole) is filled using the barrier insulating film 6 as a hard mask. Remove the PBO.

  Next, as shown in FIG. 4D, after a copper seed film is provided on the surface, copper plating is performed by wet plating, and the contact copper 9 is filled in vias (holes) by being in close contact with the lower wiring copper 4. Subsequently, upper wiring copper 8 is provided.

  Thereafter, as shown in FIG. 4E, CMP is performed to flatten the surface.

  In the wiring layer obtained as described above, the stress in the via layer is calculated to be 150 MPa or more in the downward direction, and the copper atoms in the upper wiring layer receive a stress in the direction of being attracted (pressed) to the via layer side. Therefore, disconnection hardly occurs. Incidentally, this is shown in FIG.

  In addition, the compressive stress generated in the via layer portion depends on the internal stress due to the difference in the thermal expansion coefficient of the material used for the insulating film. If the downward stress generated in the via layer is 50 MPa or more, it is caused by the stress. Voids can be suppressed and disconnection hardly occurs.

  Further, FIG. 6 shows the evaluation result of the inter-wiring TDDB. It can be seen that the wiring structure of the present invention has a 10-year life of TDDB and high insulation reliability.

  FIG. 7 is a schematic sectional view of a semiconductor device showing a second embodiment according to the present invention.

  In the present embodiment, the Ti layer 21 is thinly provided between the copper film and the insulating film, and the other points are basically the same as those of the above-described embodiment. Omitted.

  That is, by providing the Ti layer, high reliability as a wiring can be maintained.

  This is because, in the via wiring portion, peeling occurs between the copper in the via portion and the insulating material due to a difference in the thermal expansion coefficient of the material to be used, and the conduction reliability may be impaired. Therefore, improving the adhesion to the insulating film is preferable not only for widening the selection range of the insulating film material but also for improving the production yield and quality.

  Therefore, as a result of various experiments by the inventor, as shown in FIG. 8, it is seen that if the lining treatment with titanium is performed before the copper seed film is formed, the adhesion between the insulating film side wall and copper is improved. It was issued. This Ti layer is effective even if it has a thickness of several atomic layers, and it is sufficient if it has ˜2 nm. And even compared to Ta / TaN, which is a barrier metal film having a high resistance value with respect to copper, which is widely used at present, it is advantageous in the trend of miniaturization of wiring formation, of course, low resistance. This is also advantageous. Furthermore, this manufacturing method also uses the conventional Ta / TaN barrier film forming process, and the material can be used as Ti instead of Ta, and the change in the electric resistance value due to the provision of the Ti layer affects the performance. Not so much. As a result, it was possible to form a hybrid wiring process with a high yield without any trouble during the process.

Copper diffusion evaluation result by TDDB test Schematic sectional view of a semiconductor device according to the present invention Graph showing stress at via bottom Manufacturing process diagram of semiconductor device according to the present invention Graph explaining stress-induced void resistance between a barrier metal-attached SiOC laminated film and a barrier metal-free PBO / SiC laminated film Evaluation result of inter-wiring TDDB Schematic sectional view of a semiconductor device according to a second embodiment of the present invention. The graph which shows the stress-induced void tolerance improvement of the semiconductor device which becomes 2nd Embodiment of this invention

Explanation of symbols

2 Barrier insulation film (SiC, SiCN)
3 Inter-wiring insulation film (PBO)
4 Lower layer wiring copper (Cu)
5 Cap film (SiC, SiCN)
6 Barrier insulating film (SiC, SiCN)
7 Inter-wiring insulation film (PBO)
8 Upper wiring copper (Cu)
9 Connection copper

Patent applicant Next-generation semiconductor material technology research association
Representative Katsumi Udaka

Claims (7)

In a semiconductor device having a damascene wiring structure comprising an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connecting copper insulating film,
It is provided by stacking,
In addition, a semiconductor device characterized in that an insulating film material is selected such that stress toward the lower wiring layer side acts on the connection copper of the via layer. 2. The semiconductor device according to claim 1, wherein the inter-wiring insulating film is made of a resin having copper diffusion resistance. In a semiconductor device having a damascene wiring structure comprising an upper wiring layer, a lower wiring layer, and a via layer provided between the upper wiring layer and the lower wiring layer,
The wiring layer of the semiconductor device comprises wiring copper and an inter-wiring insulating film,
The via layer of the semiconductor device comprises a connection copper for electrically connecting the wiring copper of the upper wiring layer and the wiring copper of the lower wiring layer, and an insulating film for the connection copper,
The inter-wiring insulating film and the connection copper insulating film are provided by being laminated,
The inter-wiring insulating film is made of a resin having copper diffusion resistance,
The semiconductor device according to claim 1, wherein the connection copper insulating film has an etching rate different from an etching rate of the inter-wiring insulating film. 4. The semiconductor device according to claim 2, wherein the resin having copper diffusion resistance is an organic resin having N atoms having a heat resistant temperature of 400 ° C. or higher and a dielectric constant of 3.0 or lower. 5. The semiconductor device according to claim 2, wherein the resin having copper diffusion resistance is polybenzoxazole. 6. The semiconductor device according to claim 1, wherein the connecting copper insulating film comprises at least one selected from the group consisting of SiC and SiCN. 7. The semiconductor device according to claim 1, wherein Ti is provided at an interface between copper and an insulating film.

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