JP2013168687A - Semiconductor element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element manufacturing method which can ensure accurate alignment between a contact plug and a wiring line.SOLUTION: A semiconductor element manufacturing method comprises: forming a first etching stop insulation film 112, a first interlayer insulation film 120, a second etching stop insulation film 122 and a second interlayer insulation film 124 on a semiconductor substrate 10; forming a plurality of first mask patterns 134 and buffer insulation films 136 which cover both side walls of the first mask patterns; forming a plurality of second mask patterns 138a extending in parallel with the plurality of first mask patterns such that one second mask pattern is arranged between the two first mask patterns adjacent to each other; removing a part of the buffer insulation films and the insulation films to form a plurality of trenches 158 each extending between the first mask pattern and the second mask pattern in parallel with the first mask pattern and the second mask pattern, and a plurality of contact holes 152a which communicate with the trenches, respectively, and expose conductive regions of the semiconductor substrate; and simultaneously forming a plurality of wiring lines 168 which is integrally formed with the contact plugs 162 by filling a conductive material inside the trenches and the contact holes.

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, a semiconductor device having a fine pattern including a wiring line repeatedly formed at a fine pitch and a contact plug for connecting the wiring line to a peripheral conductive region. It relates to the manufacturing method.

  In manufacturing a highly integrated semiconductor device, pattern miniaturization is essential. In order to integrate many elements in a small area, the size of each individual element must be made as small as possible. For this purpose, the sum of the width of each pattern to be formed and the interval between the patterns is used. A certain pitch must be reduced.

  Recently, in a photolithography process for forming a pattern necessary for realizing a semiconductor element due to a rapid decrease in the design rule of the semiconductor element, there is a limit in forming a pattern having a fine pitch due to a resolution limit. In particular, when forming a contact hole in an insulating film to form a contact for electrically connecting unit elements formed on a substrate, a plurality of contact holes formed densely at a fine pitch in a narrow area are formed. When a photolithographic process is used to form the desired contact having a fine pitch by reducing the space that must be held between the contact hole patterns and the alignment margin, because the shape that can be realized is limited by the resolution limit. There is a limit to forming a hole pattern. In particular, as the degree of integration of the semiconductor memory device increases, the pitch between the bit lines of the ultra-high-integrated flash memory device having a feature size of 30 nm is rapidly reduced. When a photolithography process is used to form a plurality of bit lines that are repeatedly formed at such a fine pitch, there is a limit in forming a desired pattern due to the resolution limit.

  In general, before forming a bit line, a contact plug for connecting the bit line to a peripheral conductive region, for example, an active region of a semiconductor substrate, is first formed. A bit line in contact with the contact plug is formed on the contact plug. In the case of such a normal process, it is necessary to ensure a minimum misalignment margin between the contact plug and the bit line. However, since the pitch between the bit lines is reduced, it is no longer possible to secure a sufficient space between the adjacent bit lines to provide the misalign margin, and in order to secure a minimum misalign margin. There are limits to designing the layout.

  The present invention is for solving the above-described problem, and connects a plurality of wiring lines repeatedly formed at a fine pitch exceeding a resolution limit in a photolithography process and the wiring lines to a peripheral conductive region. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of ensuring accurate alignment between the contact plug and the wiring line without securing a separate misalign margin between the contact plug and the contact plug.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention forms an insulating film on a semiconductor substrate to cover a conductive region on the semiconductor substrate. A plurality of first mask patterns extending in parallel with each other in the first direction at a first pitch are formed on the insulating film. A buffer insulating film is formed to cover both side walls of the plurality of first mask patterns. Among the plurality of first mask patterns, the plurality of first mask patterns and the buffer insulating film are formed so that one second mask pattern is formed in a space between two adjacent first mask patterns. A plurality of second mask patterns each extending in parallel with the plurality of first mask patterns are formed while being self-aligned. Removing a part of the buffer insulating film and a part of the insulating film, and communicating with each of a plurality of trenches extending in parallel with the first mask pattern and the second mask pattern, and the trenches; A plurality of contact holes are formed to expose the conductive region of the semiconductor substrate. A contact plug formed in the contact hole by filling the contact hole and the trench with a conductive material, and a plurality of wiring lines formed in the trench are formed simultaneously with the contact plug. The step of forming the insulating film includes forming a first etching stop insulating film covering the conductive region on the semiconductor substrate, and forming a first interlayer insulating film on the first etching stop insulating film. Forming a second etching stop insulating film on the first interlayer insulating film, and forming a second interlayer insulating film on the second etching stop insulating film.

  The forming the plurality of trenches and the plurality of contact holes may include etching the buffer insulating film and the insulating film using the first mask pattern and the second mask pattern as an etching mask to etch the first mask pattern and the second mask hole. Forming a plurality of line-shaped trenches extending in parallel with the mask pattern, and forming an opening exposing the plurality of first mask patterns, a portion of the plurality of second mask patterns, and a portion of the bottom surface of the trench; Forming a third mask pattern, and the contact hole exposing the conductive region by etching the insulating film using the first mask pattern, the second mask pattern, and the third mask pattern as an etching mask, respectively. Forming a step.

  In the semiconductor device manufacturing method according to the present invention, an excellent CD (Critical Dimension) is used to form a contact pattern repeatedly formed at a fine pitch exceeding a resolution limit in a photolithography process using a double patterning process. It can be formed with a uniform degree. Particularly, in order to integrally form a plurality of contact plugs and wiring lines that are repeatedly formed at a fine pitch, the contact holes for forming the contact plugs and the trenches for forming the wiring lines are formed to communicate with each other. Thereafter, a process of simultaneously filling the contact hole and the trench with a conductive material is used. At this time, the position of the contact hole to be finally realized is determined by the position of the hard mask pattern repeatedly formed at a fine pitch by the double patterning process and the position of the third mask pattern formed thereon. The layout design for forming the hole is easy, the alignment of the contact hole formation position to a desired position is facilitated, and a sufficient etching margin can be secured. Also, contact holes and wiring lines to be formed can be easily formed regardless of their shapes by freely determining the shapes and arrangement of the hard mask pattern and the third mask pattern used as an etching mask.

3 is an exemplary wiring pattern layout of a semiconductor device according to a reference example of the present invention; FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a first reference example of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a method of manufacturing a semiconductor device according to a second reference example of the present invention, according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a method of manufacturing a semiconductor device according to a second reference example of the present invention, according to a process order. FIG. 5 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of processes. FIG. 5 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of processes. FIG. 5 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of processes. FIG. 5 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of processes. FIG. 5 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of processes. FIG. 6 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention according to a process order. FIG. 6 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention according to a process order. FIG. 6 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention according to a process order. FIG. 6 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention according to a process order. FIG. 6 is a partially cutaway perspective view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to a third embodiment of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to a third embodiment of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to a third embodiment of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to a third embodiment of the present invention according to a process order. FIG. 10 is a partially cutaway perspective view illustrating a semiconductor device manufacturing method according to a third embodiment of the present invention according to a process order.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  The embodiments of the present invention can be modified in various forms, and the scope of the present invention should not be construed to be limited to the embodiments described below. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements.

  FIG. 1 is an exemplary wiring pattern layout of a semiconductor device as a reference example of the present invention. FIG. 1 illustrates a layout of a plurality of bit lines 30 that constitute a part of the flash memory device.

  In FIG. 1, the plurality of bit lines 30 have substantially the same line width as the active region 12 on each active region 12 which is a conductive region, and are parallel to the active region 12 in a first direction (y direction). It extends along. The bit line 30 is electrically connected to the active region 12 through any one of the plurality of direct contacts 20. The bit lines 30 are repeatedly arranged at a predetermined pitch PB. The active region 12 which is a conductive region is, for example, an impurity diffusion region formed in the substrate 10 and is, for example, a source / drain of a transistor.

  FIG. 1 illustrates a case where the plurality of direct contacts 20 are repeatedly formed at the same pitch as the pitch of the plurality of bit lines 30. The plurality of direct contacts 20 are arranged in a line along a second direction (x direction) orthogonal to the first direction.

  2A to 2I are partially cutaway perspective views illustrating a semiconductor device manufacturing method according to a first reference example of the present invention in order of processes. 2A to 2I illustrate a process for forming the direct contact 20 and the bit line 30 according to the layout of FIG. 1 in an integrated structure. 2A to 2F are partially cutaway perspective views of a portion corresponding to the “A” region in FIG. 1, and FIGS. 2G to 2I are partially cutaway portions of the portion corresponding to the “B” region in FIG. FIG.

  Referring to FIG. 2A, the first etching stop insulating film 112 and the first etching stop layer 112 are formed on the semiconductor substrate 10 in which an active region (not shown) having the same layout as the active region 12 according to the layout illustrated in FIG. One interlayer insulating film 120 is sequentially formed.

  On the semiconductor substrate 10, for example, unit elements (not shown) necessary for forming the same semiconductor elements as a plurality of word lines are formed, and the first interlayer insulating film 120 covers the unit elements. It can consist of a plurality of insulating films. A conductive region (not shown) that can be electrically connected to the unit element is exposed on the upper surface of the semiconductor substrate 10.

  The first etching stop insulating film 112 is formed to serve as an etching stop layer when the first interlayer insulating film 120 is etched. The first etch stop insulating layer 112 may be made of a material that provides an etch selectivity different from that of the first interlayer insulating layer 120. Depending on the constituent material of the first interlayer insulating film 120, the first etching stop insulating film 112 may be formed of, for example, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon carbide film. For example, the first etch stop insulating layer 112 may be formed to a thickness of about 500 mm.

  The first interlayer insulating layer 120 may be formed of an insulating material having a relatively low dielectric constant so as to reduce RC delay caused by a coupling capacitor caused by a reduction in the space width between bit lines. . For example, the first interlayer insulating layer 120 may be made of TEOS (tetraethoxysilane (tetraethylsilane)), FSG (fluorinated silicate glass), SiOC, or SiLK. Alternatively, the first interlayer insulating film 120 may be at least one selected from the group consisting of a thermal oxide film, an oxide film formed by a CVD method, a USG film (undoped silicate glass film), and an HDP oxide film (high density plasma oxide film). One oxide film can be provided. Further, the first interlayer insulating film 120 may include a nitride film, for example, at least one film selected from the group consisting of SiON, SiN, SiBN, and BN. Further, the first interlayer insulating film 120 has a laminated structure of one nitride film selected from the nitride films exemplified above and one oxide film selected from the oxide films exemplified above. Can be.

  When the first etching stop insulating film 112 is made of a nitride film, the first interlayer insulating film 120 is preferably made of an oxide film.

  A plurality of first mask patterns 134 are formed on the first interlayer insulating layer 120 using a normal photolithography process.

  The first mask pattern 134 is formed to have a first pitch 2P that is twice as large as the pitch P of the hard mask pattern 130 (see FIG. 2E) to be finally formed. Here, the pitch P of the hard mask pattern 130 is the same as the pitch PB of the bit lines 30 illustrated in FIG. For example, the first width W1 of the first mask pattern 134 may be designed to have a value that is ¼ of the first pitch 2P.

  The first mask pattern 134 is made of a material having an etching characteristic different from that of the first interlayer insulating layer 120, that is, a material having a different etching selectivity with respect to a predetermined etching condition. For example, the first mask pattern 134 is made of any one material selected from the group consisting of an oxide film, a nitride film, a polysilicon film, and a metal film. When the first interlayer insulating layer 120 is formed of an oxide layer or a nitride layer, the first mask pattern 134 may be formed of a polysilicon layer. Alternatively, when the first interlayer insulating layer 120 is formed of a nitride layer, the first mask pattern 134 may be formed of an oxide layer.

  Referring to FIG. 2B, the first interlayer insulating layer 120 exposed between the plurality of first mask patterns 134 is removed from the upper surface by a first thickness d to form an upper surface of the first interlayer insulating layer 120. A low surface portion 120a having a groove shape is formed.

  Preferably, the first thickness d has the same dimension as the first width W1 of the first mask pattern 134.

  A dry etching process may be performed to form the low surface portion 120a on the top surface of the first interlayer insulating layer 120. For example, in the step of forming the first mask pattern 134 described with reference to FIG. 2A, after the first mask pattern 134 is formed during the dry etching process for forming the first mask pattern 134, The first interlayer insulating film 120 may be continuously excessively etched to form the low surface portion 120a. As another method, a separate dry etching process for forming the low surface portion 120a can be performed.

  The step of forming the low surface portion 120a is not an essential step for carrying out the method for manufacturing a semiconductor device according to the present invention, and may be omitted in some cases.

  Referring to FIG. 2C, each of the first mask patterns 134 may have a recess region 136 a having a predetermined width between two adjacent first mask patterns 134 among the plurality of first mask patterns 134. A buffer insulating film 136 covering both side walls is formed.

  The buffer insulating layer 136 may be formed of a film covering the upper surface and sidewalls of the first mask pattern 134 and the lower surface portion 120a of the first interlayer insulating layer 120 with a uniform thickness. The buffer insulating layer 136 may be formed to have the same thickness as the first thickness d. In addition, the thickness of the buffer insulating film 136 may be determined such that the recess region 136a limited by the upper surface of the buffer insulating film 136 has a width W2 that is the same as the first width W1.

  The buffer insulating layer 136 may be made of a material having the same or similar etching characteristics as the first interlayer insulating layer 120. For example, the buffer insulating layer 136 may be made of the same material as the constituent material of the first interlayer insulating layer 120. Alternatively, the buffer insulating layer 136 may be formed of a different material from the first interlayer insulating layer 120, although the etching characteristics are similar. For example, the buffer insulating layer 136 may be an oxide film. The buffer insulating layer 136 may be formed of an oxide layer formed by an ALD (Atomic Layer Deposition) method.

  Referring to FIG. 2D, a second mask layer 138 is formed on the buffer insulating layer 136. The second mask layer 138 may be made of a material having the same or similar etching characteristics as the first mask pattern 134. For example, the second mask layer 138 is made of any one material selected from the group consisting of an oxide film, a nitride film, a polysilicon film, and a metal film. When the first interlayer insulating layer 120 and the buffer insulating layer 136 are formed of an oxide layer or a nitride layer, the second mask layer 138 may be formed of a polysilicon layer. Alternatively, when the first interlayer insulating layer 120 and the buffer insulating layer 136 are formed of a nitride layer, the second mask layer 138 may be formed of an oxide layer. Alternatively, when the first interlayer insulating layer 120 and the buffer insulating layer 136 are each formed of an oxide layer, the second mask layer 138 may be formed of a polysilicon layer or a nitride layer.

  By forming the second mask layer 138, the recess region 136 a is filled with the second mask layer 138. When the thickness of the buffer insulating film 136 has a value that is ¼ of the first pitch 2P, the width of the portion of the second mask layer 138 filled in the recess region 136a, that is, the recess. The width W2 of the region 136a may be a quarter value of the first pitch 2P, that is, the same value as the width W1 of the first mask pattern 134.

  Referring to FIG. 2E, a portion of the second mask layer 138 and a portion of the buffer insulating layer 136 are removed until a top surface of the first mask pattern 134 is exposed, and a plurality of second mask layers 136a are formed in the recess 136a. A two-mask pattern 138a is formed.

  The plurality of second mask patterns 138a have a structure that is self-aligned by the first mask pattern 134 and the buffer insulating layer 136, and extend in the same direction as the extending direction of the plurality of first mask patterns 134. It consists of a line pattern. The first mask pattern 134 and the second mask pattern 138 a constitute a hard mask pattern 130. The hard mask pattern 130 is used as an etching mask during dry etching of the first interlayer insulating layer 120 in a subsequent process. The hard mask pattern 130 including the first mask pattern 134 and the second mask pattern 138a has a width W1 or W2 that is ¼ of the first pitch 2P, and ½ of the first pitch 2P. The line pattern has a shape that is repeatedly formed at a pitch P.

  For example, a CMP (Chemical Mechanical Polishing) process may be used to remove a part of the second mask layer 138 and a part of the buffer insulating film 136. Alternatively, in order to remove a part of the second mask layer 138 and a part of the buffer insulating film 136, first, the second mask layer 138 is formed such that the second mask pattern 138a remains only in the recess region 136a. After removing a part, a part of the buffer insulating film 136 exposed between the plurality of second mask patterns 138a is removed to expose the upper surface of the first mask pattern 134, thereby obtaining the result of FIG. 2E. Get things.

  In the figure, the buffer insulating film portion whose upper surface is exposed by removing a part thereof is referred to as a buffer insulating film 136b, and the buffer insulating film portion on which the second mask pattern 138a is mounted in FIG. As shown.

  Here, in order to remove a part of the second mask layer 138 and a part of the buffer insulating film 136, a wet etching process may be used.

  Referring to FIG. 2F, a third mask pattern in which an opening 140a exposing the upper surface of the buffer insulating layer 136b and the upper surface of the hard mask pattern 130 is formed on the resultant structure on which the hard mask pattern 130 is formed. 140 is formed.

  FIG. 2F illustrates a case where the opening 140 a formed in the third mask pattern 140 has a line shape extending along a direction orthogonal to the extending direction of the hard mask pattern 130. This is because the openings 140a having a line form are formed corresponding to the arrangement form of the direct contacts 20 illustrated in FIG. However, the present invention is not limited to this. The third mask pattern 140 may have openings 140a having various planar shapes and various arrangements according to the arrangement form of the direct contact 20. Alternatively, the third mask pattern 140 may be a line pattern extending in a direction different from the extending direction of the hard mask pattern 130. As desired, the third mask pattern 140 and the hard mask pattern 130 may have an extending direction that forms a predetermined inclination angle with respect to the extending direction of the hard mask pattern 130, for example, an angle of about 5 to 90 degrees. It may have a pattern shape extending across each other. Alternatively, when each of the plurality of direct contacts 20 is formed at an arbitrary position without being limited to a specific arrangement rule, a third mask pattern in which a plurality of island-shaped openings are formed at the corresponding position is formed. It is also possible to do.

  A predetermined region of the upper surface of the buffer insulating layer 136b is exposed through the third mask pattern 140 and the hard mask pattern 130. Here, the exposed region of the buffer insulating layer 136b corresponds to a contact hole region formed in the first interlayer insulating layer 120 in a subsequent process.

  For example, the third mask pattern 140 may be formed of a photoresist film. Alternatively, the third mask pattern 140 may be a polysilicon film, a nitride film, a hard mask layer such as ACL (amorphous carbon layer), a capping layer such as SiON, TEOS, or ALD-oxide film, It may have a laminated structure of at least two layers selected from the group consisting of an ARC film (anti-reflective coating film) and a photoresist film. For example, the third mask pattern 160 may be a three-layer stacked film in which an SOC film (spinon carbon film), a SiARC film, and a photoresist layer are sequentially stacked, or an SOC film, a SiARC film, and an organic film. An ARC film and a multilayer film having a four-layer structure in which a photoresist layer is sequentially stacked may be used.

  Referring to FIG. 2G, the buffer insulating layer 136b and the first interlayer insulating layer 120 are anisotropically dry etched using the hard mask pattern 130 and the third mask pattern 140 as etching masks, respectively, to form an upper contact hole 152. Form. At this time, the total thickness of the first interlayer insulating film 120 is such that the first interlayer insulating film 120 having a predetermined thickness D1 remains on the first etching stop insulating film 112 at the bottom surface of the upper contact hole 152. Of these, only a part is etched to form the upper contact hole 152. A thickness D1 of the first interlayer insulating layer 120 remaining under the upper contact hole 152 may be set to correspond to a thickness of a wiring line formed in a subsequent process.

  Referring to FIG. 2H, the third mask pattern 140 is removed.

  Referring to FIG. 2I, the buffer insulating layer 136b and the first interlayer insulating layer 120 are etched using the hard mask pattern 130 as an etching mask to form a plurality of line-shaped trenches 158 extending in parallel with the hard mask pattern 130. To do. The trench 158 is formed to communicate with the upper contact hole 152. While the trench 158 is formed, in the vicinity of the entrance of the upper contact hole 152, a corner portion (corner portion) of the first interlayer insulating film 120c is a portion where the trench 158 and the upper contact hole 152 communicate with each other. As a result, a round corner portion A having a round profile is formed in the first interlayer insulating layer 120c. In the figure, the first interlayer insulating film in which the round corner portion A is formed is shown as the first interlayer insulating film 120c, and the other first interlayer insulating film portion is shown as the first interlayer insulating film 120b.

  The remaining thickness D1 of the first interlayer insulating layer 120 exposed through the upper contact hole 152 between the hard mask patterns 130 during the formation of the trench 158 is also etched to form the upper portion. A depth of the contact hole 152 extends downward to form a contact hole 152a exposing the first etching stop insulating film 112.

  If necessary, the depth D2 from the upper surface of the first interlayer insulating film 120b to the bottom surface of the trench 158 (the upper surface of the first interlayer insulating film 120c) is the first interlayer exposed through the upper contact hole 152. The remaining thickness D1 of the insulating film 120 (see FIGS. 2G and 2H) can be set to be the same. However, the present invention is not limited to this. In some cases, the depth D2 of the trench 158 may be smaller or larger than the residual thickness D1 of the first interlayer insulating film 120.

  Referring to FIG. 2J, the hard mask pattern 130 is removed. In order to remove the hard mask pattern 130, for example, a wet etching process may be used.

  Referring to FIG. 2K, the first etching stop is exposed at the bottom surface of the contact hole 152a formed in the first interlayer insulating film 120 using the first interlayer insulating film 120 and the buffer insulating film 136b as an etching mask. The insulating film 112 is anisotropically etched to expose a conductive region (not shown) of the semiconductor substrate 10. When the semiconductor device having the layout of FIG. 1 is manufactured, the active region 12 is exposed at the bottom surface of the contact hole 152a.

  2K, a plurality of contact holes 152a exposing the conductive regions of the semiconductor substrate 10 are formed in the first interlayer insulating layer 120c, and the hard mask pattern 130 is formed above the contact holes 152a. The width of the contact hole 152a along the first direction (y direction in FIG. 1) parallel to the extending direction is formed in the first interlayer insulating film 120c forming both side walls of the contact hole 152a in the first direction. Since the width is limited by the round corner portion A, the width thereof is variable depending on the distance from the semiconductor substrate 10. Further, the width of the contact hole 152a along the second direction (x direction in FIG. 1) perpendicular to the first direction at the upper part of the contact hole 152a is equal to the both side walls above the contact hole 152a in the second direction. Since the width is limited by the vertical sidewall of the first interlayer insulating film 120b, the width is constant depending on the distance from the substrate.

  Referring to FIG. 2L, the contact hole 152a and the trench 158 are filled with a conductive material to form a contact plug 162 formed in the contact hole 152a and a wiring line 168 formed in the trench 158. .

  After depositing the conductive material on the resultant structure in which the contact hole 152a and the trench 158 are formed to form the wiring line 168, the upper surfaces of the interlayer insulating layer 120b and the buffer insulating layer 136c are exposed. A CMP (chemical mechanical polishing) or etchback process can be performed.

  The conductive material may be a metal such as W, Cu, Ti, or Ta, a metal nitride such as WN, TiN, or TaN, or doped polysilicon.

  Since a round corner portion A is formed in the first interlayer insulating film 120c at a portion where the contact hole 152a and the trench 158 communicate with each other in the vicinity of the entrance of the contact hole 152a, the contact hole 152a and the contact hole 152a In the contact region 164 where the contact plug 162 and the wiring line 168 are integrally connected when the contact plug 162 and the wiring line 168 are integrally formed by filling the trench 158 with a conductive material, The width of the contact plug 162 is limited by the round corner portion A, and a cross-sectional area larger than the middle portion and the lower portion of the contact plug 162 is formed on the upper portion of the contact plug 162 positioned below the wiring line 168 from the bottom. Have

  More specifically, the width Wy of the contact plug 162 along the same first direction (y direction in FIGS. 1 and 2L) as the extension direction of the wiring line 168 in the contact plug 162 is defined as the first interlayer insulation. The width Wy (see FIG. 1) limited by the round corner portion A formed in the film 120c is variable depending on the distance from the upper surface of the semiconductor substrate 10. That is, the width Wy of the contact plug 162 in the first direction is the width at the top of the contact plug 162 adjacent to the contact region 164 (a part of the width Wy is represented by Wy1 in FIG. 2L). The contact plug 162 is larger than the width at the middle portion and the lower portion thereof (in FIG. 2L, a part of the width Wy is represented by Wy2).

  On the other hand, the width Wx of the contact plug 162 along the second direction (the x direction in FIGS. 1 and 2L) perpendicular to the extending direction of the wiring line 168 in the contact plug 162 is vertical to the first interlayer insulating film 120b. The width Wx is limited by the side wall, and the width Wx is constant depending on the distance from the upper surface of the semiconductor substrate 10. The width Wx of the contact plug 162 along the second direction is substantially the same as the width WB along the second direction of the wiring line 168.

  As described above, the contact region 164 whose cross-sectional area is widened by the round corner portion A is secured between the contact plug 162 and the wiring line 168, so that the contact plug 162 and the wiring line 168 are secured. The contact resistance between them can be reduced and the electrical characteristics can be improved.

  The contact plug 162 and the wiring line 168 constitute the direct contact 20 and the bit line 30 according to the layout of FIG. The direct contact 20 and the bit line 30 have a structure in which the direct contact 20 and the bit line 30 are communicated with each other through a contact region 164 widened by the round corner portion A. Accordingly, the contact resistance between the direct contact 20 and the bit line 30 can be reduced, and the electrical characteristics of the semiconductor device can be improved.

  3A and 3B are partially cutaway perspective views illustrating a method of manufacturing a semiconductor device according to a second reference example of the present invention in order of processes. 3A and 3B illustrate a process for integrally forming the direct contact 20 and the bit line 30 according to the layout of FIG. 3A and 3B are partially cutaway perspective views of a portion corresponding to the “B” region in FIG.

  The semiconductor device manufacturing method according to the second reference example of the present invention is similar to the semiconductor device manufacturing method according to the first reference example described with reference to FIGS. 2A to 2L. However, in the second reference example, as described with reference to FIG. 2K, when the first etching stop insulating film 112 is removed to expose the conductive region of the semiconductor substrate 10, the first interlayer insulating film is used. The first etching stop insulating film 112 is removed in a state where the hard mask pattern 130 remains on 120b. 3A and 3B, the same reference numerals as those in FIGS. 2A to 2L denote the same members. Therefore, detailed description thereof will be omitted in this example.

  Referring to FIG. 3A, as described with reference to FIGS. 2A to 2I, the contact hole 152a exposing the first etching stop insulating film 112 on the semiconductor substrate 10 is communicated with the contact hole 152a. After the process to form the trench 158, the exposed portion of the first etching stop insulating film 112 is removed using the hard mask pattern 130, the first interlayer insulating films 120b and 12c, and the buffer insulating film 136b as an etching mask. Then, a conductive region (not shown) of the semiconductor substrate 10 is exposed at the bottom surface of the contact hole 152a.

  Referring to FIG. 3B, a conductive layer 160 is formed to fill the contact hole 152a and the trench 158 by depositing a conductive material with the hard mask pattern 130 remaining on the interlayer insulating layer 120b. Further details regarding the conductive material are as described with reference to FIG. 2L.

  Next, a part of the conductive layer 160 and the hard mask pattern 130 are removed until the upper surfaces of the interlayer insulating film 120b and the buffer insulating film 136b are exposed by a CMP or etch back process, as shown in FIG. 2L. Obtain the result.

  4A to 4E are partially cutaway perspective views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention, according to a process order. 4A to 4E illustrate a process for integrally forming the direct contact 20 and the bit line 30 according to the layout of FIG. 4A and 4B are partially cutaway perspective views of a portion corresponding to the “A” region in FIG. 1, and FIGS. 4C to 4E are portions of the portion corresponding to the “B” region in FIG. It is a notch perspective view.

  The semiconductor device manufacturing method according to the first embodiment of the present invention is similar to the semiconductor device manufacturing method according to the first reference example described with reference to FIGS. 2A to 2L. However, in the first embodiment, when the trench 158 (see FIG. 2I) is formed, the second etching stop insulating film 122 is used as an etching stop layer. 4A to 4E, the same reference numerals as those in FIGS. 2A to 2L denote the same members. Therefore, detailed description thereof will be omitted in this example.

  Referring to FIG. 4A, a first etching stop insulating film 112, a first interlayer insulating film 120, a second etching stop insulating film 122, and a second interlayer insulating film 124 are sequentially formed on the semiconductor substrate 10.

  The first etching stop insulating film 112 serves as an etching stop layer when the first interlayer insulating film 120 is etched, and the second etching stop insulating film 122 is used when the second interlayer insulating film 120 is etched. It is to be formed so as to serve as an etching stop layer. The first etch stop insulating film 112 and the second etch stop insulating film 122 may be made of a material that provides an etch selectivity different from that of the first interlayer insulating film 120 and the second interlayer insulating film 124. Depending on the material of the first interlayer insulating film 120 and the second interlayer insulating film 124, the first etching stop insulating film 112 and the second etching stop insulating film 122 may be, for example, a silicon nitride film, a silicon oxide film, or a silicon oxide film. It can be made of a nitride film or a silicon carbide film. The first etching stop insulating film 112 and the second etching stop insulating film 122 may be made of the same material or different materials. For example, the first etch stop insulating film 112 and the second etch stop insulating film 122 may each be formed to a thickness of about 500 mm.

  The constituent materials of the first interlayer insulating film 120 and the second interlayer insulating film 124 are as described for the first interlayer insulating film 120 with reference to FIG. 2A. The first interlayer insulating layer 120 and the second interlayer insulating layer 124 may be made of the same material or different materials.

  A plurality of first mask patterns 134 are formed on the second interlayer insulating film 124 by the same method as described in FIG. 2A.

  Referring to FIG. 4B, a buffer insulating layer 136 and a plurality of second mask patterns 138a are formed on the first mask pattern 134 by the same method as described with reference to FIGS. 2B to 2E. A hard mask pattern 130 composed of two mask patterns 138a is formed.

  Referring to FIG. 4C, an opening for partially exposing the upper surface of the buffer insulating layer 136b and the upper surface of the hard mask pattern 130 on the resultant structure on which the hard mask pattern 130 is formed in the same manner as described with reference to FIG. 2F. A third mask pattern 140 formed with 140a is formed.

  Next, the buffer insulating film 136b, the second interlayer insulating film 124, the second etching stop insulating film 122, and the first interlayer insulating film 120 are formed using the hard mask pattern 130 and the third mask pattern 140 as etching masks, respectively. The upper contact hole 152 is formed by sequentially performing anisotropic dry etching. At this time, as described with reference to FIG. 2G, the first interlayer insulating film 120 having a predetermined thickness D1 remains on the first etching stop insulating film 112 on the bottom surface of the upper contact hole 152. The upper contact hole 152 is formed by etching only a part of the total thickness of the first interlayer insulating layer 120.

  Referring to FIG. 4D, after removing the third mask pattern 140, the buffer insulating layer 136b and the second interlayer insulating layer 124 are etched using the hard mask pattern 130 as an etching mask in the same manner as described with reference to FIG. 2I. A plurality of line-shaped trenches 158 extending in parallel with the hard mask pattern 130 are formed. However, in the present embodiment, the second etching stop insulating film 122 is used as an etching stop layer when etching the second interlayer insulating film 124 for forming the trench 158.

  The trench 158 is formed to communicate with the upper contact hole 152. While the trench 158 is formed, the remaining thickness D1 of the first interlayer insulating layer 120 exposed through the upper contact hole 152 between the hard mask patterns 130 is also etched to form the upper contact hole 152. A contact hole 152a is formed to extend downward and expose the first etching stop insulating film 112.

  Referring to FIG. 4E, the bottom surface of the contact hole 152a is exposed through a series of processes as described with reference to FIGS. 2J to 2L or a series of processes as described with reference to FIGS. 3A and 3B. After removing the first etching stop insulating film 112, the contact hole 152a and the trench 158 are filled with a conductive material to form a contact plug 162 and a wiring line 168 having an integral structure.

  When the first etching stop insulating film 112 and the second etching stop insulating film 122 are made of the same material or a material having similar etching characteristics, the first etching stop insulation exposed at the bottom surface of the contact hole 152a. While the film 112 is removed, a portion of the second etching stop insulating film 122 exposed at the bottom surface of the trench 158 is removed together, and the first interlayer insulating film 120 is removed at the bottom surface of the trench 158. Can be exposed. In this case, as illustrated in FIG. 4E, the bottom surface of the wiring line 168 is in direct contact with the top surface of the first interlayer insulating film 120.

  However, the present invention is not limited to this. Although not shown, the second etching stop insulating film 122 may remain on the first interlayer insulating film 120 on the bottom surface of the trench 158 in some cases. In this case, a structure in which a second etching stop insulating film 122 is interposed between the first interlayer insulating film 120 and the wiring line 168 is obtained.

  FIGS. 5A to 5E are partially cutaway perspective views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention, according to a process sequence. FIGS. 5A to 5E illustrate a process for integrally forming the direct contact 20 and the bit line 30 according to the layout of FIG. 5A and 5B are partially cutaway perspective views of a portion corresponding to the “A” region in FIG. 1, and FIGS. 5C to 5E are partially cutaway portions of the portion corresponding to the “B” region in FIG. FIG.

  A method of manufacturing a semiconductor device according to the second embodiment of the present invention is similar to the method of manufacturing a semiconductor device according to the first reference example described with reference to FIGS. 2A to 2L. However, in the first reference example, the trench 158 is formed after the upper contact hole 152 is formed first, but in the second embodiment, the contact hole 152a is formed after the trench 158 is formed first. 5A to 5F, the same reference numerals as those in FIGS. 2A to 2L denote the same members. Therefore, in this example, detailed description thereof is omitted.

  Referring to FIG. 5A, after the first etching stop insulating film 112 and the first interlayer insulating film 120 are formed on the semiconductor substrate 10 by the same method as described with reference to FIGS. 2A to 2E, the first mask pattern 134 and the first mask pattern 134 are formed. A hard mask pattern 130 composed of two mask patterns 138a is formed.

  Next, the buffer insulating film 136 and a part of the first interlayer insulating film 120 are etched using the hard mask pattern 130 as an etching mask to form a plurality of line-shaped trenches 558 extending in parallel with the hard mask pattern 130. (Note that FIGS. 5A and 5B show the buffer insulating film 136c after this etching).

  Referring to FIG. 5B, a third mask pattern 540 having an opening 540a exposing a part of the hard mask pattern 130 and a part of the bottom surface of the trench 558 is formed.

  The constituent material of the third mask pattern 540 is as described for the third mask pattern 140 with reference to FIG. 2F.

  Referring to FIG. 5C, the first interlayer insulating layer 120 is etched using the hard mask pattern 130 and the third mask pattern 540 as an etching mask and the first etching stop insulating layer 112 as an etching stop layer. Thus, a contact hole 552 is formed. A portion of the first etch stop insulating layer 112 is exposed through the contact hole 552.

  Referring to FIG. 5D, a step of removing a portion of the first etching stop insulating film 112 exposed through the contact hole 552 and a step of removing the third mask pattern 540 and the hard mask pattern 130. Each. As a result, the inside of the contact hole 552 and the inside of the trench 558 are completely exposed.

  Here, of the first etching stop insulating film 112 removal process and the third mask pattern 540 and hard mask pattern 130 removal process, which process is performed first is not particularly limited. For convenience, a desired process can be performed first.

  Referring to FIG. 5E, in the same manner as described with reference to FIG. 2L, the contact holes 552 and the trenches 558 are filled with a conductive material, and the contact holes 552 and the trenches 558 each have an integral structure. And a wiring line 168 is formed.

  6A to 6E are partially cutaway perspective views illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention according to a process order. 6A to 6E illustrate a process for integrally forming the direct contact 20 and the bit line 30 according to the layout of FIG. 6A and 5B are partially cutaway perspective views of a portion corresponding to the “A” region in FIG. 1, and FIGS. 6C to 6E are partially cutaway portions of the portion corresponding to the “B” region in FIG. FIG.

  A method of manufacturing a semiconductor device according to the third embodiment of the present invention is similar to the method of manufacturing a semiconductor device according to the second embodiment described with reference to FIGS. 5A to 5E. However, in the third embodiment, when the trench 558 (see FIG. 5A) is formed, the second etching stop insulating film 122 is used as an etching stop layer. 6A to 6E, the same reference numerals as those in FIGS. 2A to 2L, 4A to 4E, and 5A to 5E denote the same members. Therefore, in this example, detailed description thereof is omitted.

  Referring to FIG. 6A, the first etching stop insulating film 112, the first interlayer insulating film 120, the second etching stop insulating film 122, and the second etching stop are formed on the semiconductor substrate 10 in the same manner as described with reference to FIGS. 4A and 4B. After sequentially forming the two interlayer insulating film 124, a plurality of first mask patterns 134 and a buffer insulating film 136 are formed thereon, and a plurality of second mask patterns 138a are formed on the buffer insulating film 136c using these. Then, a hard mask pattern 130 including the first mask pattern 134 and the second mask pattern 138a is formed.

  Next, the hard mask pattern is etched using the hard mask pattern 130 as an etching mask and the second etching stop insulating film 122 as an etching stop layer to etch the buffer insulating film 136 and the second interlayer insulating film 124, and the hard mask pattern A plurality of line-shaped trenches 558 extending in parallel with 130 are formed.

  Referring to FIG. 6B, a third mask pattern 540 having an opening 540a for exposing a part of the hard mask pattern 130 and a part of the bottom surface of the trench 558 is formed by the same method as described with reference to FIG. 5B. .

  Referring to FIG. 6C, after the second etch stop insulating film 122 is etched using the hard mask pattern 130 and the third mask pattern 540 as an etching mask, the hard mask pattern 130 and the third mask pattern 540 are then formed. Using the first etching stop insulating film 112 as an etching stop layer using the etching mask as an etching mask, the first interlayer insulating film 120 is etched to form a contact hole 552. A portion of the first etch stop insulating layer 112 is exposed through the contact hole 552.

  Referring to FIG. 6D, a step of removing a portion of the first etch stop insulating film 112 exposed through the contact hole 552 and a step of removing the third mask pattern 540 and the hard mask pattern 130. And each. As a result, the inside of the contact hole 552 and the inside of the trench 558 are completely exposed.

  Here, it is not particularly limited which of the first etching stop insulating film 112 and the third mask pattern 540 and the hard mask pattern 130 is removed first. For the convenience of the process, a desired process can be performed first. In addition, as described with reference to FIG. 4E, the first etching stop insulating film 112 exposed at the bottom surface of the contact hole 552 is removed in a state where the second etching stop insulating film 122 is exposed. If the first etch stop insulating film 112 and the second etch stop insulating film 122 are made of the same material or materials having similar etching characteristics, the first etch stop exposed at the bottom surface of the contact hole 552 is used. While the insulating film 112 is removed, the portion of the second etching stop insulating film 122 exposed on the bottom surface of the trench 558 is removed together, and the trench 558 as illustrated in FIG. 6D. The first interlayer insulating layer 120 may be exposed at the bottom surface.

  Referring to FIG. 6E, in the same manner as described with reference to FIG. 2L, the contact hole 552 and the trench 558 are filled with a conductive material, and the contact hole 552 and the trench 558 each have an integral structure. And a wiring line 168 is formed.

  As described with reference to FIG. 6D, while the first etching stop insulating film 112 exposed at the bottom surface of the contact hole 552 is removed, the trench 558 of the second etching stop insulating film 122 is removed. If the portions exposed on the bottom surface of the wiring line 168 are removed together, the bottom surface of the wiring line 168 is in direct contact with the top surface of the first interlayer insulating film 120 as illustrated in FIG. 6E. However, the present invention is not limited to this. Although not shown, the second etching stop insulating film 122 may remain on the first interlayer insulating film 120 on the bottom surface of the trench 558 in some cases. In this case, a structure in which a second etching stop insulating film 122 is interposed between the first interlayer insulating film 120 and the wiring line 168 is obtained.

  The present invention has been described with reference to the preferred embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made by those skilled in the art within the technical idea and scope of the present invention.

  The present invention can be suitably applied to technical fields related to semiconductor devices and manufacturing methods thereof.

10 Semiconductor substrate,
12 active region,
20 Direct contact,
30 bit lines,
112 first insulating film for stopping etching,
120, 120b, 120c first interlayer insulating film,
120a low surface area,
122 second etching stop insulating film,
124 second interlayer insulating film,
130 hard mask pattern,
134 a first mask pattern;
136, 136b, 136c buffer insulating film,
136a recess area,
138 second mask layer,
138a second mask pattern,
140 third mask pattern,
140a opening,
152 upper contact hole,
152a contact hole,
158 trench,
160 conductive layer,
162 contact plug,
164 contact area,
168 Wiring line,
558 trench,
540 third mask pattern,
540a opening,
552 Contact hole.

Claims (16)

Forming an insulating film covering a conductive region on the semiconductor substrate on the semiconductor substrate;
Forming a plurality of first mask patterns extending in parallel with each other in a first direction at a first pitch on the insulating film;
Forming a buffer insulating film covering both side walls of the plurality of first mask patterns;
Among the plurality of first mask patterns, the plurality of first mask patterns and the buffer insulating film are formed so that one second mask pattern is formed in a space between two adjacent first mask patterns. Forming a plurality of second mask patterns each extending in parallel with each of the plurality of first mask patterns, each being self-aligned;
A part of the buffer insulating film and a part of the insulating film are removed, and a plurality of trenches extending in parallel with the first mask pattern and the second mask pattern are communicated with the trenches, respectively. Forming a plurality of contact holes exposing the conductive regions of the semiconductor substrate;
Simultaneously forming a contact plug formed in the contact hole by filling a conductive material in the contact hole and the trench, and a plurality of wiring lines formed in the trench integrally with the contact plug; Including
The step of forming the insulating film includes:
Forming a first etching stop insulating film covering a conductive region on the semiconductor substrate;
Forming a first interlayer insulating film on the first etching stop insulating film;
Forming a second etching stop insulating film on the first interlayer insulating film;
Forming a second interlayer insulating film on the second etching stop insulating film. A method of manufacturing a semiconductor device, comprising: The first etching stop insulating film and the second etching stop insulating film are made of insulating films having different etching characteristics from the first interlayer insulating film and the second interlayer insulating film, respectively.
The first etching stop insulating film and the second etching stop insulating film, and the first interlayer insulating film and the second interlayer insulating film are selected from the group consisting of an oxide film, a nitride film, an oxynitride film, and a silicon carbide film, respectively. The method for manufacturing a semiconductor device according to claim 1, comprising any one of the films described above. Forming the contact hole comprises:
Etching the first interlayer insulating film using the first etching stop insulating film as an etching stop layer;
Etching the first etching stop insulating film exposed through the first interlayer insulating film using the first mask pattern and the second mask pattern as an etching mask to expose the conductive region, and
Forming the trench comprises:
3. The method of claim 1, further comprising: etching the second interlayer insulating film and the buffer insulating film using the second etching stop insulating film as an etching stop layer before the conductive region is exposed. The manufacturing method of the semiconductor element of description. Forming the contact hole comprises:
Etching the first interlayer insulating film until the first etching stop insulating film covering the conductive region is exposed;
Removing the first mask pattern and the second mask pattern in a state where the conductive region is covered with the first etching stop insulating film;
Removing the first etching stop insulating film exposed through the first interlayer insulating film using the first interlayer insulating film and the buffer insulating film as an etching mask to expose the conductive region. The method for manufacturing a semiconductor device according to claim 1, wherein:   The method of claim 4, wherein a wet etching process is used to remove the first mask pattern and the second mask pattern. Forming the plurality of trenches and the plurality of contact holes;
Etching the buffer insulating film and the insulating film using the first mask pattern and the second mask pattern as an etching mask to form a plurality of line-shaped trenches extending in parallel with the first mask pattern and the second mask pattern; ,
Forming a third mask pattern in which an opening exposing a part of the plurality of first mask patterns and the plurality of second mask patterns and a part of the bottom surface of the trench is formed;
Etching the insulating film using the first mask pattern, the second mask pattern, and the third mask pattern as an etching mask to form the contact hole exposing the conductive region, respectively. A method for manufacturing a semiconductor device according to claim 1. The step of forming the insulating film includes:
Forming a first etching stop insulating film covering a conductive region on the semiconductor substrate;
The method according to claim 6, further comprising: forming a first interlayer insulating film on the first etching stop insulating film. The first etching stop insulating film and the first interlayer insulating film are made of insulating films having different etching characteristics,
The first etching stop insulating film and the first interlayer insulating film are each composed of any one film selected from the group consisting of an oxide film, a nitride film, an oxynitride film, and a silicon carbide film. Item 8. A method for manufacturing a semiconductor element according to Item 7. Forming the contact hole comprises:
Etching the first interlayer insulating film using the first etching stop insulating film as an etching stop layer;
Etching the first etching stop insulating film exposed through the first interlayer insulating film using the first mask pattern and the second mask pattern as an etching mask to expose the conductive region. The method of manufacturing a semiconductor element according to claim 7. Forming the contact hole comprises:
Etching the first interlayer insulating film until the first etching stop insulating film covering the conductive region is exposed;
Removing the first mask pattern and the second mask pattern in a state where the conductive region is covered with the first etching stop insulating film;
Removing the first etching stop insulating film exposed through the first interlayer insulating film using the first interlayer insulating film and the buffer insulating film as an etching mask to expose the conductive region. The method of manufacturing a semiconductor element according to claim 7.   The method of claim 10, wherein a wet etching process is used to remove the first mask pattern and the second mask pattern. The step of forming the insulating film includes:
Forming a first etching stop insulating film covering a conductive region on the semiconductor substrate;
Forming a first interlayer insulating film on the first etching stop insulating film;
Forming a second etching stop insulating film on the first interlayer insulating film;
The method according to claim 6, further comprising: forming a second interlayer insulating film on the second etching stop insulating film. The first etching stop insulating film and the second etching stop insulating film are made of insulating films having different etching characteristics from the first interlayer insulating film and the second interlayer insulating film, respectively.
The first etching stop insulating film, the second etching stop insulating film, the first interlayer insulating film, and the second interlayer insulating film are each formed of an oxide film, a nitride film, an oxynitride film, and a silicon carbide film. A method for manufacturing a semiconductor element according to claim 12. Forming the trench comprises:
Etching the buffer insulating film and the second interlayer insulating film using the first mask pattern and the second mask pattern as an etching mask, and using the second etching stop insulating film as an etching stop layer,
Forming the contact hole comprises:
Etching the first interlayer insulating film using the first etching stop insulating film as an etching stop layer;
Etching the first etching stop insulating film exposed through the first interlayer insulating film using the first mask pattern and the second mask pattern as an etching mask to expose the conductive region. The method of manufacturing a semiconductor element according to claim 12. Forming the trench comprises:
Etching the buffer insulating film and the second interlayer insulating film using the first mask pattern and the second mask pattern as an etching mask, and using the second etching stop insulating film as an etching stop layer,
Forming the contact hole comprises:
Etching the first interlayer insulating film until the first etching stop insulating film covering the conductive region is exposed;
Removing the first mask pattern and the second mask pattern in a state where the conductive region is covered with the first etching stop insulating film;
Removing the first etching stop insulating film exposed through the first interlayer insulating film using the first interlayer insulating film and the buffer insulating film as an etching mask to expose the conductive region. The method of manufacturing a semiconductor element according to claim 12.   The method of claim 15, wherein a wet etching process is used to remove the first mask pattern and the second mask pattern.

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