200901370 九、發明說明： 【發明所屬之技術領域】 本申凊案主張2007年6月15日向韓國智財局申請之韓國 專利申請案第1〇_2〇〇7_〇〇591〇3號之權利該案之全文以弓丨 用的方式併入本文中。 本申睛案是2006年3月6曰申請之已共同讓與之美國專利 申請案第11/367,437號的部份接續中請案，其相關標的以 引用的方式併入本文中。 本發明係關於一種具有細微圖案配線之半導體裝置及一 種有關製造方法。更特定而言，本發明係關於一種半導體 裝置，其具有具備細微間距之細微圖案配線及分別將該等配 線與相鄰導電區域連接之接觸栓；及一種有關製造方法。 【先前技術】 製造高度整合半導體裝置需要形成及使用恆久更微細之 圖案及相關元件。亦即，為將形成現代半導體裝置之眾多 兀件整合於日益變小之區域中，個別元件之大小必須減小 且相鄰元件之間的分離距離亦必須減小。元件大小之減小 及有關元件之密度增大係部分地由連接各種元件之導電圖 案之"間距”之減小來實現。間距通常由圖案本身之寬度加 將圖案與相鄰圖案或有關元件分離之間隙之寬度的總和來 界定。 界定現代半導體裝置之積體密度之所需間距（或多個間 距）很大程度上為個別半導體裝置之全面設計規則之產 物。在許多情況下，現代設計規則要求已達到現有光微影 設備之解析度及效能極限之圖案間距。舉例而言，可用光 129500.doc 200901370 微影設備之解析度限制現在限定半導體基板之極小（亦即 乍）區域中之細微間距接觸孔之可實現大小。對於現代半 導體裝置中之接觸孔之界定及製造之該等實際極限隨對於 相鄰接觸孔之分離距離及對準所設置之最低限度而變化。 現有光微影解析度極限及限制完全不能在保持可接受之設 計限度的同時形成具有更細微間距之接觸孔。200901370 IX. Description of the invention: [Technical field to which the invention belongs] This application claims the Korean Patent Application No. 1〇_2〇〇7_〇〇591〇3, which was applied to the Korea Intellectual Property Office on June 15, 2007. The full text of the case is hereby incorporated by reference. This application is hereby incorporated by reference in its entirety in its entirety in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all The present invention relates to a semiconductor device having fine pattern wiring and a related manufacturing method. More particularly, the present invention relates to a semiconductor device having fine pattern wiring having fine pitches and contact plugs respectively connecting the wiring lines to adjacent conductive regions; and a related manufacturing method. [Prior Art] The fabrication of highly integrated semiconductor devices requires the formation and use of more permanent patterns and related components. That is, in order to integrate a plurality of components forming a modern semiconductor device into increasingly smaller regions, the size of individual components must be reduced and the separation distance between adjacent components must also be reduced. The reduction in the size of the components and the increase in the density of the associated components are achieved in part by the reduction in the "pitch" of the conductive patterns connecting the various components. The spacing is usually the width of the pattern itself plus the pattern and adjacent patterns or related components. The sum of the widths of the separation gaps is defined. The required spacing (or spacing) that defines the bulk density of modern semiconductor devices is largely a product of the overall design rules of individual semiconductor devices. In many cases, modern design The rules require that the pattern spacing of the resolution and performance limits of existing photolithographic devices be reached. For example, the resolution limit of available 129500.doc 200901370 lithography equipment now limits the area of the semiconductor substrate that is extremely small (ie, 乍). The fine-grained contact holes can be sized. The practical limits for the definition and fabrication of contact holes in modern semiconductor devices vary with the separation distances and alignments for adjacent contact holes. Resolution limits and limits cannot be formed at all times while maintaining acceptable design limits The fine pitch contact holes.
所達到之習知間距極限之一常見實例可見於半導體記憶 體裝置中之相鄰位元線之設計及製造令。I例而纟，某些 高度整合快閃記憶體褒置中之位元線之間的間距已急劇減 小至30 nm範圍内之特徵大小。可用光微影設備完全不能 使用習知方式來充分地形成該等特徵。 在現代半導體記憶體裝置中之，，側向地"排狀位元線之 形成期間’各別接觸栓通常經形成以將每一位元線”垂直 地，，與相關作用區域或某—其他元件連接。術語側向及垂 直實質上為相對的且用以幫助描述。I穿以下描述，不因 使用β亥專描述性術語而要求任音總打泌％ . 文八仕思4何形態。在已形成接觸 栓之後’形成電接觸各別接觸於々^ j按觸栓之位兀線。在上覆於所排 列之先前形成且垂直延仲夕拔艇& , 、狎之接觸栓上之側向延伸之位元線 的此製造期間，必須遵守某些對準限度（亦即接觸检與位 元線之間的錯位容差）以確保所得半導體裝置之可靠性。 該等對準限度很大程度上由在户妖4斗 由存在於相鄰位元線及/或接觸 栓之間的分離距離界定。囡卜 1疋因此，減小位元線及/或接觸栓 之間距將限制對準限度。 【發明内容】 在一實施例中 本發明提供一種半導體裝置，其包含： 129500.doc 200901370 一形成於一半導體基板上之第一層間絕緣層，其中哕a 層間絕緣層包含交錯之蝕刻殘餘部分及未蝕刻部分。亥第一 每一蝕刻殘餘部分界定一接觸孔及—在— 其中 隹接觸區域中愈 接觸孔連接之對應線形渠溝的幾何形態，且其中每，、遠 殘餘部分包含一界定該接觸區域之幾彳母蝕刻 分；一填充該接觸孔之接觸栓及一填 狀# 具兄該線形渠溝之 配線層，其中該接觸栓經由該接觸區域將該半導體、，、 一導電區域與該配線層電連接。 -土板之 在另-實施例中，本發明提供_種製造―半 方法，其包含：在一半導體基板上形成一第— = 緣層；在該第-触刻終止絕緣層上形成一層間絕緣層；在 該層間絕緣膜上在一第一方向i ^ 乃Π上形成一複合硬遮 其中該複合硬遮罩圖案包含—縫免Μ Λ 莱’ ^ ^3緩衝絕緣膜之殘餘部分；在 该禝合硬遮罩圖案上在一不同於該第一方向之 形成一交叉遮罩圖案，其令該交又遮罩圖案包含向上 該開口選擇性地曝該緩衝絕緣膜之該等殘餘部分之 使用該複合硬遮罩圖案與該交 刀， 緩衝絕緣層之該等殘餘部分 Μ Ί /AA 寸降口1刀以形成接觸孔至 一冰度，從而在該等接觸孔之 主 m Μ ^ &ί -Γ ^ -表面與該第—蝕刻終止絕 緣：之間打一殘餘分離厚度；移除該 該層間絕緣膜之殘餘蝕刻残案以曝 I刀，敍刻s亥層間絕缓居 曝殘餘#刻部分以形成# I 專 分離厚度以形成複數個接 ❻除該殘餘 曝該第-勒列Μ 該複數個接觸孔選擇性地 ' Χ、'、絕緣層之部分；以至少一導電材料填充 該複數個接觸孔及該複數個線形渠溝，從而使複數= 129500.doc 200901370 該複數個接觸孔中之接觸栓及分別連接之複數個處於該複 數個線形渠溝中之配線層同時且一體成型。 在另一實施例中，本發明提供一種製造一半導體裝置之 方法，其包含：在一半導體基板上形成一第一钱刻終止絕 緣層；在該第—㈣終止絕緣層上形成-第-層間絕緣 層；在該第-層間絕緣膜上形成一第二蝕刻終止絕緣層； 在該第二姓刻終止絕緣膜上形成一第二層間^ 第二層間絕緣膜上在-第—方向上形成—複合硬遮= 案其^該複合硬遮罩圖案包含—緩衝絕緣膜之殘餘部 刀’在5亥複合硬遮罩圖案上在一不同於該第—方向之第二 方向上形成一父又遮罩圖案’其中該交叉遮罩圖案包八一 開口，該開口選擇性地曝該緩衝絕緣膜之餘: 部分；使用該複合硬遮罩圖案與該交又遮單圖宰之 2刻該緩衝絕緣層之該等殘餘部分之該㈣部分以穿㈣ 二：層間絕緣層及該第二蝕刻終止絕緣層而形成接觸孔至 ^度’從而在該等接觸孔之底表面與該第—㈣終止絶 緣層之間留下一殘餘分離厚 兮坌- 又移除°亥乂又遮罩圖案以曝 “第-層間絕緣膜之殘餘_部分；㈣該第 層之該等曝殘餘韻刻部分向下直至該第 緣： 以形成複數個線形渠溝且同時移除該殘餘分離厚戶= =個接觸孔，該複數個接觸孔選擇性地曝該第—钱刻终 及該複數個線形罕溝，：而I ?充複數個接觸孔 中之接觸… 處於該複數個接觸孔 ，及分別連接之複數個處於該複數個線形準溝中 之配線層同時且一體成型。 I小木溝t 129500.doc 200901370 【實施方式】 、本發明現將針對若干例示性實施例參照隨附圖式來描 述。然而，本發明可以許多不同形式來實施且不應視為僅 阳於所說明之實施例。實際上，提供該等實施例作為教示 實例。貝牙圖 < ’各種層、區域及/或^件之厚度及相對 厚度已為清晰而誇示。貫穿書面描述及圖<，相同參考用 以指示相同或類似元件。 圖1為》尤明根據本發明之實施例之配線圖案在半導體基 板上之例示性排列之總布置圖。圖1之布置圖取自其中i 數個位元線30形成快閃記憶體裝置之一部分的實例。铁 而’此實例選擇僅為例示性的，且如由以下實施例所教 不，本發明可應用於任何多種不同半導體裝置及/或苴中 之元件。 〃 然而，參看圖1中說明之實例，複數個位元線3〇中之每 一者具有近似等於對應作用區域12之寬度的線寬度。為達 成說明之目的’已採取任意布置幾何形態且標註此幾何形 態内之某些”方向"以清楚地描述一元件相關於另—者之相 對（及例不性）定向及排歹。該等描述實質上為相對的。 、舉例而言，複數個作用區域12及對應複數個位元線30稱 為在第一方向（亦即”y”方向）上平行延伸。在圖丨之說明實 例中，複數個位元線30中之每一者經由直接接觸2〇與對應 ，作用區域12電連接。複數個位元線3〇以所需位元線間距 "PB"形成。因此，複數個直接接觸2〇亦以位元線間距匕形 成。複數個直接接觸2〇線性地排列在第二方向（亦即 向)上，其中第一方向與第二方向彼此成直角且界定布置 129500.doc -10- 200901370 幾何形態之主側向平面。 圖2A至2L為依序說明根據本發明之實施例之製造半導 體裝置之方法的剖面（或部分剖面）透視圖。圖之八至儿說明 根據圖1之布置之直接接觸2〇與位元線％之一體成型。圖 2A至2F對應於圖j中標識之區域"a”，且圖扣至對應於 圖1中標識之區域"B ”。 參看圖2 A，第一蝕刻終止絕緣層丨丨2及第一層間絕緣層 120依序形成（例如在與由第一方向及第二方向界定之側向 平面正交之第三，'z"方向上垂直地堆疊）於半導體基板10 上，其中界定具有與圖丨中所示之作用區域12之布置類似 之布置的作用區域（未圖示）。 形成包括例如複數個字元線之半導體裝置所需之單位元 件（未圖示）可形成於半導體基板1〇上。第一層間絕緣層12〇 可由複數個覆蓋單位元件之絕緣膜形成。另外，與單位元 件可電連接之導電區域（未圖示）可曝於半導體基板之上 表面上。 第触刻終止絕緣層112充當應用於第一層間絕緣層120 之姓刻製私之姓刻終止層。第一敍刻終止絕緣層1〗2可由 一或多種相對於第一層間絕緣層12〇具有蝕刻選擇性之材 料所形成。在某些實施例中，第一層間絕緣層j2〇及第一 蝕刻終止絕緣層丨12可根據其所需蝕刻選擇特性分別由氮 化矽膜、氧化矽膜、氮氧化矽膜及/或碳化矽層形成。舉 例而言’若第一蝕刻終止絕緣層112為氮化物膜，則第一 層間絕緣層120可為氧化物膜。在一實施例中，將第一蚀 129500.doc 200901370 刻終止絕緣層112形成至約500 A之厚度。 第—層間絕緣層120可由具有相對低介電常數之絕緣材 料形成，以便減小由耦合電容器引起之電阻電容（RC)延 遲’該耦合電容器之產生可歸因於相鄰位元線之間的間隔 寬度減小。舉例而言，第一層間絕緣層120可由正;5夕酸四 乙醋（TEOS)、氟矽酸鹽玻璃（FSG)、SiOC、SiLK等形成。 或者’第一層間絕緣層120可由一或多種選自包括熱形成 氧化物膜、化學氣相沈積（CVD)形成氧化物膜、未換雜石夕 酸鹽玻璃（USG)膜及高密度電漿（HDP)氧化物膜之可能膜 之群的氧化物膜形成。或者，第一層間絕緣層12〇可由一 或多種選自包括SiON、SiN、SiBN及BN之可能膜之群的 氮化物膜形成。或者，第一層間絕緣層！ 2〇可以包括諸如 彼等以上標識者之一或多種氮化物膜及一或多種氧化物膜 之堆疊結構來形成。 第一複數個遮罩圖案134係使用習知光微影技術而形成 於第-層間絕緣層12G上。在說明實例中，第—複數個遮 罩圖案134以第一間距2P來形成，該第一間距2p為所需”最 終”間距P (參見例如圖2 E中之複合硬遮罩圖案〗3 〇)之彼間 距的兩倍。在說明實例中，複合硬遮罩圖案13〇之最終間 距P與圖1之位元線30之所需位元線間距Pb相同。舉例而 言’界定每-第-遮罩圖案134之第_寬度％可設計為第 —間距2P之1/4。 第-遮罩圖案Π4可由具有與形成第一層間絕緣層12〇之 材料相關的麵刻選擇性的材料（亦即一或多種具有與特定 12950〇.cj〇c 12 200901370 钮刻製程相關之不帽速率的材料)來形成。舉例而 言，第一遮罩圖案134可由—或多種諸如氧化物膜、氮化 物膜、多晶矽膜及/或金屬膜之材 刊付术形成。舉例而言， 若第一層間絕緣層120為氧化物層或氣 層或虱化物膜，則第一遮 罩圖案134可為多晶矽膜。另外，若 右弟—層間絕緣層120為 氮化物膜，則第一遮罩圖案134可為氧化物膜。 參看圖2B，將第一厚度” d”自由第一 W乐遮罩圖案134所曝之 第一層間絕緣層120之上表面中移除，A common example of a conventional pitch limit achieved can be found in the design and manufacture of adjacent bit lines in a semiconductor memory device. In the case of I, the spacing between the bit lines in some highly integrated flash memory devices has been drastically reduced to a feature size in the range of 30 nm. Light lithography devices are completely incapable of using the conventional means to adequately form such features. In modern semiconductor memory devices, during the formation of laterally "striped bit lines, 'each contact plug is typically formed to place each bit line vertically, with the associated active area or some— Other components are connected. The terms lateral and vertical are essentially relative and are used to help describe. I wear the following description, and do not require the use of β Hai descriptive terminology to require the total sound to be secreted. After the contact plug has been formed, 'the electrical contact is formed to contact the 兀 j 按 按 按 按 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触During this fabrication of the laterally extending bit lines, certain alignment limits (i.e., misalignment tolerances between the contact and bit lines) must be observed to ensure the reliability of the resulting semiconductor device. The limit is largely defined by the separation distance between the adjacent bit lines and/or the contact pins in the household demon 4 bucket. Therefore, reducing the distance between the bit lines and/or the contact pins will be Limiting the alignment limit. [Invention] In an embodiment The present invention provides a semiconductor device comprising: 129500.doc 200901370 A first interlayer insulating layer formed on a semiconductor substrate, wherein the 哕a interlayer insulating layer comprises staggered etch residues and unetched portions. An etched residual portion defines a contact hole and a geometry of the corresponding linear trench in which the contact hole is connected in the 隹 contact region, and wherein each, the far residual portion includes a plurality of etched etch points defining the contact region a contact plug filling the contact hole and a wiring layer of the wire-shaped trench, wherein the contact plug electrically connects the semiconductor, and a conductive region to the wiring layer via the contact region. In another embodiment, the present invention provides a fabrication-semi-method comprising: forming a first--edge layer on a semiconductor substrate; forming an interlayer insulating layer on the first-etch-stop insulating layer Forming a composite hard mask on the interlayer insulating film in a first direction i ^ Π , wherein the composite hard mask pattern comprises a slit-free ' 莱 莱 ' ^ ^ 3 buffer insulating film a portion of the hard mask pattern forming a cross mask pattern different from the first direction, wherein the matte mask pattern includes selectively exposing the buffer insulating film to the opening And the residual portion is used in the composite hard mask pattern and the intersection, the residual portion of the buffer insulating layer Μ Ί /AA inch is lowered to form a contact hole to an ice, so that the contact hole is the main m Μ ^ & ί -Γ ^ - surface and the first etch stop insulation: a residual separation thickness is applied; the residual etching residue of the interlayer insulating film is removed to expose the I knife, and the s Releasing the residual portion to form a partial separation thickness to form a plurality of junctions in addition to the residual exposure of the first-lele column 选择性 the plurality of contact holes selectively 'Χ,', portions of the insulating layer; a conductive material filling the plurality of contact holes and the plurality of linear trenches such that the complex number = 129500.doc 200901370 the contact plugs in the plurality of contact holes and the plurality of wires respectively connected in the plurality of linear trenches The layers are simultaneously and integrally formed. In another embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: forming a first dielectric termination insulating layer on a semiconductor substrate; forming - a first interlayer on the (IV) termination insulating layer An insulating layer; a second etch-stop insulating layer is formed on the first interlayer insulating film; and a second interlayer is formed on the second-last insulating film; the second interlayer insulating film is formed on the -first direction - Composite hard mask = the composite hard mask pattern comprising - the residual knife of the buffer insulating film - forming a father and a cover in a second direction different from the first direction on the 5H composite hard mask pattern a cover pattern 'where the cross-mask pattern includes an opening, the opening selectively exposing the buffer insulating film: a portion; the buffer is insulated using the composite hard mask pattern and the cross-covering The (four) portion of the remaining portions of the layer form a contact hole to the second end by the (four) two: interlayer insulating layer and the second etch-stop insulating layer to thereby insulate the bottom surface of the contact holes from the first (four) termination. Leave a residue between the layers Separating the thick 兮坌 - and removing the 乂 乂 遮 mask pattern to expose the "residual _ portion of the first interlayer insulating film; (d) the exposed residual rhyme portion of the first layer down to the first edge: to form a plurality a linear trench and simultaneously removing the residual separation thicker == a contact hole, the plurality of contact holes selectively exposing the end of the first money and the plurality of linear halves, and I? filling a plurality of contacts The contact in the hole is in the plurality of contact holes, and the plurality of wiring layers respectively connected in the plurality of linear quasi-grooves are simultaneously and integrally formed. I Xiaomugou t 129500.doc 200901370 [Embodiment] The invention will be described with respect to a number of exemplary embodiments, which may be embodied in many different forms, and should not be construed as being merely to the illustrative embodiments. In fact, the embodiments are provided as illustrative examples. The thicknesses and relative thicknesses of the various layers, regions and/or components have been clearly and exaggerated. Throughout the written description and drawings, the same reference is used to refer to the same or similar elements. According to this A general layout of an exemplary arrangement of wiring patterns on a semiconductor substrate of an embodiment of the invention. The layout of Figure 1 is taken from an example in which i number of bit lines 30 form part of a flash memory device. The example selections are merely illustrative, and as taught by the following embodiments, the invention is applicable to any of a variety of different semiconductor devices and/or components in the crucible. 〃 However, referring to the example illustrated in Figure 1, a plurality of bits Each of the lines 3〇 has a line width approximately equal to the width of the corresponding active area 12. For the purpose of illustration, 'arranged geometry has been taken and some of the "directions" within this geometry are marked to clearly Describe a component's relative (and unequal) orientation and drainage. These descriptions are essentially relative. For example, the plurality of active regions 12 and corresponding plurality of bit lines 30 are said to extend in parallel in the first direction (i.e., the "y" direction). In the illustrated embodiment of the figure, each of the plurality of bit lines 30 is electrically coupled to the corresponding active area 12 via a direct contact 2〇. A plurality of bit lines 3〇 are formed by the required bit line spacing "PB". Therefore, a plurality of direct contacts 2〇 are also formed by bit line spacing 匕. A plurality of direct contacts 2 are linearly arranged in a second direction (i.e., the direction), wherein the first direction and the second direction are at right angles to each other and define a major lateral plane of the geometry of 129500.doc -10- 200901370. 2A through 2L are cross-sectional (or partial cross-sectional) perspective views sequentially illustrating a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. Figure 8 to the description of the direct contact 2〇 and the bit line % of the arrangement according to the arrangement of Figure 1. Figures 2A through 2F correspond to the area "a" identified in Figure j, and are linked to the area "B" corresponding to that identified in Figure 1. Referring to FIG. 2A, the first etch-stop insulating layer 丨丨2 and the first interlayer insulating layer 120 are sequentially formed (for example, in a third plane orthogonal to the lateral plane defined by the first direction and the second direction, 'z" The direction is vertically stacked on the semiconductor substrate 10, wherein an active region (not shown) having an arrangement similar to the arrangement of the active regions 12 shown in FIG. A unit (not shown) required to form a semiconductor device including, for example, a plurality of word lines may be formed on the semiconductor substrate 1A. The first interlayer insulating layer 12'' may be formed of a plurality of insulating films covering the unit elements. Further, a conductive region (not shown) electrically connectable to the unit element may be exposed on the upper surface of the semiconductor substrate. The first etch stop insulating layer 112 serves as a surnamed end layer of the surname applied to the first interlayer insulating layer 120. The first imprint termination insulating layer 1 can be formed of one or more materials having an etch selectivity with respect to the first interlayer insulating layer 12A. In some embodiments, the first interlayer insulating layer j2 and the first etch-stop insulating layer 12 may be respectively selected from a tantalum nitride film, a hafnium oxide film, a hafnium oxynitride film, and/or according to a desired etching selectivity property thereof. A layer of tantalum carbide is formed. For example, if the first etch stop insulating layer 112 is a nitride film, the first interlayer insulating layer 120 may be an oxide film. In one embodiment, the first etch 129500.doc 200901370 terminates the insulating layer 112 to a thickness of about 500 Å. The first interlayer insulating layer 120 may be formed of an insulating material having a relatively low dielectric constant in order to reduce a resistance capacitance (RC) delay caused by a coupling capacitor. The generation of the coupling capacitor is attributable to the relationship between adjacent bit lines. The spacing width is reduced. For example, the first interlayer insulating layer 120 may be formed of positive; TEOS, fluorosilicate glass (FSG), SiOC, SiLK, or the like. Alternatively, the first interlayer insulating layer 120 may be formed of one or more selected from the group consisting of a thermally formed oxide film, a chemical vapor deposition (CVD) oxide film, a non-exchanged silicate glass (USG) film, and a high-density electricity. An oxide film of a group of possible films of a slurry (HDP) oxide film is formed. Alternatively, the first interlayer insulating layer 12 may be formed of one or more nitride films selected from the group consisting of SiON, SiN, SiBN, and BN. Or, the first interlayer insulation layer! The ruthenium may be formed by a stacked structure such as one or more of the above-identified ones or a plurality of nitride films and one or more oxide films. The first plurality of mask patterns 134 are formed on the first interlayer insulating layer 12G using a conventional photolithography technique. In the illustrated example, the first plurality of mask patterns 134 are formed at a first pitch 2P that is the desired "final" pitch P (see, for example, the composite hard mask pattern in FIG. 2E). ) twice the distance between them. In the illustrated example, the final pitch P of the composite hard mask pattern 13 is the same as the desired bit line pitch Pb of the bit line 30 of FIG. For example, the _width % defining the -th-mask pattern 134 can be designed to be 1/4 of the first-pitch 2P. The first-mask pattern Π4 may be made of a material having a surface-selective property associated with a material forming the first interlayer insulating layer 12 (i.e., one or more having a specific engraving process associated with a specific 12950 〇.cj〇c 12 200901370) Not forming a rate of material) to form. For example, the first mask pattern 134 may be formed by - or a plurality of materials such as an oxide film, a nitride film, a polysilicon film, and/or a metal film. For example, if the first interlayer insulating layer 120 is an oxide layer or a gas layer or a vaporized film, the first mask pattern 134 may be a polysilicon film. Further, if the right interlayer-interlayer insulating layer 120 is a nitride film, the first mask pattern 134 may be an oxide film. Referring to FIG. 2B, the first thickness "d" is removed from the upper surface of the first interlayer insulating layer 120 exposed by the first W-mask pattern 134,
砂除以使得降低表面部 分120a形成於第一層間絕緣層12〇之上表面中。在說明實 施例中，第一厚度"d"具有等於第一遮罩圖案134之第一寬 度買丨之垂直深度。 習知乾式蝕刻製程可用以形成第一層間絕緣層12〇之上 表面中之降低表面部分12〇3。舉例而言，用以形成第—遮 罩圖案m之製程可包括過度姓刻第一層間絕緣層12〇以形 成降低表面部分伽。或者’乾式#刻製程可獨立地透過 第-遮罩圖案U4應用於第一層間層12〇之上表面以形成降 低表面部分120a。然而，降低表面部分120&之形成對本發 明之某些實施例並非必需的且可省略。 參看圖2C，緩衝絕緣層136形成於第一遮罩圖案134之側 壁上以形成具有第一遮罩圖案134之相鄰者之間的預定寬 度的凹槽區域136a。因此，緩衝絕緣層136可經形成以覆 蓋第一遮罩圖案134之上表面及側壁表面以及第—層間絕 緣層120之降低表面部分12〇a。在說明實例中，將緩衝絕 緣層136形成至等於第一厚度"d"之厚度。在此特定實施例 129500.doc -13· 200901370 中，緩衝絕緣層Π6之厚度界定具有等於第一寬度恥之第 二寬度W2之凹槽區域136a。 緩衝絕緣層i 3 6可由-或多種具有與第一層間絕緣層！ 2 〇 之蝕刻特性相同或類似之蝕刻特性的材料來形成。舉例而 言，在一特定實施例中，緩衝絕緣層136由與第一層間絕 緣層120相同之材料來形成。緩衝絕緣層136可為例如氧化 物膜，且例如可使用習知原子層沈積（ALD)製程來形成。 參看圖2D，第二遮罩層138形成於緩衝絕緣層136上。第 二遮罩層138可由一或多種具有與第一遮罩圖案134之蝕刻 特性相同或類似之蝕刻特性的材料來形成。舉例而言，第 二遮罩層138可由一或多種諸如氧化物、氮化物、多晶矽 及/或金屬之材料來形成。舉例而言，當第一層間絕緣層 120及緩衝絕緣層136由氧化物層或氮化物膜形成時第二 遮罩層138可由多晶矽膜形成。若第一層間絕緣層12〇及緩 衝絕緣層136各自由氧化物膜形成，則第二遮罩層138可由 多晶石夕層或氮化物膜形成。 在形成第二遮罩層138之後，凹槽區域136a以形成第二 遮罩層138之材料填充。若緩衝絕緣層136之厚度為第一間 距21>之厚度之1/4，則填充凹槽區域136a之第二遮罩層138 之邛刀之所仔寬度將為第二寬度W2(例如，在說明實例 中’第一間距2P之1/4,或第一寬度Wl)。 參看圖2E ,第二遮罩層138及緩衝絕緣層136之上部側向 延伸部分經移除以曝第一遮罩圖案134之上表面。以此方 式，第二複數個遮罩圖案138a可形成於凹槽區域136a中。 129500.doc • 14- 200901370 、第—複數個遮罩圖案138&以自對準之方式與第一複數個 遮罩圖案134及緩衝絕緣層之殘餘部分n6b交錯。此等平 灯父錯線圖案在第一層間絕緣層120上在第-方向上側向 I伸第—遮罩圖案134及第二遮罩圖案丨3 8a之所得組合 Μ複合硬遮罩圖案13G。複合硬料圖案13G現在可在隨 錢用於第-層間絕緣層120之乾式蝕刻製程期間用作蝕 亥J遮罩。特別值得注意的是複合硬遮罩圖案13〇具有線圖 〇 帛’其現在以等於由等於第一間距2Ρ之1Μ之類似寬度分 離之第一寬度Wl的圖案寬度來重複。因此，硬遮罩圖案 U〇可以等於第—間距2P之1/2的最終間距p來形成，其中 ^〗p可表示可由所使用之光微影設備之解析度極限 獲得的最細微間距。 在剛述過程中，習知上應用之化學機械研磨（CMP)製程 可用以同日寸移除第二遮罩層138及緩衝絕緣層之上部側 向乙伸邛刀。或者，第二遮罩層13 8及緩衝絕緣層136之上 C 冑側向延伸部分可藉由應用獨立習知㈣製程來獨立地移 除，以便形成圖2E中說明之所得結構。舉例而言各別定 時之濕式姓刻製程可獨立地用以移除第二遮罩層US及緩 - 衝絕緣層I36之上部侧向延伸部分。 .參看®2F ’具有選擇性地曝緩衝絕緣層之殘餘部分136a 之上表面及複合硬遮罩圖案130的開口 140a之交又遮罩圖 案140形成於所得結構上。形成於交又遮罩圖案14〇中之線 形開口 140a在與複合硬遮罩圖案13〇正交之第二方向上 伸。線形開口 140a之位置及寬度界定圖^所示之直接= 129500.doc -15· 200901370 觸20之側向幾何形態。在說明實例中，開口 14〇&具有簡單 線性形狀，但本發明之實施例不限於此，且可形成具有更 複雜側向幾何形態之直接接觸20。類似地，交又遮罩圖案 M0不必需與複合硬遮罩圖案130正交，而可具有事實上在 例如5°至90。範圍内之幾何定向。 或者’線性（或線形）交叉遮罩圖案1 40可被由複數個島 形開口形成之交叉遮罩圖案140置換。當直接接觸之最終 布置實質上為非線性（或任意）時，此類交又遮罩圖案i 4〇可 尤其適用。 複合硬遮罩圖案130與交叉遮罩圖案14〇之間的所得上覆 排列選擇性地曝緩衝絕緣層之殘餘部分1366之上表面。緩 衝絕緣層之殘餘部分136b之此等曝部分對應於直接接觸孔 2〇之所需位置。亦即，緩衝絕緣層之曝殘餘部分13补將經 垂直地蝕刻以形成穿過第一層間絕緣層i2〇之接觸孔。 在實施例中，父叉遮罩圖案140由光阻劑膜形成，但 可替代地或附加地由單獨應用或堆疊之多個膜形成，包括 多晶矽膜、氮化物膜、非晶形碳層（ACL)、封蓋層（諸如 SiON、TEOS)及ALD氧化物、抗反射塗層（ARC)膜等。舉 例而s，交又遮罩圖案14〇可由依序堆疊旋塗式碳（s〇c) 膜、矽ARC層及光阻劑層，或由依序堆疊s〇c膜、石夕腐 膜、有機ARC層及光阻劑層來形成。 參看圖2G使用複合硬遮罩圖案m及交又遮罩圖案⑷ 作為姓刻遮罩，緩衝絕緣層之殘餘部分⑽及第一層間絕 緣層120可各向異性地乾式钱刻以形成上接觸孔152。在說 129500.doc •16· 200901370 明實施例中，上接觸孔152由向下部分#刻穿過第一層間 絕緣層12〇、在上接觸孔152之底部與第—餘刻終止絕緣層 112之《下分離厚度Dl來形成。在本發明之某些實施二 中，在上接觸孔152下自第一層間絕緣層12〇保留之分離厚 度Di在其厚度方面將對應於隨後形成之配線層之所需厚 度。 參看圖2H’移除交又遮罩圖案】4〇。 參看圖21，使㈣合硬料㈣130作為㈣遮罩，緩 衝絕緣層之曝殘餘部分136b及第一層間絕緣層12〇之下伏 部分經另外触刻以形成複數個與複合硬遮罩圖案⑽平行 延伸之線形渠溝158。線形渠溝158中之每一者與上接觸孔 152中之-對應者連接。在形成線形渠溝158期間，靠近每 -線形渠溝爾上接觸孔152之連接點的第一層間絕緣層 120之上隅角”A"㈣刻以具有圓形輪廊。因此，第一層間 絕緣層之㈣殘餘部分咖包㈣㈣狀部分” A”。在說 明實施例中，第一層間絕緣層之餘刻殘餘部分120c與第一 層間絕緣層之未蝕刻部分12〇b交錯。 f形成複數個線形渠溝158時，透過上接觸孔152曝之第 ^間絕緣層120之殘餘分離厚度叫皮完全㈣消除，以 于上接觸孔152曝第-_終止絕緣層112。 在說明實施例中，你猎筮 便侍第—層間絕緣層120之上表面中 Z形渠溝158之成型深度D2等於第一層間絕緣層12〇之殘 施刀離厚度Dl。然而，本發明不限於含有此特定特徵之實 施例’且線形渠溝158之成型深度h可大於或小於第一層 129500.doc 200901370 間絕緣層120之殘餘分離厚度Di。 參看圖2】，移除複合硬遮軍圖案13〇。此舉可藉由應用 習知濕式蚀刻製程來實現。 參看圖2K’使用第一層間絕緣層之未蝕刻部分碰及緩 衝、巴緣層之殘餘^们36b作為蚀刻遮罩，將由接觸孔 曝之第-蝕刻終止絕緣層112之部分各向異性地乾式蝕刻 以曝半導體基板10之導電區域。舉例而言，在製造具有圖 1中所示之布置的半導體裝置期間，彳以如上所述之方式 透過接觸孔1 52a曝作用區域12。 因此如圖2K中所示，形成複數個接觸孔1523以透過第 一層間絕緣層120選擇性地曝半導體基板1〇之導電區域。 每一接觸孔152a之寬度（如在第一（或”y")方向（亦即與複合 硬遮罩圖案i 3 〇之側向延伸方向平行之方向)上量測)部分地 由第-層間絕緣層之每一蝕刻殘餘部分12〇。之圓形肩狀部 刀A之4何形態來界定，此係因為此特徵界定第一層間 絕緣層之蝕刻殘餘部分U〇c之蝕刻側壁之位置。因此，每 -接觸孔152々方向寬度將根據此特徵在半導體基板1〇 上之側壁位置而變化。此外，在說明實例巾，每—接觸孔 1 曰52a之寬度(如在與第一方向成直角之第二方向(或”均上 罝測）由第一層間絕緣層之相鄰未蝕刻部分12仳之間的分 離距離來界定。 參看圖2L，複數個接觸孔1 52&及對應複數個線形渠溝 m或多種導f #料填充以形成填充接觸孔仙之接 觸栓1 62及填充線形渠溝】58之配線層1 。在本發明之一 129500.doc -18- 200901370 實施例中，Α ϋ當地形成具有經界定厚度之配線層i68， 使用層間絕緣層120之上表面及/或緩衝絕緣層 < 殘餘部分 13訃作為蝕刻終止物將習知CMP或回蝕刻製程應用於導電 材料之上表面。 用以形成接觸栓162及配線層168之導電材料可包括諸如 W、Cu ' Τι或Ta之金屬、諸如WN、TiN及TaN之金屬氮化 物及/或摻雜多晶梦中之一或多者。 因為第一層間絕緣層之每一蝕刻殘餘部分12〇〇之每一圓 形肩狀部分”A”位於接觸孔1523及對應線形渠溝158之交界 處，所以每一接觸栓162之材料寬度將部分地由接觸栓Μ] 及配線層168在接觸區域164中一體式連接之處的圓形肩狀 部分’’A”之幾何形態來界定。因此，每一接觸栓162之上截 段在接觸區域164t變寬而超過其中截段或下截段幾何形 態。 圖2L之說明實施例將以一些其他細節來描述。每一接觸 栓具有由第一層間絕緣層之未蝕刻部分12〇b之間的分離距 離所界定之X方向寬度在操作實例中，此χ方向寬度等 於第一間距或W1之1/4。（參見圖2八及^)。接觸拴162之下 截段及中截段具有y方向寬度We。接觸區域164具有相對 於第一層間絕緣層之每一蝕刻殘餘部分12〇c之圓形肩狀部 分"A"之幾何形態變化之y方向寬度貿^。每一配線層168之 寬度WB近似等於接觸栓162在X方向上之Wx。 另外注意，接觸區域164具有特徵為不存在連接接觸拴 162與對應配線層168之急轉點的橫截面。接觸拴162與配 129500. doc . 1〇 200901370 線層168之間的此增寬及圓形接觸表面提供改良之電特 性。 在前述實施例中之接觸栓162與配線層168組合以形成圖 1之直接接觸20及位元線3〇。亦即，直接接觸2〇及位元線 30在具有以上所示之特性的接觸區域164中連接。因此， 直接接觸2G與位元線3G之間的接觸電阻減小且總電效能得 以改良。 圖3A及3B為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖。圖3八及38說明與圖i中所示 之布置一致之直接接觸與位元線之另一一體成型。圖3八及 3B對應於圖1之區域”b”。 所說明之製造半導體裝置之方法非常類似於先前參照圖 2A至2L所描述之方法。然而，在圖3八及36之實施例中， 當移除第一蝕刻終止絕緣層】〗2之部分以便曝半導體基板 10之導電區域時，允許複合遮罩圖案13〇保留在第一層間 絕緣層120上。在圖3A及3B中，與圖2A至2L共有之參考數 字表示等效元件。因此，將不重複關於相同部件之詳細描 述。 參看圖3 A，在形成曝第一蝕刻終止絕緣層丨丨2之所選擇 4为的接觸孔1 52a之後及在形成分別連接接觸孔丨52之線 形渠溝158之後，將複合遮罩圖案13〇、第一層間絕緣層 1 20及緩衝絕緣層之殘餘部分丨36b用作蝕刻遮罩以移除第 一蝕刻終止絕緣層112之曝部分。因此，半導體基板1〇之 導電區域（未圖示）由接觸孔152a曝。 129500.doc •20- 200901370 參看圖3B，隨後將導電材料沈積於複合遮罩圖案ι3〇上 及層間絕緣層120上以形成填充接觸孔152a及線形渠溝ι58 之導電層1 60。導電材料之詳細描述與參照圖几所描述相 同。 隨後’可使用習知CMP或回蝕刻製程來移除導電層ι6〇 之一部分及複合遮罩圖案130直至曝層間絕緣層12〇之上表 面及/或緩衝絕緣層1 3 6之殘餘部分。 圖4A至4E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖。如同上述，圖4A至4E說明 與圖1之布置一致之直接接觸與相關位元線之一體成型。 圖4A及4B對應於圖1之區域A’且圖4C至4E對應於圖1之區 域B。 圖4A至4E中說明之製造半導體裝置之方法與相對於圖 2 A至2 L描述之製造方法類似。然而，在當前實施例中， 當形成線形渠溝1 58時，第二蝕刻終止絕緣層！ 22係用作钱 刻終止層。在圖4A及4E中，與圖2A至2L共有之參考數字 表示等效元件。因此，將不重複相同部件之詳細描述。 參看圖4 A，第一蝕刻終止絕緣層Π 2、第一層間絕緣層 120、第二蝕刻終止絕緣層122及第二層間絕緣層ι24依序 形成於半導體基板10上。 第一触刻終止絕緣層112充當在蝕刻第一層間絕緣層12〇 時之钮刻終止層，且第二蝕刻終止絕緣層122充當在姓刻 第二層間絕緣層124時之蝕刻終止層。第一蝕刻終止絕緣 層112及第二蝕刻終止絕緣層122可分別由提供相對於第一 129500.doc 21 200901370 層間絕緣層12 〇及笛_ 、 第一層間絕緣層124之蝕刻選擇性的材 沮成根據形成第-層間絕緣層120及第二層間絕缘層 之組份材料1 第—银刻終止絕緣層i丨2及第二蝕刻終止絕 緣層12 2可由（例如η 化石夕膜形成。ΓΓ、氧化錢、氮氧切膜或碳 第—餘刻終止絕緣層i i 2及第二蝕刻終止絕 緣層122可由相回从+丨 、 ★ 才料或不同材料組成。在—實施例中， 將第㈣終止絕緣層i 12及第二㈣終止絕緣層1 形成至約500 A之厚度。 合目 形成第一層間絕緣層120及第二層間絕緣層124之材料可 與參照圖2A之第一層間絕緣層12〇所描述之材料相同 一層間絕緣層120及第-声間 此不同之材料組成。緣層4可由相同材料或彼 與相對於圖2A所給出之描述__致，複數個第—遮罩圖案 134形成於第二層間絕緣層124上。 ” 參看圖4B ’根據如參照圖2B至2E所描述之方法 衝絕緣層136及複數個第：遮罩圖案⑽形成於第—遮罩 圖案134上。目此’複合遮罩圖案13〇可 U4及第二遮罩圖案咖形成。 遮罩圖案 參看圖4C，根據如參照圖脚斤描述之方法將且八 :曝緩衝絕緣層136之殘餘部分之上表面及複合硬遮；： 案uo之開口 的交又遮罩圖案14〇形成於所得結構上。 其後，使用複合硬遮罩圖案13〇及交又遮罩圖案14〇作為 =遮罩，可使用各向異性製程來依序乾式_緩衝絕緣 之殘餘部分⑽、第二層間絕緣層124、第二蝕刻終止 129500.doc -22· 200901370 絕緣層122及第一層間絕緣層12〇。以壯士 j 匕方式’可形成上接 觸孔152。此時，如參照圖2G所描述，μ社& 上接觸孔152僅部分 地穿過第一層間絕緣層120之總厚度而形 J〜成，在第一層間 絕緣層12〇中留下保留在第一蝕刻終止絕緣層ιΐ2上之預定 分離厚度D!。 ^ 參看圖4D，在根據如參照圖21所描述之方法來移除交又 遮罩圖案14〇之後’使用複合硬遮罩圖案nG作為姓刻遮罩 來蚀刻緩衝絕緣層之殘餘部分⑽及第二層間絕緣層HA 之下伏部分中之所選擇者以形成複數個與複合硬遮罩圖案 "0平行延伸之線形渠溝158。然而，在說明實施例中，在 形成線形渠溝職間’第二姑刻終止絕緣層122係用作餘 刻第二層間絕緣層124時之蝕刻終止層。 每-線形渠溝15 8分別在接觸區域中與上接觸孔i 5 2連 接。如前所述，在形成線形渠溝158期間，將第一層間絕 緣層12G之殘餘分離厚叫移除以選擇性地曝第—餘刻終 止絕緣層112之部分。 X '" 參看圖4E，如參照圖2JM或圖3A及3B所描述，移除 第一姓刻終止絕緣層112之曝部分，，將接觸孔152a 及線形渠溝1 5 8以一或多種導f 裡导電材枓填充，從而使接觸栓 162及配線層168 —體成型。 當第一敍刻終止絕绫js 1】，a & S緣層112及第二蝕刻終止絕緣層122由 具有類似蝕刻特性之相同材料形成時，在移除由接觸孔 1 52a曝之第一敍刻終止絕 層112的同時，亦移除由線形 木溝158曝之第二蝕刻終止絕緣層122之部分。因此，可由 129500.doc •23- 200901370 線形渠溝158曝第一層間絕緣層之蝕刻部分^…^此時， 如圖4Ε中所說明’配線層168之底表面直接接觸第一層間 絕緣層之#刻#分12Ge之上表面。然@，本發明不限於此 特定特徵。儘管未說明，但第H終止絕緣層122可在 線形渠溝158的底部而保留在第一層間絕緣層12〇上。在此 情況下m终止絕緣層122插人第—層間絕緣層12〇 與配線層168之間。The sand is divided such that the reduced surface portion 120a is formed in the upper surface of the first interlayer insulating layer 12A. In the illustrated embodiment, the first thickness "d" has a vertical depth equal to the first width of the first mask pattern 134. A conventional dry etching process can be used to form the reduced surface portion 12?3 in the upper surface of the first interlayer insulating layer 12?. For example, the process for forming the first mask pattern m may include excessively engraving the first interlayer insulating layer 12A to form a reduced surface portion gamma. Alternatively, the 'dry' engraving process can be applied to the upper surface of the first interlayer 12 独立 through the first-mask pattern U4 independently to form the reduced surface portion 120a. However, reducing the formation of surface portions 120& is not essential to certain embodiments of the present invention and may be omitted. Referring to Fig. 2C, a buffer insulating layer 136 is formed on the side wall of the first mask pattern 134 to form a groove region 136a having a predetermined width between adjacent ones of the first mask patterns 134. Therefore, the buffer insulating layer 136 may be formed to cover the upper surface and the side wall surface of the first mask pattern 134 and the lower surface portion 12a of the first interlayer insulating layer 120. In the illustrated example, the buffer insulating layer 136 is formed to a thickness equal to the first thickness "d". In this particular embodiment 129500.doc -13. 200901370, the thickness of the buffer insulating layer Π6 defines a recessed region 136a having a second width W2 equal to the first width shame. The buffer insulating layer i 3 6 may have - or a plurality of insulating layers with the first layer! 2 材料 A material having the same or similar etching characteristics as the etching characteristics. By way of example, in one particular embodiment, the buffer insulating layer 136 is formed of the same material as the first interlayer insulating layer 120. The buffer insulating layer 136 may be, for example, an oxide film, and may be formed, for example, using a conventional atomic layer deposition (ALD) process. Referring to FIG. 2D, a second mask layer 138 is formed on the buffer insulating layer 136. The second mask layer 138 may be formed of one or more materials having etching characteristics that are the same as or similar to those of the first mask pattern 134. For example, the second mask layer 138 can be formed from one or more materials such as oxides, nitrides, polysilicones, and/or metals. For example, the second mask layer 138 may be formed of a polysilicon film when the first interlayer insulating layer 120 and the buffer insulating layer 136 are formed of an oxide layer or a nitride film. If the first interlayer insulating layer 12 and the buffer insulating layer 136 are each formed of an oxide film, the second mask layer 138 may be formed of a polycrystalline layer or a nitride film. After the second mask layer 138 is formed, the recessed regions 136a are filled with a material that forms the second mask layer 138. If the thickness of the buffer insulating layer 136 is 1/4 of the thickness of the first pitch 21>, the width of the trowel of the second mask layer 138 filling the recessed region 136a will be the second width W2 (for example, In the example, '1/4 of the first pitch 2P, or the first width W1). Referring to FIG. 2E, the second mask layer 138 and the upper lateral extension of the buffer insulating layer 136 are removed to expose the upper surface of the first mask pattern 134. In this manner, a second plurality of mask patterns 138a may be formed in the recessed regions 136a. The first plurality of mask patterns 138& The flat lamp parent staggered pattern is formed on the first interlayer insulating layer 120 in the first direction, and the resultant combination of the first mask pattern 134 and the second mask pattern 丨38a is combined with the composite hard mask pattern 13G. . The composite hard pattern 13G can now be used as an etched J mask during the dry etching process that is used for the inter-layer insulating layer 120. It is particularly noteworthy that the composite hard mask pattern 13 has a line pattern 〇 其 which is now repeated with a pattern width equal to the first width W1 separated by a similar width equal to 1 第一 of the first pitch. Therefore, the hard mask pattern U 〇 can be formed equal to the final pitch p of 1/2 of the first pitch 2P, where ^ y p can represent the finest pitch which can be obtained by the resolution limit of the photolithographic apparatus used. In the course of the description, a conventional chemical mechanical polishing (CMP) process can be used to remove the second mask layer 138 and the upper side of the buffer insulation layer. Alternatively, the second visor layer 138 and the C 胄 laterally extending portion above the buffer insulating layer 136 can be independently removed by applying a separate conventional (four) process to form the resulting structure illustrated in Figure 2E. For example, the wet timing process of each of the timings can be used independently to remove the laterally extending portions of the second mask layer US and the buffer layer I36. Referring to the <2F'''''''''''''''''' The linear opening 140a formed in the intersecting mask pattern 14A extends in a second direction orthogonal to the composite hard mask pattern 13''. The position and width of the linear opening 140a define the direct geometry of the contact 20 as shown in Fig. = 129500.doc -15· 200901370. In the illustrated example, the openings 14 & have a simple linear shape, but embodiments of the invention are not limited thereto and direct contacts 20 having more complex lateral geometries may be formed. Similarly, the cross-mask pattern M0 does not have to be orthogonal to the composite hard mask pattern 130, but may have, for example, 5° to 90°. Geometric orientation within the range. Alternatively, the 'linear (or linear) cross-mask pattern 144 may be replaced by a cross-mask pattern 140 formed by a plurality of island-shaped openings. Such a cross-mask pattern i 4 〇 may be particularly useful when the final arrangement of direct contact is substantially non-linear (or arbitrary). The resulting overlying arrangement between the composite hard mask pattern 130 and the crossed mask pattern 14A selectively exposes the upper surface of the residual portion 1366 of the buffering insulating layer. The exposed portions of the residual portion 136b of the buffer insulating layer correspond to the desired positions of the direct contact holes 2''. That is, the exposed residual portion 13 of the buffer insulating layer is vertically etched to form a contact hole through the first interlayer insulating layer i2. In an embodiment, the parent-cross mask pattern 140 is formed of a photoresist film, but may alternatively or additionally be formed of a plurality of films applied or stacked separately, including a polysilicon film, a nitride film, an amorphous carbon layer (ACL) ), a capping layer (such as SiON, TEOS) and an ALD oxide, an anti-reflective coating (ARC) film, and the like. For example, s, the mask pattern 14 can be sequentially stacked with a spin-on carbon (s〇c) film, a 矽ARC layer and a photoresist layer, or sequentially stacked s〇c film, Shixi ruth film, organic The ARC layer and the photoresist layer are formed. Referring to FIG. 2G, a composite hard mask pattern m and a cross-mask pattern (4) are used as the surname mask, and the residual portion (10) of the buffer insulating layer and the first interlayer insulating layer 120 can be anisotropically dry-formed to form an upper contact. Hole 152. In the embodiment of 129500.doc •16·200901370, the upper contact hole 152 is etched through the first interlayer insulating layer 12 from the lower portion #, and the insulating layer is terminated at the bottom of the upper contact hole 152 and the first remaining portion. 112" is formed by separating the thickness D1. In some implementations 2 of the present invention, the separation thickness Di retained from the first interlayer insulating layer 12 under the upper contact hole 152 will correspond in thickness to the desired thickness of the subsequently formed wiring layer. Referring to Figure 2H', the cross-mask pattern is removed. Referring to FIG. 21, the (four) hard material (four) 130 is used as a (four) mask, the exposed portion 136b of the buffer insulating layer and the underlying portion of the first interlayer insulating layer 12 are additionally etched to form a plurality of composite hard mask patterns. (10) Linear grooves 158 extending in parallel. Each of the linear grooves 158 is connected to a corresponding one of the upper contact holes 152. During the formation of the linear trench 158, the first interlayer insulating layer 120 near the connection point of the upper contact hole 152 of each of the linear trenches has an upper corner "A" (4) engraved to have a circular corridor. Therefore, the first (4) Residual portion of the interlayer insulating layer (4) (four)-shaped portion "A". In the illustrated embodiment, the residual portion 120c of the first interlayer insulating layer is interleaved with the unetched portion 12〇b of the first interlayer insulating layer. When f is formed into a plurality of linear trenches 158, the residual separation thickness of the second insulating layer 120 exposed through the upper contact holes 152 is completely eliminated (4), so that the upper contact holes 152 expose the -th termination insulating layer 112. In the illustrated embodiment, the forming depth D2 of the Z-shaped groove 158 in the upper surface of the shovel-interlayer insulating layer 120 is equal to the residual sizing thickness D1 of the first interlayer insulating layer 12 。. However, the present invention Not limited to the embodiment containing this particular feature' and the forming depth h of the linear trench 158 may be greater or less than the residual separation thickness Di of the insulating layer 120 between the first layer 129500.doc 200901370. Referring to Figure 2], the composite hard mask is removed. Army pattern 13 〇. This can be done by applying the wet The etching process is implemented. Referring to FIG. 2K', the unetched portion of the first interlayer insulating layer is used to touch the buffer, and the residual layer 36b is used as an etch mask, and the first etching-exposed insulating layer 112 is exposed by the contact hole. Partially anisotropic dry etching to expose the conductive regions of the semiconductor substrate 10. For example, during fabrication of the semiconductor device having the arrangement shown in Figure 1, the germanium is exposed through the contact holes 152a in the manner described above. 12. Thus, as shown in FIG. 2K, a plurality of contact holes 1523 are formed to selectively expose the conductive regions of the semiconductor substrate 1 through the first interlayer insulating layer 120. The width of each contact hole 152a (as in the first ( Or the "y") direction (i.e., measured in a direction parallel to the lateral extension direction of the composite hard mask pattern i 3 )) is partially etched by each of the etch residual portions 12 of the inter-layer insulating layer. The circular shoulder is defined by the shape of the knife A, because this feature defines the position of the etched sidewall of the etch residue U 〇 c of the first interlayer insulating layer. Therefore, the width in the direction of the contact hole 152 将 will vary depending on the position of the side wall on the semiconductor substrate 1 根据 according to this feature. In addition, in the description of the example towel, the width of each contact hole 1 曰 52a (such as in a second direction at a right angle to the first direction (or "on average") is determined by the adjacent unetched portion of the first interlayer insulating layer. Referring to FIG. 2L, a plurality of contact holes 1 52 & and corresponding plurality of linear trenches m or a plurality of conductive materials are filled to form contact plugs 1 62 and filled lines The wiring layer of the trenches 58. In one embodiment of the invention 129500.doc -18- 200901370, the wiring layer i68 having a defined thickness is locally formed, and the upper surface of the interlayer insulating layer 120 is used and/or buffered. Insulating Layer < Residual portion 13讣 is applied as an etch stop to a conventional CMP or etch back process applied to the upper surface of the conductive material. The conductive material used to form the contact plug 162 and the wiring layer 168 may include, for example, W, Cu ' Τ or One or more of a metal of Ta, a metal nitride such as WN, TiN, and TaN, and/or a doped polycrystal. Because each of the etching residues 12 of the first interlayer insulating layer has a circular shape The shoulder portion "A" is located at the contact hole 1523 and corresponding At the junction of the linear trenches 158, the material width of each contact plug 162 will be partially covered by the contact plugs and the circular shoulder portion 'A' where the wiring layer 168 is integrally joined in the contact region 164. The geometry is defined. Thus, the upper section of each contact pin 162 widens over the contact area 164t beyond the section or lower section geometry. The illustrated embodiment of Figure 2L will be described in some other detail. The contact plug has an X-direction width defined by a separation distance between the unetched portions 12〇b of the first interlayer insulating layer, which in the example of operation is equal to the first pitch or 1/4 of W1. 2 and ^). The lower and middle sections of the contact 拴162 have a y-direction width We. The contact area 164 has a circular shoulder shape with respect to each etched residual portion 12〇c of the first interlayer insulating layer. The width y of each of the wiring layers 168 is approximately equal to Wx of the contact plug 162 in the X direction. Note that the contact region 164 is characterized by the absence of a connection contact. 162 and the corresponding wiring layer 168 The cross section of the transition point. The contact 拴162 and the 129500.doc.1〇200901370 This widening and circular contact surface between the line layers 168 provides improved electrical characteristics. The contact plug 162 and the wiring layer in the foregoing embodiments. 168 are combined to form direct contact 20 and bit line 3A of Figure 1. That is, direct contact 2〇 and bit line 30 are connected in contact region 164 having the characteristics shown above. Therefore, direct contact with 2G and bit The contact resistance between the wires 3G is reduced and the total electrical efficiency is improved. 3A and 3B are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. Figures 3 and 38 illustrate another integral formation of direct contact and bit lines consistent with the arrangement shown in Figure i. Figures 3 and 3B correspond to the area "b" of Figure 1. The illustrated method of fabricating a semiconductor device is very similar to the method previously described with reference to Figures 2A through 2L. However, in the embodiment of FIGS. 3 and 36, when the portion of the first etch-stop insulating layer is removed to expose the conductive region of the semiconductor substrate 10, the composite mask pattern 13 is allowed to remain between the first layers. On the insulating layer 120. In Figs. 3A and 3B, reference numerals common to Figs. 2A to 2L denote equivalent elements. Therefore, a detailed description about the same components will not be repeated. Referring to FIG. 3A, the composite mask pattern 13 is formed after forming the selected contact hole 152a of the first etch stop insulating layer 丨丨2 and after forming the linear trenches 158 respectively connecting the contact holes 52. The first interlayer insulating layer 120 and the remaining portion 36b of the buffer insulating layer serve as an etch mask to remove the exposed portion of the first etch-stop insulating layer 112. Therefore, the conductive region (not shown) of the semiconductor substrate 1 is exposed by the contact hole 152a. 129500.doc • 20- 200901370 Referring to FIG. 3B, a conductive material is then deposited on the composite mask pattern ι3 and on the interlayer insulating layer 120 to form a conductive layer 160 that fills the contact hole 152a and the line trench ι58. The detailed description of the conductive material is the same as described with reference to the figures. A portion of the conductive layer ι6 及 and the composite mask pattern 130 may then be removed using conventional CMP or etch back processes until the surface of the interlayer insulating layer 12 and/or the residual portion of the buffer insulating layer 136 is removed. 4A through 4E are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. As described above, Figures 4A through 4E illustrate the direct contact and associated bit line formation in accordance with the arrangement of Figure 1. 4A and 4B correspond to the area A' of Fig. 1 and Figs. 4C to 4E correspond to the area B of Fig. 1. The method of fabricating a semiconductor device illustrated in Figures 4A through 4E is similar to the method of fabrication described with respect to Figures 2A through 2L. However, in the current embodiment, when the linear trenches 1 58 are formed, the second etch terminates the insulating layer! The 22 series is used as a money stop layer. In Figs. 4A and 4E, reference numerals common to Figs. 2A to 2L denote equivalent elements. Therefore, a detailed description of the same components will not be repeated. Referring to FIG. 4A, a first etch-stop insulating layer Π2, a first interlayer insulating layer 120, a second etch-stop insulating layer 122, and a second interlayer insulating layer ι24 are sequentially formed on the semiconductor substrate 10. The first etch stop insulating layer 112 serves as a button stop layer when the first interlayer insulating layer 12 is etched, and the second etch stop insulating layer 122 serves as an etch stop layer when the second interlayer insulating layer 124 is last. The first etch stop insulating layer 112 and the second etch stop insulating layer 122 may be respectively provided by an etch selectivity that provides an interlayer insulating layer 12 and a first interlayer insulating layer 124 with respect to the first layer 129500.doc 21 200901370 The first silver-cut termination insulating layer i丨2 and the second etch-stop insulating layer 12 2 may be formed of (for example, η fossil film) according to the constituent material 1 forming the first interlayer insulating layer 120 and the second interlayer insulating layer. The oxidized money, the oxynitride film or the carbon first-end insulating layer ii 2 and the second etch-stop insulating layer 122 may be composed of a phase return from +丨, ★ materials or different materials. In the embodiment, the first (4) Terminating the insulating layer i 12 and the second (four) terminating insulating layer 1 to a thickness of about 500 A. The material for forming the first interlayer insulating layer 120 and the second interlayer insulating layer 124 may be the same as that of the first layer of FIG. 2A. The material described in the interlayer insulating layer 12 is composed of the same interlayer insulating layer 120 and the different materials between the first and the first sounds. The edge layer 4 may be made of the same material or a description given with respect to FIG. 2A. The first mask pattern 134 is formed between the second layers The edge layer 124 is formed on the first mask pattern 134 according to the method as described with reference to Figures 2B to 2E. The composite mask layer 136 and the plurality of mask patterns (10) are formed on the first mask pattern 134. The pattern 13 can be formed by U4 and the second mask pattern. The mask pattern is shown in FIG. 4C, according to the method as described with reference to the figure, and the upper surface of the residual portion of the buffer insulating layer 136 and the composite hard mask are exposed; : The opening and mask pattern 14〇 of the opening of the case uo is formed on the obtained structure. Thereafter, the composite hard mask pattern 13〇 and the overlap mask pattern 14〇 are used as the mask, and an anisotropic process can be used. The dry portion _ buffer insulation residual portion (10), the second interlayer insulating layer 124, the second etch stop 129500.doc -22· 200901370, the insulating layer 122 and the first interlayer insulating layer 12 〇 can be formed in a strong manner The upper contact hole 152. At this time, as described with reference to FIG. 2G, the upper contact hole 152 is only partially passed through the total thickness of the first interlayer insulating layer 120, and is formed in the first layer. The layer 12 is left in the first etch stop insulating layer ι 2 The separation thickness D is predetermined. ^ Referring to FIG. 4D, after the cross-mask pattern 14 is removed according to the method as described with reference to FIG. 21, the composite insulating mask pattern nG is used as a surname mask to etch the buffer insulating layer. The remaining portion (10) and the selected one of the lower interlayer portions of the second interlayer insulating layer HA form a plurality of linear trenches 158 extending in parallel with the composite hard mask pattern "0. However, in the illustrated embodiment, Forming a linear trench trench' second etching termination insulating layer 122 serves as an etch stop layer when the second interlayer insulating layer 124 is left. Each of the linear grooves 15 8 is connected to the upper contact hole i 5 2 in the contact area, respectively. As previously discussed, during the formation of the linear trench 158, the residual separation thickness of the first interlayer insulating layer 12G is removed to selectively expose the portion of the first insulating insulating layer 112. X '" Referring to FIG. 4E, as described with reference to FIG. 2JM or FIGS. 3A and 3B, the exposed portion of the first-lasting end insulating layer 112 is removed, and the contact hole 152a and the linear trench 158 are one or more. The conductive material 枓 is filled in the guide f, so that the contact plug 162 and the wiring layer 168 are integrally formed. When the first singulation termination js 1], the a & S edge layer 112 and the second etch stop insulating layer 122 are formed of the same material having similar etching characteristics, the first exposure exposed by the contact hole 1 52a is removed. While the termination layer 112 is being etched, portions of the second etch stop insulating layer 122 exposed by the linear trenches 158 are also removed. Therefore, the etched portion of the first interlayer insulating layer can be exposed by the 129500.doc •23-200901370 linear trench 158. At this time, as illustrated in FIG. 4A, the bottom surface of the wiring layer 168 directly contacts the first interlayer insulating layer. Layer #刻# points the surface of 12Ge. However, the invention is not limited to this particular feature. Although not illustrated, the Hth termination insulating layer 122 may remain on the first interlayer insulating layer 12A at the bottom of the linear trench 158. In this case, the m termination insulating layer 122 is interposed between the first interlayer insulating layer 12A and the wiring layer 168.
圖5A至5E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖。圖从至5£又說明直接接觸 與相關位元線之一體成型。圖5A及5B對應於圖！之區域 A。圖5C至5E對應於圖}之區域B。 斤說月之製半導體裝置之方法大致類似於參照圖2 a至 2L所描述之方法。在前者實施财，首先形成上接觸孔 152，且卩通後形成線形渠溝158。然而，在圖从至π中所 說月之η把例中，首先形成線形渠溝i %，且隨後形成接 觸孔1523。在圖从及汀中，與圖2A至2L共有之參考數字 表不等效7L件。g)此，將不重複相同部件之詳細描述。 參看圖5A，根據如參照圖2A至2E所描述之方法，將第 韻刻終止絕緣層112及第一層間絕緣層】2〇形成於半導體 基板ίο上。然後，複合硬遮罩圖案13〇可由帛一遮罩圖案 134及第二遮罩圖案138a形成。 其後’使用複合硬料圖案13G作為#刻料，緩衝絕 緣層136及第—層間絕緣層12G經選擇性地㈣以形成複數 個與複合硬遮軍圖案130平行延伸之線形渠溝558。 129500.doc -24- 200901370 看圖5B’形成具有部分地曝複合硬遮罩圖案之上 及線形渠溝558之底表面之開口 54(^的交叉遮罩圖案 540 〇 形成父又遮罩圖案54〇之材料可與參照圖2F所描述之形 成交又遮罩圖案140之材料相同。 ^看圖5C，使用複合硬遮罩圖案13〇及交又遮罩圖案54〇 作為敍刻遮罩’將第—钮刻終止絕緣層112用作姓刻終止 層以蝕刻第—層間絕緣層12〇,藉此形成接觸孔552。第一 蝕刻終止絕緣層112部分地透過接觸孔552而曝。 參看圖5D，移除透過接觸孔552而曝之第一蝕刻終止絕 緣層112之部分，且獨立地移除交叉遮罩圖案54〇及複合硬 遮罩圖案130。因此，徹底曝接觸孔552及線形渠溝558之 内表面。 另外，移除第一蝕刻終止絕緣層i丨2及交叉遮罩圖案54〇 以及複合硬遮罩圖案130之順序並不固定且可為處理方便 起見而顛換。 參看圖5E ’根據如參照圖2L所描述之方法，將接觸孔 552及線形渠溝558以一或多種導電材料填充，從而使接觸 栓162及配線層168—體成型。 圖6 A至6E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖。圖6A至6E又說明直接接觸 與相關位元線之一體成型。圖6 a及6B對應於圖1之區域 A。圖6C至6E對應於圖1之區域b。 圖6A至6E中說明之製造半導體裝置之方法與參照圖5a 129500.doc -25· 200901370 至5E所描述之方法大體上類似。在說明實施例中，第二姓 刻終止絕緣層〗則作形成線形渠溝⑸時之㈣終止層 (參看圖5A)。在圖从至紐中，與圖w2l、圖从請及 圖5八請共有之參考數字表示等效元件。因此將不重 複相同部件之詳細描述。5A through 5E are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. The figure from 5 to £ shows the direct contact and the formation of a related bit line. Figures 5A and 5B correspond to the figure! Area A. 5C to 5E correspond to the area B of Fig.}. The method of describing a semiconductor device of the month is substantially similar to the method described with reference to Figures 2a to 2L. In the former, the upper contact hole 152 is formed first, and the linear groove 158 is formed after the pass. However, in the example of the η of the month from the π, the linear trench i % is first formed, and then the contact hole 1523 is formed. In the figures and the figures, the reference numerals shared with Figs. 2A to 2L are not equivalent to 7L pieces. g) This will not repeat the detailed description of the same components. Referring to Fig. 5A, the first end insulating layer 112 and the first interlayer insulating layer are formed on the semiconductor substrate ίο according to the method as described with reference to Figs. 2A to 2E. Then, the composite hard mask pattern 13 can be formed by the first mask pattern 134 and the second mask pattern 138a. Thereafter, the composite hard material pattern 13G is used as the #刻刻, and the buffer insulating layer 136 and the first interlayer insulating layer 12G are selectively (4) to form a plurality of linear grooves 558 extending in parallel with the composite hard occlusion pattern 130. 129500.doc -24- 200901370 Figure 5B' is formed with an opening 54 having a partially exposed composite hard mask pattern and a bottom surface of the linear trench 558 (the cross mask pattern 540 ^ forms a parent and mask pattern 54 The material of the crucible may be the same as the material of the mask pattern 140 formed as described with reference to FIG. 2F. ^ See FIG. 5C, using a composite hard mask pattern 13 and a matte mask pattern 54 as a masking mask' The first-tap termination insulating layer 112 serves as a surname termination layer to etch the first interlayer insulating layer 12, thereby forming a contact hole 552. The first etch-stop insulating layer 112 is partially exposed through the contact hole 552. See FIG. 5D. The portion of the first etch-stop insulating layer 112 exposed through the contact hole 552 is removed, and the cross-mask pattern 54 and the composite hard mask pattern 130 are independently removed. Therefore, the contact hole 552 and the linear trench are completely exposed. In addition, the order of removing the first etch-stop insulating layer i 丨 2 and the cross-mask pattern 54 〇 and the composite hard mask pattern 130 is not fixed and can be reversed for convenience of processing. 5E 'based on the side as described with reference to Figure 2L The contact hole 552 and the linear trench 558 are filled with one or more conductive materials to form the contact plug 162 and the wiring layer 168. FIGS. 6A to 6E illustrate the fabrication of a semiconductor device according to another embodiment of the present invention. A cross-sectional perspective view of the method. Figures 6A through 6E illustrate the direct contact and associated bit line formation. Figures 6a and 6B correspond to area A of Figure 1. Figures 6C through 6E correspond to area b of Figure 1. The method of fabricating a semiconductor device illustrated in 6A to 6E is substantially similar to the method described with reference to Figures 5a 129500.doc - 25. 200901370 to 5E. In the illustrated embodiment, the second surname terminates the insulating layer to form a line shape. In the case of the trench (5), the (4) termination layer (see Fig. 5A). In the figure from the map to the map, the reference numerals common to the figure w2l, the figure and the figure 5 represent the equivalent components. Therefore, the details of the same components will not be repeated. description.
參看圖6A，根據如參照圖从及仙所描述之方法，將第 -蝕刻終止絕緣層112、第一層間絕緣層12〇、第终 止絕緣層122及第二層間絕緣層124依序形成於半導體基板 1〇上。然後，將複數個第一遮罩圖案134及緩衝絕緣層136 形成於所得結構上。使用此等膜，將複數個第二遮罩圖案 13㈣成於緩衝絕緣層136上以形成包括第—遮罩圖案134 及第二遮罩圖案138a之複合硬遮罩圖案13〇。 隨後，使用複合硬遮罩圖案13〇作為蝕刻遮罩及第二蝕 刻終止絕緣層m作為㈣終止層，㈣緩衝絕緣層之殘 餘部分136b及第二層間絕緣層124以形成複數個與複合硬 遮罩圖案130平行延伸之線形渠溝558。 參看圖6B，根據如參照圖5B所描述之方法，形成具有 部分地曝複合硬遮罩圖案130及線形渠溝558之底表面I開 口 540a的交叉遮罩圖案54〇。 參看圖6C，使用複合硬遮罩圖案13〇及交叉遮罩圖案“^ 作為蝕刻遮罩，蝕刻緩衝絕緣層之殘餘部分13讣、第二層 間絕緣層120及第二蝕刻終止絕緣層122。隨後，使用複合 硬遮罩圖案130及交又遮罩圖案54〇作為蝕刻遮罩，將第I 蝕刻終止絕緣層U2用作蝕刻終止層以蝕刻第一層間絕緣 129500.doc -26- 200901370 層120，藉此形成接觸孔552。第一蝕刻終止絕緣層ιΐ2部 分地透過接觸孔552而曝。 參看圖5D，獨立地執行移除透過接觸孔552而曝之第一 蝕刻終止絕緣層112之所選擇部分，及隨後移除交又遮罩 圖案540及複合硬遮罩圖案13〇。因此，完全地曝接觸孔 5 52及線形渠溝55 8之内表面。 另外，如參照圖4E所描述，若第一蝕刻終止絕緣層112 及第二蝕刻終止絕緣層122由相同材料或具有類似蝕刻特 性之材料組成，則當由接觸孔552曝之第一蝕刻終止絕緣 層112在曝第二蝕刻終止絕緣層122之狀態下移除時，在移 除由接觸孔5 5 2曝之第一蝕刻終止絕緣層！丨2的同時，亦完 全移除由線形渠溝558曝之第二蝕刻終止絕緣層122之部 分。因此，如圖6D中所說明，第一層間絕緣層12〇可由渠 溝5 5 8曝。 參看圖6E，根據如參照圖2L所描述之方法，將接觸孔 552及線形渠溝558以一或多種導電材料填充，從而形成在 接觸孔552及渠溝558内具有一體成型結構的接觸栓162及 配線層168。 如多”’、圖6D所描述，若在移除由接觸孔552曝之第一钱 刻終止絕緣層U2的同時完全移除由渠溝558曝之第二蝕刻 終止絕緣層122之部分’則如圖6E中所說明，配線層168之 底表面直接接觸第一層間絕緣層12〇之上表面。然而，本 發明不限於此特定特徵。雖然未說明，但在某些實施例 中第一蝕刻終止絕緣層122可在渠溝5 58的底表面處而保 129500.doc •27- 200901370 留在第一層間絕緣層120上。類似地，第二省虫刻終止絕緣 層122可插入第一層間絕緣層咖與配線層168之間。 根據本發明之各種實_之半㈣裝置包含複數個接觸 栓，其分別穿透複數個以細微間距形成之接觸孔以將複數 個配線層(例如位元線)與複數個安置於半導體基板上之導 電區域連接。複數個接觸栓中之每—者具有根據其自基板 之延伸距離而在第-方向上變化之寬度，i當其接近連接 :應配線層之接觸區域時增寬。本發明之某些實施例之此 態樣減少接觸栓與配線層之間的接觸電阻。但是，每一接 觸栓在不同於第一方向之第二方向上之寬度保持恆定且可 精確地界定。接觸栓之第二方向寬度可近似等於配線層之 寬度。複數個接觸栓及複數個配線層可在沈積—或多種導 電材料之單個步驟期間一體成型。因此，甚至當複數個接 觸孔及配線層以極細微間距緊密地成型時，每一接觸栓仍 將具有等於對應配線層且與其充分對準之寬度，而無錯位 偏差之風險。因此’可易於設計及製造高度整合半導體裝 置。 ，此外|根據本發明之實施例之在半導體裝置内形成細 微圖案之方法中’ ϋ由使用雙重圖案化，以潛在地超過可 用光微影設備之解析度極限之細微間距來形成的接觸圖案 可以極好之臨界尺寸均一性來形成。特定言之，為將具有 極、田微間距之複數個接觸栓及配線層—體成型，界定接觸 栓之接觸孔與界定配線層之線形渠溝可在明確界定之接觸 區域中有效地連接，且接觸孔及渠溝可同時以―或多種導 129500.doc -28· 200901370 電材料填充。因而，因為最終形成接觸孔 且货' 轉由使 用包括交叉遮罩圖案之雙重圖案化製程由以細微間 之硬遮罩圖案來確^，故以此方式，以有助於界定接觸 孔之布i，且接觸狀各別位置易於在半導體裝置之總體 设計内對準。因此，可確保有效蝕刻限度。此外，用於前 述實施例中之各種遮罩圖案之形狀及排列可自由地確定， 從而使得可獲得任何合理設計之接觸孔及配線層。Referring to FIG. 6A, the first etch stop insulating layer 112, the first interlayer insulating layer 12, the termination insulating layer 122, and the second interlayer insulating layer 124 are sequentially formed according to the method as described with reference to FIGS. The semiconductor substrate 1 is mounted on the substrate. Then, a plurality of first mask patterns 134 and a buffer insulating layer 136 are formed on the resultant structure. Using these films, a plurality of second mask patterns 13 (four) are formed on the buffer insulating layer 136 to form a composite hard mask pattern 13A including the first mask pattern 134 and the second mask pattern 138a. Subsequently, a composite hard mask pattern 13 is used as an etch mask and a second etch stop insulating layer m as a (four) termination layer, (iv) a residual portion 136b of the buffer insulating layer and a second interlayer insulating layer 124 to form a plurality of composite hard masks The cover pattern 130 extends in a linear groove 558 extending in parallel. Referring to Fig. 6B, a cross mask pattern 54 having a partially exposed composite hard mask pattern 130 and a bottom surface I opening 540a of the linear trench 558 is formed in accordance with the method as described with reference to Fig. 5B. Referring to FIG. 6C, the composite hard mask pattern 13 and the cross mask pattern "^" are used as an etch mask to etch the residual portion 13 of the buffer insulating layer, the second interlayer insulating layer 120, and the second etch stop insulating layer 122. Using the composite hard mask pattern 130 and the alternating mask pattern 54 as an etch mask, the first etch stop insulating layer U2 is used as an etch stop layer to etch the first interlayer insulating layer 129500.doc -26- 200901370 layer 120 Thereby, a contact hole 552 is formed. The first etch-stop insulating layer ι 2 is partially exposed through the contact hole 552. Referring to FIG. 5D, the selection of the first etch-stop insulating layer 112 exposed through the contact hole 552 is separately performed. And partially removing the mask pattern 540 and the composite hard mask pattern 13 . Therefore, the inner surfaces of the contact hole 5 52 and the linear groove 55 8 are completely exposed. Further, as described with reference to FIG. 4E, The first etch stop insulating layer 112 and the second etch stop insulating layer 122 are composed of the same material or a material having similar etching characteristics, and when the first etch is terminated by the contact hole 552, the insulating layer 112 is terminated by the second etching. When the layer 122 is removed, the second etch stop insulating layer 122 exposed by the linear trench 558 is also completely removed while removing the first etch stop insulating layer 丨2 exposed by the contact hole 552. Therefore, as illustrated in Fig. 6D, the first interlayer insulating layer 12 can be exposed by the trenches 548. Referring to Fig. 6E, the contact holes 552 and the linear trenches are formed according to the method as described with reference to Fig. 2L. 558 is filled with one or more conductive materials to form contact plugs 162 and wiring layers 168 having an integrally formed structure in contact holes 552 and trenches 558. As described in FIG. 6D, if removed by contact holes The first exposure of the 552 exposes the insulating layer U2 while completely removing the portion of the second etch-stop insulating layer 122 exposed by the trench 558. Then, as illustrated in FIG. 6E, the bottom surface of the wiring layer 168 is in direct contact with the first surface. The upper surface of the interlayer insulating layer 12 is. However, the invention is not limited to this particular feature. Although not illustrated, in some embodiments the first etch stop insulating layer 122 may remain on the first interlayer insulating layer 120 at the bottom surface of the trench 5 58 while maintaining 129500.doc • 27- 200901370. Similarly, the second insecticidal termination insulating layer 122 can be interposed between the first interlayer insulating layer and the wiring layer 168. The half (four) device according to the present invention comprises a plurality of contact plugs respectively penetrating a plurality of contact holes formed at fine pitches to place a plurality of wiring layers (eg, bit lines) and a plurality of layers on the semiconductor substrate The conductive areas are connected. Each of the plurality of contact plugs has a width that varies in the first direction according to the distance from the substrate, i is widened as it approaches the contact area of the wiring layer. This aspect of certain embodiments of the present invention reduces the contact resistance between the contact plug and the wiring layer. However, the width of each contact plug in a second direction different from the first direction remains constant and can be accurately defined. The width of the contact plug in the second direction can be approximately equal to the width of the wiring layer. A plurality of contact plugs and a plurality of wiring layers may be integrally formed during a single step of depositing - or a plurality of conductive materials. Therefore, even when a plurality of contact holes and wiring layers are closely formed at a very fine pitch, each contact plug will have a width equal to and sufficiently aligned with the corresponding wiring layer without risk of misalignment. Therefore, it is easy to design and manufacture highly integrated semiconductor devices. In addition, in the method of forming a fine pattern in a semiconductor device according to an embodiment of the present invention, a contact pattern formed by using double patterning to potentially exceed the fine pitch of the resolution limit of the available photolithographic apparatus may be used. Excellent critical dimension uniformity is formed. In particular, in order to form a plurality of contact plugs and wiring layers having a pole-to-field micro-pitch, the contact holes defining the contact plugs and the linear trenches defining the wiring layers can be effectively connected in the well-defined contact areas. The contact holes and the trenches can be filled with or with a plurality of conductive materials 129500.doc -28· 200901370. Thus, since the contact hole is finally formed and the double patterning process including the use of the cross mask pattern is performed by the hard mask pattern in the finest manner, in this way, the cloth which helps define the contact hole is used. i, and the respective locations of the contacts are easily aligned within the overall design of the semiconductor device. Therefore, an effective etching limit can be ensured. Further, the shapes and arrangements of the various mask patterns used in the foregoing embodiments can be freely determined, so that any properly designed contact holes and wiring layers can be obtained.
雖然本發明已參照其例示性實施例而特定展示及描述， 但一般熟習此項技術者應瞭解在不悖離如以下申請專利範 圍所界定之本發明之範疇的情況下可對其作出形式及細節 上之各種變化。 【圖式簡單說明】 圖1為說明根據本發明之一實施例之半導體裝置之例示 性配線布置的俯視圖； 圖2 A至2L為說明根據本發明之實施例之製造半導體裝 置之方法的剖面透視圖； 圖3 A及3B為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖； 圖4A至4E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖； 圖5 A至5 E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖；且 圖6A至6E為說明根據本發明之另一實施例之製造半導 體裝置之方法的剖面透視圖。 129500.doc -29· 200901370 【主要元件符號說明】 10 半導體基板 12 作用區域 20 直接接觸 30 位元線 112 第一蝕刻終止絕緣層 120 第一層間絕緣層 120a 降低表面部分While the present invention has been particularly shown and described with respect to the exemplary embodiments thereof, it will be understood by those skilled in the art that the invention may be practiced without departing from the scope of the invention as defined by the following claims. Various changes in details. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing an exemplary wiring arrangement of a semiconductor device in accordance with an embodiment of the present invention; FIGS. 2A to 2L are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. Figure 3A and 3B are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention; and Figures 4A through 4E are cross-sectional views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention; 5A to 5E are cross-sectional perspective views illustrating a method of fabricating a semiconductor device in accordance with another embodiment of the present invention; and FIGS. 6A to 6E are diagrams illustrating fabrication of a semiconductor device in accordance with another embodiment of the present invention. A cross-sectional perspective view of the method. 129500.doc -29· 200901370 [Description of main component symbols] 10 Semiconductor substrate 12 Active region 20 Direct contact 30-bit line 112 First etch-stop insulating layer 120 First interlayer insulating layer 120a Lower surface portion
120b 未蝕刻部分 120c #刻殘餘部分 122 第二蝕刻終止絕緣層 124 第二層間絕緣層 130 複合硬遮罩圖案 134 第一遮罩圖案 136 緩衝絕緣層 136a 凹槽區域 13 6b 殘餘部分 138 第二遮罩層 138a 第二遮罩圖案 140 交叉遮罩圖案 140a 開口 152 上接觸孔 152a 接觸孔 158 線形渠溝 129500.doc -30- 200901370 160 162 164 168 540 540a 552 558 導電層 接觸栓 接觸區域 配線層 交又遮罩圖案 開口 接觸iL 線形渠溝 129500.doc -31120b unetched portion 120c #刻 residual portion 122 second etch stop insulating layer 124 second interlayer insulating layer 130 composite hard mask pattern 134 first mask pattern 136 buffer insulating layer 136a recess region 13 6b residual portion 138 second mask Cover layer 138a Second mask pattern 140 Cross mask pattern 140a Opening 152 Upper contact hole 152a Contact hole 158 Linear trench 129500.doc -30- 200901370 160 162 164 168 540 540a 552 558 Conductive layer contact plug contact area wiring layer The mask pattern is in contact with the iL linear groove 129500.doc -31