1343632 > 第9608974號專利說明書修正本 修正日期·· 100年3月25日 " 九、發明說明： - 【發明所屬之技術領域】 \ 本發明係有關於一種半導體元件的製造方法，特別有 關於一種於内連線之間表面無矽化物殘留的半導體元件 的製造方法。 【先前技術】 半導體積體電路元件，例如動態隨機存取記憶體 (DRAM)在現今資訊電子業中佔不可或缺的地位，主要 由一個電晶體與一個電容器所構成。由於DRAM元件積 集度要求越來越高，記憶單元與電晶體的尺寸需要大幅縮 小，才可能製造出記憶容量更高，處理速度更快的DRAM。 於傳統半導體元件的製造過程中，需利用圖案化的硬 遮罩層，例如多晶石夕層，定義閘極接觸窗及位元線接觸構 槽。於閘極接觸窗及位元線接觸構槽形成之後，直接進型 内連線製作步驟。最後於平坦化金屬層的步驟中，一併移 除圖案化多晶矽層硬遮罩層。 第1A-1H圖係顯示傳統製作接觸窗及位元線接觸於 半導體元件上的各步驟的剖面示意圖。請參閱第1A圖， …一半導體基板10，例如單晶矽基板，其上具有複數個閘 極結構20a-20e。 接著，請參閱第1B圖，形成第一介電層25於半導體 ' 基板〗0上，並填入該複數個閘極結構之間，並施以平坦 化步驟於第一介電層25，使其與複數個閘極結構20a-20e 齊高。形成第二介電層30於第一介電層25上，並形成一 多晶矽層35於第二介電層30上。 1343632 修正曰期：100年3月25曰 4 第96128974號專利說明書修正本1343632 > Patent Specification No. 9608972 Revision of this revision date··March 25, 100" IX. Description of the Invention: - Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor element, particularly A method of manufacturing a semiconductor device in which no germanium remains on the surface between interconnects. [Prior Art] Semiconductor integrated circuit components, such as dynamic random access memory (DRAM), are indispensable in today's information electronics industry, and are mainly composed of a transistor and a capacitor. Due to the increasing demand for DRAM component accumulation, the size of memory cells and transistors needs to be greatly reduced, making it possible to manufacture DRAMs with higher memory capacity and faster processing speed. In the fabrication of conventional semiconductor components, a patterned hard mask layer, such as a polycrystalline layer, is used to define the gate contact window and the bit line contact trench. After the gate contact window and the bit line contact groove are formed, the direct connection interconnection step is made. Finally, in the step of planarizing the metal layer, the patterned polysilicon layer hard mask layer is removed together. The 1A-1H diagram shows a cross-sectional view of the steps of conventionally fabricated contact windows and bit lines in contact with semiconductor components. Referring to Fig. 1A, a semiconductor substrate 10, such as a single crystal germanium substrate, has a plurality of gate structures 20a-20e thereon. Next, referring to FIG. 1B, a first dielectric layer 25 is formed on the semiconductor 'substrate 0', and is filled between the plurality of gate structures, and a planarization step is applied to the first dielectric layer 25, so that It is aligned with a plurality of gate structures 20a-20e. A second dielectric layer 30 is formed on the first dielectric layer 25, and a polysilicon layer 35 is formed on the second dielectric layer 30. 1343632 Revision period: March 25, 100, 4 Revision of the patent specification No. 96128974
請參閱第1C圖，施以微影及钱刻步驟，將多晶石夕層 35圖案化成一遮罩層’並定義出複數個開口 對應基板 接觸開口（substrate _t⑽。pening) '位元線接觸開口⑽ hne contact line)及閘極接觸開口（邮噴⑽〇卿㈣。 接者’以圖案化遮罩層35為—硬遮罩並㈣該第一與第 一介電層25、30以形成複數個接觸窗4〇，如第 示。 曾接著，請參閱» 1E®，施以微影及钱刻製程定義一 ‘電溝槽45對應該也接觸涔g4 —茌蜩命40。依序沉積一阻障層50 =金屬導電層55於半導體基板上，如第ιρ圖所示。阻 户早層）〇的材質為丁i/TiN所椹成、沾、>•人陆 所構成的稷合層，順應性地形成 ^圖木化遮罩層〕5以及開n 4G之上 材質為金屬鎢。 ^ ^ 人千請參閱第1G圖’接著施以平坦化步驟6〇，移除第二 州電層30上的部分金屬導雷爲 ’’ ,鸯導電層5)、阻障層50及多晶矽 曰h，以形成—内連線結構，如第⑴圖所示。Referring to FIG. 1C, the lithography and engraving steps are performed to pattern the polycrystalline layer 35 into a mask layer' and define a plurality of openings corresponding to the substrate contact openings (substrate _t(10). pening) 'bit line contact Opening (10) hne contact line) and gate contact opening (mail spray (10) 〇 ( (4). The connector 'is patterned mask layer 35 as a hard mask and (d) the first and first dielectric layers 25, 30 to form A plurality of contact windows 4〇, as shown in the figure. Once then, please refer to » 1E®, applying lithography and money engraving process definitions. 'Electrical trenches 45 should also be in contact with 涔g4 — 茌蜩40. A barrier layer 50 = a metal conductive layer 55 on the semiconductor substrate, as shown in Fig. ιρ. The material of the early layer is 丁i/TiN, which is composed of ii/TiN, 沾, > The layer is formed to conformally form the metallized mask layer 5 and the material of the open n 4G is metal tungsten. ^ ^人千 Please refer to Figure 1G' and then apply the planarization step 6〇 to remove part of the metal-guided lightning on the second state electrical layer 30 as '', conductive layer 5), barrier layer 50 and polysilicon h, to form - the interconnect structure, as shown in Figure (1).
Ti/4:在/述習知半導體元件的製造過程中，複合層 TVTiN與多晶矽層35直接技 丁攸口 /w 55 Φ - 接觸，在形成金屬（鎢）導電層 如鈦化矽）。 s在"面處會形成矽化物（例 第2圖係顯示於第1 〇圖 > . 35 Α Λβ [〇 tj. 9 ,,, 设3層Ti/TiN與多晶石夕層 構二閱第2圖™所 高溫的作用石夕與鈦相互““的界面51位置，由於 與矽化鈦晶粒5〗b的混雜區姑〜形成未反應矽晶粒5] a 矽化鈦曰# μ μ %'、區或。由於未反應矽晶粒51a與 夕化鈦S曰拉训的性質截然不同，因此無法於單一平坦化 6 1343632 第9卿74號專利說明懿正本 修正日期：刚年3月训 (化學機械研磨，CMP)步驟6G中順利移除，導 :夕化=留，造成半導體元件的位元線之間的橋接，影響 其兀件效能及可靠度。 【發明内容】 避旁本發明提供一種半導體元件的製造方法’ 避免於夕曰曰石夕與阻障層形成石夕化物，造成後續平 的矽化物殘留，進而避免丰導娜 、一衣牙 接，改善其元件效能及可靠度元線之間的橋 括:供一種半導體元件的製造方法，包 岭體土板，其上具有複數的閘極紝構。形忐 -介電層於該半導體基板上。形成 ]冓形成 電層上。以該圖案化遽罩層為一硬遮該介 埴入哕接錨办士 犧牲層於该圖案化遮罩層上並 ”入該接觸ή中。依序移除部份 罩層，露出該介電層並牲廣及5亥圖案化遮 以微影及關製程定義二導t觸J二的該犧牲層齊高。施 二接觸固的犧牲層。依序沉積 ， 於該半導體基板上，以及施 曰及一金屬導電層 層上的部分該金屬導電層及化步驟，移除該介電 構。 ^曰及°亥阻障層以形成-内連線結 本發明實施例另提供一種丰遙歸_ 括提供一半導f# 肢兀件的製造方法，包 笔人币ΐ 板，其上具有複數個閘極结m 之間。施以-第-平坦化步驟於=開極結構 複數個_構齊高。形成-第二介二； 7 Γ343632 第戰974號專利說明書修正本 修正曰期：丨00年3月25日 j形成一圖案化遮罩層於該第二介電層上。以哕 ，罩層為—硬遮罩並關㈣—與第二介電層 接丈形成—犧牲層於該圖案化遮罩層上並埴入Ϊ ，觸命卜依序移除部份的該犧牲層及該圖案化遮罩二 路出_二介電層並與該接觸窗内的該犧牲層齊:曰 刻製程定義一導電溝槽對應該些接觸窗「並二 於該半導體基板上，以及施以—第二平;層 第二介電層上的部分該金屬導電層？:：遠 内連線結構。 ，早層以形成一 為使本發明之上述目的、特徵和優點能更明 文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 例說著圖式說明之範 似或相同之部分皆使用相;之圖號::逑：:相 是厚度可擴大’並以簡化或是方便標示。’再:例 ，式中各7L件之部分將以分職魏明之 未繪示或描述之元件，為所屬技術領域中。 另外’特定之實施例僅二= 々寸疋方式，其並非用以限定本發明。 及圖係顯示根據本發明實施例之製作接觸窗 於半導體元件上的各步驟的剖面示ΐ圖； 八圖，-半導體基板η〇，例如單晶矽、鍺、： 1343632 第96U8974號專利說明書修正本 修正日期：100年3月25日 錯、絕緣層上有邦01)基板，其上具有複數侧極結構 20a 120e。基板11 〇可分為主要元件陣列區域及週邊控 制區域。閘極結構120a-120c表示設置於主要元件陣列^ 域及閘極結構120e表示設置於週邊控制區域的元件。 接著，請參閱第3B圖，形成第一介電層125於半導 體基板11〇上，填入該複數個閘極結構12〇a_i2〇e之間， 並施以平坦化步驟，例如化學機械研磨（CMp)步驟，使 一 η電層125與複數個閘極結構12〇a_12〇e齊高。接著 形成第二介電層丨30於第一介電層】25上，並形 =層W於第二介電層13〇上。第一介電層125與第二二 電層130的材質為低介電常數〇〇w_k)材料層 物㈣鹽玻璃㈣或靖= I玻璃（BPSG)。第二介電層13Q的材質亦可為四 正矽酸鹽（tetra-ethyl-otho_silicate , TE〇s)。 土 施以微影及崎驟，將多㈣ 135圖案化成一遮罩層’並定義出複數 板接觸開口（substrate contari η ⑽對應基 rb：t ]jnp f C〇maCt叩啊)、位元線接觸開口 ( C Ct hne)及閘極接觸開口（gate t 邮。接著，以圖案化遮罩層13 : 該第一與第二介電屏125 nn、…勹更心罩亚蝕刻 如第3D圖所示。S 形成複數個接觸窗】4〇， =，請參閱第3E圖’形成一 基板】〗〇上並填入各接觸窗 圖案化遮罩部份的犧牲… 内的犧牲層齊高。依序^二”電層130並與接觸窗140 "门依序移除部份的犧牲層U2及圖案化遮 9 1343632 t白1Γ可藉由化學機械研磨（CMp)法，依序移除 。刀的犧牲層142及圖案化遮罩層135。或者，节 的犧牲層]42及圖案化遮罩層…的步驟；二 除:接：的：犧牲層142，再將該圖案化遮罩層135剝 ^示 再移除接觸窗140内的犧牲層142,如3F圖 播ί 閱第圖，施以微影及蝕刻製裎定義一導電雀 i屬iiT些接觸窗14〇。依序沉積—阻障層】5〇及二 ^^層】55於半導體基板上。_層⑼的材質為_ 括虱化鈦、鎢/氮化鎢或鈕/氮化鈕’順應性地 的材電層130以及開口 M〇上。金屬導電層155 的材貝為金屬鎢或銅。 驟，」施以平坦化步驟，例如化學機械研磨(CMP)步 岸夕于、弟—介電層13〇上的部分金屬導電層⑸及阻障 曰 以形成一内連線結構，如第3H圖所示。 获^由於多晶石夕層】35已於先前步驟中與犧牲層】42-併 1夕35:觸因此：障層(複合層Ti/™)不與多晶矽層遮罩層 接觸’便無金屬石夕化物殘留的問題。根據本發明實秭Ti/4: In the manufacturing process of the conventional semiconductor device, the composite layer TVTiN and the polycrystalline germanium layer 35 are directly contacted with a w / 55 55 / Φ - contact to form a metal (tungsten) conductive layer such as yttrium titanium oxide. s will form a telluride at the surface of the quotation (example 2 is shown in the first & diagram > 35 Α Λβ [〇tj. 9 ,,, 3 layers of Ti/TiN and polycrystalline slab layer 2 See Fig. 2 for the high temperature effect of the interaction between Shixi and Titanium "" at the interface 51 position, due to the formation of unreacted niobium grains in the mixed region with the niobium oxide crystal grains 5] b 5] a Titanium telluride # μ μ %', zone or. Since the unreacted niobium grains 51a and the Xihua titanium S曰 pull training are completely different in nature, they cannot be single flattened. 6 1343632 No. 9 Qing 74 Patent Description 懿正本本修正日期: March of the new year Training (Chemical Mechanical Polishing, CMP) step 6G is smoothly removed, and the conduction: Xihua = retention, causing bridging between the bit lines of the semiconductor components, affecting the efficiency and reliability of the components. [Summary] The invention provides a method for manufacturing a semiconductor device, which avoids the formation of a stellate compound in the smectic layer and the barrier layer, thereby causing the subsequent flat bismuth compound to remain, thereby avoiding the fat guide and the gutta-percha, improving the component performance and reliability. Bridge between the metric lines: a method for manufacturing a semiconductor component, a ridged soil plate, The gate has a plurality of gate structures. The germanium-dielectric layer is formed on the semiconductor substrate. The germanium is formed on the electrical layer. The patterned germanium cap layer is a hard cover and the dielectric layer is sacrificed. Layering on the patterned mask layer and into the contact layer. Partially removing the mask layer, exposing the dielectric layer and embossing the pattern and embossing the lithography and defining the process The sacrificial layer of J2 is high. The sacrificial layer is applied to the solid layer. The semiconductor layer is deposited on the semiconductor substrate, and a portion of the metal conductive layer on the metal substrate is removed. The dielectric structure is formed by a barrier layer to form an inner junction. The embodiment of the present invention further provides a method for manufacturing a half-guided f# limb member, which comprises a pen and a man-made board. There is a plurality of gate junctions m between them. The -first-flattening step is applied to the = open-pole structure, and the plurality of structures are high. Forming - the second dielectric layer; 7 Γ 343632 Patent No. 974 Patent Specification Amendment曰期: On March 25, 00, j forms a patterned mask layer on the second dielectric layer. a hard mask and off (four) - formed with the second dielectric layer - a sacrificial layer on the patterned mask layer and into the Ϊ, the portion of the sacrificial layer and the patterning are removed in sequence The mask is separated from the second dielectric layer and is aligned with the sacrificial layer in the contact window: the engraving process defines a conductive trench corresponding to the contact window "and on the semiconductor substrate, and is applied - second a portion of the metal conductive layer on the second dielectric layer?:: a far inner wiring structure. The early layer is formed to make the above objects, features and advantages of the present invention more specific. And in conjunction with the drawings, a detailed description is as follows: [Embodiment] For example, the similar or identical parts of the drawings are used; the figure number: 逑:: the phase is the thickness can be expanded' Simplified or easy to mark. </ br /> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In addition, the specific embodiments are only two-inclusive and are not intended to limit the invention. And a diagram showing a cross-sectional view of each step of fabricating a contact window on a semiconductor device in accordance with an embodiment of the present invention; FIG. 8 is a semiconductor substrate η〇, such as a single crystal 矽, 锗,: 1343632 Patent Specification No. 96U8974 The date of this revision: on March 25, 100, the wrong substrate has a state 01) substrate having a plurality of side pole structures 20a 120e thereon. The substrate 11 can be divided into a main element array area and a peripheral control area. The gate structures 120a-120c indicate elements disposed in the main element array field and the gate structure 120e indicating elements disposed in the peripheral control area. Next, referring to FIG. 3B, a first dielectric layer 125 is formed on the semiconductor substrate 11〇, filled between the plurality of gate structures 12〇a_i2〇e, and subjected to a planarization step, such as chemical mechanical polishing ( The CMp) step causes an n-electrode layer 125 to be aligned with a plurality of gate structures 12a_a 12E. Then, a second dielectric layer 30 is formed on the first dielectric layer 25, and the layer W is formed on the second dielectric layer 13A. The first dielectric layer 125 and the second second electrical layer 130 are made of a low dielectric constant 〇〇w_k) material layer (4) salt glass (4) or Jing = I glass (BPSG). The material of the second dielectric layer 13Q may also be tetra-ethyl-otho_silicate (TE〇s). Applying lithography and roughness to the soil, patterning multiple (four) 135 into a mask layer and defining a plurality of plate contact openings (substrate contari η (10) corresponding to base rb:t]jnp f C〇maCt叩), bit line Contact opening (C Ct hne) and gate contact opening (gate t. Next, to pattern the mask layer 13: the first and second dielectric screens 125 nn, ... 心 more mask sub-etching as shown in Figure 3D As shown, S forms a plurality of contact windows] 4 〇, =, please refer to Figure 3E 'Form a substrate 】 〇 并 并 并 并 并 并 并 并 并 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案The sacrificial layer U2 and the patterned mask 9 1343632 t white 1 移除 can be sequentially removed by the chemical mechanical polishing (CMp) method. The sacrificial layer 142 of the knives and the patterned mask layer 135. Or, the sacrificial layer 42 of the node and the step of patterning the mask layer; the second: the: sacrificial layer 142, and then the patterned mask The layer 135 strips and removes the sacrificial layer 142 in the contact window 140, such as the 3F image, and the lithography and etching process defines a conductive fin iiT The contact windows 14〇 are sequentially deposited—the barrier layer】5〇 and the second layer】55 on the semiconductor substrate. The layer (9) is made of 虱 titanium, tungsten/tungsten nitride or button/nitriding. The button is compliant with the material layer 130 and the opening M. The metal conductive layer 155 is made of metal tungsten or copper. [Steps," a planarization step, such as chemical mechanical polishing (CMP) stepping, a part of the metal conductive layer (5) on the dielectric layer 13 and the barrier layer to form an interconnect structure, as shown in Fig. 3H. Obtained due to the polycrystalline layer 35 layer 35 has been sacrificed in the previous steps Layer] 42- and 1 35 35: Touch: Therefore, the barrier layer (composite layer Ti/TM) does not contact the polysilicon layer mask layer, so there is no problem of metal ruthenium residue remaining. According to the present invention
Hi匕鈦殘留得以解決，且避免半導體元件的位元線之一 曰’ 9橋接，改善其元件效能及可靠度。 本發=雖以較佳實施例揭露如上’然其並非用以限定 1、明的範圍’任何所屬技術領域中具有通常知識者，在 :脫離本發明之精神和範#可做些許的更動與潤 一口此本表明之保護範圍當視後附之申請專利範圍所界 疋者為準。 1343632 v - 第96128974號專利說明書修正本 修正日期：100年3月25曰 【圖式簡單說明】 第1A-1H圖係顯示傳統製作接觸窗及位元線接觸於半 導體元件上的各步驟的剖面示意圖； 第2圖係顯示於第1G圖中複合層Ti/TiN與多晶矽層 3 5的局部區域2的放大圖；以及 第3A-3H圖係顯示根據本發明實施例之製作接觸窗及 位元線接觸於半導體元件上的各步驟的剖面示意圖。 【主要元件符號說明】 習知部分（第1A〜2圖） 10〜半導體基板； 25〜第一介電層； 35〜多晶石夕層、圖案化遮罩層； 38〜開口； 45〜導電溝槽； 55〜金屬導電層； 2〜局部區域； 51a〜未反應矽晶粒； 52〜鈦(Ti)層； 本案部分（第3A〜3E圖） 110〜半導體基板； 120a_120e〜閘極結構； 130〜第二介電層； 138〜開口； 142〜犧牲層； 150〜阻障層； 20a_20e〜閘極結構； 30〜第二介電層； 40〜接觸窗； 50〜阻障層； 60〜平坦化步驟； 51〜界面； 5 lb〜矽化鈦晶粒； 54〜氮化鈦(TiN)層。 125〜第一介電層； 135〜多晶石夕層、圖案化遮罩層； 140~接觸窗； 145〜導電溝槽； 155〜金屬導電層。The Hi匕 titanium residue is solved, and one of the bit lines of the semiconductor element is prevented from bridging, improving the component performance and reliability. The present invention is disclosed in the preferred embodiment as described above, but it is not intended to limit the scope of the invention, and the scope of the invention is not limited to the spirit of the invention. The scope of protection stated in this copy is subject to the scope of the patent application attached. 1343632 v - Patent Specification No. 96228974 Revision Date: March 25, 100 [Simplified Drawing] The 1A-1H system shows the cross section of the conventionally fabricated contact window and the contact of the bit line with the semiconductor element. 2 is an enlarged view showing a partial region 2 of a composite layer Ti/TiN and a polysilicon layer 35 in FIG. 1G; and a 3A-3H diagram showing a contact window and a bit in accordance with an embodiment of the present invention. A schematic cross-sectional view of the steps in which the lines are in contact with the semiconductor device. [Description of main component symbols] Conventional part (Fig. 1A to 2) 10~ semiconductor substrate; 25~first dielectric layer; 35~ polycrystalline layer, patterned mask layer; 38~ opening; 45~ conductive Groove; 55~ metal conductive layer; 2~ partial area; 51a~ unreacted germanium grain; 52~ titanium (Ti) layer; part of the case (3A~3E) 110~ semiconductor substrate; 120a_120e~ gate structure; 130~second dielectric layer; 138~opening; 142~ sacrificial layer; 150~ barrier layer; 20a_20e~ gate structure; 30~ second dielectric layer; 40~ contact window; 50~ barrier layer; Flattening step; 51~ interface; 5 lb~ titanium telluride grain; 54~ titanium nitride (TiN) layer. 125~first dielectric layer; 135~ polycrystalline layer, patterned mask layer; 140~ contact window; 145~ conductive trench; 155~ metal conductive layer.