TW447080B - Manufacturing method of dual damascene semiconductor device - Google Patents

Abstract

There is disclosed a manufacturing method of dual damascene, which provides the semiconductor device with a small dimension and a easy manufacturing method. The present invention provides a manufacturing method of dual damascene, which comprises providing a semiconductor device having a semiconductor substrate; next, after completing the step of manufacturing transistors, depositing a first dielectric layer on the surface of the semiconductor substrate; then, forming a first photoresist layer on the first dielectric layer, and using the first photoresist layer as a mask to etch the first dielectric layer; after removing the photoresist layer, depositing a first inter-metal dielectric layer on the surface of the semiconductor substrate and above the first dielectric layer; using the chemical mechanical polishing method to planarize the first inter-metal dielectric layer until the first dielectric layer is exposed; further, depositing a second dielectric layer on the planarized first inter-metal dielectric layer; then, forming a second photoresist layer on the second dielectric layer, and using the second photoresist layer as a mask to etch the second dielectric layer; then, after removing the photoresist layer, depositing a second inter-metal dielectric layer on the first inter-metal dielectric layer and on the surface of the second dielectric layer, and using the chemical mechanical polishing method to planarize the second inter-metal dielectric layer until the second dielectric layer is exposed; next, etching the second dielectric layer and the first dielectric layer to define a second wiring layer and a first wiring layer for thereby forming a dual damascene structure; then, forming a barrier layer on the surface of the second inter-metal dielectric layer and in the second wiring layer and the first wiring layer; finally, depositing a metal layer on the barrier layer wherein the metal layer is filled in the second wiring layer and the first wiring layer.

Description

^ 447 0 8 0 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device-a new double-layer embedding method, which enables it to obtain a small scale. About + 7G pieces of conductor and 5-2 background of the invention: Recently, the demand for semiconductor components is increasing rapidly. Especially the computer is fast. Since hundreds or thousands of electricity are required to be manufactured on a single semiconductor wafer, it is necessary to reduce the size of the device due to its density characteristics. Due to the large number of electronic components, the semiconductor device needs to be composed of crystals, and the integrated crystal circuit is very complicated. It increases the electronic components in the integrated circuit, and keeps the original k of the component. A simplified manufacturing method is the first. The first to seventh figures show a conventional method for manufacturing a double-layer wire structure of a semiconductor device. The chemical vapor deposition (CVI) method is used to deposit an oxide layer 120 with a layer thickness of about 4000 to 6000 angstroms above the surface of the semiconductor substrate 100. However, the height of the halide layer 120 is determined by the subsequent metal filling. Depending on the height. Immediately after the photoresist is used as a mask, the oxide layer 1 2 0 is etched by anisotropic etching to form a first metal wire. Then, a metal layer 160 is deposited on the semiconductor substrate 100 and inside the first metal wire 140, and then, a chemical mechanical polishing (CMP) technique is used to planarize the etched metal layer 160.

Page 5 447080 V. Description of the invention (2) The thickness of the metal layer 160 is approximately equal to the thickness of the oxide layer 120. Next, a conductive metal layer is deposited on the semiconductor device by physical vapor deposition (PVD), and then a photoresist is used as a mask, and the conductive metal layer 180 'is etched by anisotropic silver engraving to form a second metal wire 200. Next, a plasma-assisted chemical vapor deposition (PECVD) method was used to deposit an inter-metal dielectric layer 220 over the semiconductor device, and then the technology of chemical mechanical polishing (CMP) was used to flatten the surface.化 etching the inner metal dielectric layer 240. The eighth to fourteenth drawings are another conventional method for manufacturing a double-layered semiconductor device. An oxide layer 120 having a thickness of about 4000 to 6000 angstroms is deposited by chemical vapor deposition (CVD) on the surface of the semiconductor substrate 100. However, the height of the oxide layer 120 is based on the height of the subsequent metal filler. It depends. A chemical vapor deposition (CVD) method is used to deposit a silicon nitride layer 300 over the oxide layer 120. The silicon nitride layer 300 is used as a stop layer for the second metal wire etching. Then, a plasma-assisted chemical vapor deposition (PECVD) method is used to deposit an internal dielectric layer 320 with a thickness of about 4000 to 6000 angstroms over the semiconductor element, and then 'chemical mechanical polishing (C MP technology) planarizes the metal dielectric layer 320 within the silver engraving. Using a photoresist as a mask, the inner metal dielectric layer 36 is etched first using anisotropic etching, and then the silicon nitride resist layer 3 8 0 is etched to form a second metal wiring 3 4 0. Then, a photoresist layer is deposited on the semiconductor element, and the photoresist layer 400 is etched using an anisotropic etching method to form a first metal frame line 42. .

Page 6 447080 V. Description of the invention (3) Due to the conventional dual damascene method, the thickness of the photoresist layer 400 is too thick, which causes difficulty in exposure resolution. Moreover, the double-layer talk-in method can replace the traditional plasma etching method to complete the copper metal pattern. Therefore, a new double-layer embedded manufacturing method is urgently needed to obtain a small-sized semiconductor element and a simpler manufacturing method. 5 ~ 3 Objects and Summary of the Invention: The purpose of the present invention is to provide a new double-layer embedded manufacturing method, a wet etching method of silicon nitride layer, which can etch out two layers of wire release, followed by 2 dry etching. Method, the remaining silicon nitride layer is etched to obtain a complete double-layer embedded structure. Yet another object of the present invention is to provide a new method for manufacturing a semiconductor device by using a wet etching method of a silicon nitride layer on the silicon nitride layer and the oxygen layer ', which can obtain a high etching selection ratio. According to the above-mentioned purpose, the present invention provides a new two-layer embedded manufacturing method, which includes providing a semiconductor device having a semiconductor element. After the transistor manufacturing step is completed, then, the first dielectric conductor substrate is over. Then, a first photoresist layer is formed on the first dielectric layer, and the first dielectric layer is etched by using the first photoresist layer as a photomask. ， 着 ’The first internal metal dielectric layer is deposited on the first dielectric remaining after the etching

Page 7 4 47 0 8 0 5. Description of the invention (4) The first inner metal dielectric layer is planarized to expose the first dielectric layer by chemical mechanical polishing on the substrate and the semiconductor substrate. Furthermore, a second dielectric layer is deposited over the first inner metal dielectric layer and the first dielectric layer after the planarization. Then, a second photoresist layer is formed over the second dielectric layer, and the second dielectric layer is etched by using the second photoresist layer as a photomask. The etching selectivity of the second dielectric layer and the first inner metal dielectric layer is used to stop the etching of the second dielectric layer on the first inner metal dielectric layer. Next, a second inner metal dielectric layer is deposited over the surfaces of the first inner metal dielectric layer and the second dielectric layer, and the second inner metal dielectric layer is planarized to expose the second inner metal dielectric layer by a chemical mechanical polishing method. Dielectric layer. Next, the second dielectric layer and the first dielectric layer are etched to define a second layer of wiring and a first layer of wiring to form a double-layered structure. Then, a barrier layer (b a r r i e r 1 a y e r) is formed on the second layer wire, the inside of the first layer wire and the surface of the second inner metal dielectric layer. Finally, a metal layer is deposited over the barrier layer, and the metal fills the interior of the second layer of wiring and the first layer of wiring. 5-4 shows the diagram briefly: The first to seventh diagrams show a conventional manufacturing method of a double-layer wire structure. The eighth to fourteenth drawings are the manufacturing methods of the conventional manufacturing method of the double-layer wire structure. The fifteenth figure is a cross-sectional view of the operation of each step of the double-layer embedding method in the embodiment of the present invention, which includes the formation of a semiconductor substrate and a first silicon nitride layer. The sixteenth figure is the operation of each step of the double-layer embedding method in the embodiment of the present invention.

4 47 08 0 V. Description of the invention (5) A sectional view including the formation of a first silicon nitride wire and a first inner metal dielectric layer. The seventeenth figure is a schematic diagram showing the operation of each step of the double-layer embedding method according to the embodiment of the present invention, which includes the formation of a second silicon nitride layer. The eighteenth figure is a schematic diagram of the operations of each step of the double-layer embedding method in the embodiment of the present invention, which includes the formation of a second silicon nitride wire and a second inner metal dielectric layer. The nineteenth figure is a schematic diagram of each step of the double-layer embedding method in the embodiment of the present invention, which includes the etching of the first silicon nitride wire and the second silicon nitride wire and the formation of a barrier layer. The twentieth diagram is a schematic diagram of the operations of each step of the double-layer embedding method in the embodiment of the present invention, which includes the formation of a conductive metal. Symbols of the main parts: 1 0 0 Silicon substrate 120 Oxidation layer 140 First layer wire 160 Conductive metal 1 80 Conductive metal 200 Second layer wire 220 Flattening the metal dielectric layer in the metal dielectric layer 240 3 0 0Metal dielectric layer in silicon nitride barrier layer 320

Page 9 447080 V. Description of the invention (6) 340 second layer wire 3 rows 0 metal dielectric layer after etching 380 silicon nitride barrier layer 400 photoresist layer 420 first layer wire 430 barrier layer 440 after etching Conductive metal layer 460 etched conductive metal layer 10 cut substrate 1 2 silicon nitride layer 12A first silicon nitride wire 14 photoresist layer 16 I anisotropic etching 18 first inner metal dielectric layer 20 second Silicon nitride layer 20A, second silicon nitride wire 2 2 photoresist layer 24 anisotropic etching 26 second inner metal dielectric layer 3 0 barrier layer 32 conductive metal layer 5-5 Detailed description of the invention:

Page 447080 V. Description of the invention (Ό Figure 20 shows a cross-sectional view of the double-layer embedding method in the embodiment of the present invention. Figures 15 to 19 show the exploded schematic diagram of the manufacturing method of the double-layer embedding method β In these drawings, the same elements are denoted by the same reference numerals.

The fifteenth figure shows that the semiconductor substrate 10 uses a silicon substrate of electrical P type; however, an n-type silicon substrate can also be used. After all transistor manufacturing steps are completed, a first silicon nitride layer 12 is deposited by chemical vapor deposition (CVD) to a thickness of between about 8000 and 11,000 angstroms over the semiconductor substrate 10. However, its nitride The height of the silicon layer 12 depends on the height of the metal filler. Immediately after, the silicon nitride layer 12 is etched using a photoresist as a mask by an anisotropic etching method. The sixteenth figure shows that the anisotropic silver engraving method is used to etch the nitride nitride layer 1 2. After photoresist removal, next, a plasma-assisted chemical vapor deposition (PECVD) or high-density plasma (HDP) -assisted chemical vapor deposition method is used to deposit a layer with a thickness of about 12,000 to 15,000 angstroms. An inter-metal dielectric layer 18 is formed on the semiconductor substrate 10 and the nitrided hard wire 1 2 A ′, and then a chemical mechanical polishing (c μ ρ) technique is used to planarize and etch the first inter-metal dielectric layer. Layer 8 to expose the top surface of the first nitrided layer 12A. θ Figure 17 shows that a second silicon nitride layer 20 with a thickness of about 8000 to 1 1 000 angstroms is deposited by chemical vapor deposition (CVD) on a flat surface.

447 0 8 0 V. Description of the invention (8) The nitride cutting layer 12A and the surface of the first inner metal dielectric layer 18 are above. However, the height of the nitride nitride layer 20 depends on the height of the metal filler. Then, using the photoresist 22 as a mask, the silicon nitride layer 20 is etched by an anisotropic etching method, so that the etching is stopped at the first inner metal dielectric layer. The eighteenth figure shows that the silicon nitride layer 20 is etched by an anisotropic etching method. Then 'the plasma-assisted chemical vapor deposition (pECVD) or high-density electroplating C HDP' is used to deposit a second internal metal dielectric with a thickness of about 1 2000 to 1 5000 Angstrom A layer (dielectric iayer) 26 is above the surface of the second silicon nitride layer 20A and the first inner metal dielectric layer 18. Then, using a technique of chemical mechanical polishing (CMp), the second inner metal dielectric layer 26 is etched with silver to planarize the top surface of the second silicon nitride layer 20A. The second silicon nitride layer 20 A and the first silicon nitride layer 12 A are etched by a wet etching method, and the prototypes of forming the second metal wire and the first metal wire are shown in Fig. 19, respectively. Then, the remaining second silicon nitride layer 20A and the first silicon nitride layer 12A are etched by dry etching to form a second metal wire and a first metal, respectively. Next, the conductive material of the barrier layer 30 is formed on the surface of the second metal wire, the first metal wire inside and the second metal dielectric layer 26, which can avoid filling with aluminum and tungsten metal. The peak phenomenon of the aluminum-silicon interface caused by the time, and the adhesion of tungsten to other materials is improved. The more commonly used barrier layer materials are two kinds of nitride nitride TiN and tungsten nitride Tiw.

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447080 V. Description of the invention (9) Finally, the twentieth figure shows that the titanium nitride T i N is used as a barrier layer. Above the structure, the second layer of metal frame line and the first layer of metal frame line are filled with conductive metal 32, and the second layer of metal frame line and the first layer of metal frame line are used to connect the respective components. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patents.

Claims (1)

447080 6. Scope of patent application 1. A double-layer embedding method for a semiconductor device, including at least the following steps: providing a semiconductor device having a semiconductor substrate; depositing a first dielectric layer on the semiconductor substrate; forming a first A photoresist layer is over the first dielectric layer; using the first photoresist layer as a photomask, #etching the first dielectric layer; depositing a first inner metal dielectric layer on the semiconductor substrate and after etching Above the first dielectric layer, the first inner metal dielectric layer is planarized by chemical mechanical polishing method to expose the first dielectric layer; a second dielectric layer is deposited on the first inner metal layer. Forming a second photoresist layer over the second dielectric layer; and using the second photoresist layer as a photomask to describe the second dielectric layer; A second inner metal dielectric layer is deposited over the surfaces of the first inner metal dielectric layer and the second dielectric layer, and the second inner metal dielectric layer is planarized to expose the second inner metal dielectric layer by a chemical mechanical polishing method. Dielectric layer; etching the second dielectric Layer and first dielectric layer to define a second layer wire and first layer wire; forming a barrier layer on the second layer wire, the inside of the first layer wire and the second inner metal dielectric layer Over the surface; and depositing a metal layer over the barrier layer, and the metal fills the interior of the second layer of the line and the first layer of the line. 2. The double-layer embedding method according to item 1 of the scope of the patent application, wherein the first dielectric material mentioned above includes at least a gasified stone. Page 14 447080 6. Scope of patent application 3. The double-layer embedding method described in item 1 of the scope of patent application, wherein the above-mentioned second dielectric material includes at least silicon nitride. In the description above, his method is proud. The double-layered double-layered oxygen package contains two items, including the first to the second layer. Fan Dianli is the exclusive application of Jin Shenner as described in Section 4. Section 5. The double-layer embedding method as described in Section 1. The second inner metal dielectric layer includes at least silicon dioxide. .6. The double-layer embedding method as described in item 1 of the scope of the patent application, wherein the above barrier layer includes at least ΤίN. 7. The double-layered embedding method according to item 1 of the scope of the patent application, wherein the barrier skin mentioned above includes at least T i W. 8. The double-layer embedding method according to item 1 of the scope of the patent application, wherein the first internal metal dielectric layer planarization method is made by a chemical mechanical polishing method or an etching method. 9. The double-layer embedding method as described in item 1 of the scope of the patent application, wherein the second internal metal dielectric layer planarization method is a chemical mechanical polishing method. i 0, a double-layer embedding method for semiconductor devices, including at least the following steps: Page 15 447 0 8 0 VI. Patent Application Fanyuan— ~ -------- Provide-Semiconductor element 'which has a silicon substrate; deposit a first silicon nitride layer on the silicon substrate; Forming a first photoresist layer over the first silicon nitride layer; using the first photoresist layer as a light lift, # isotropically etching the first nitride nitride layer, a first inner metal dielectric layer on Above the silicon substrate and the etched first stone, the first inner metal dielectric layer is planarized to expose a first nitride nitride layer by a chemical mechanical polishing method; a second silicon nitride layer is deposited on the first silicon nitride layer; Over the first inner metal dielectric layer and a portion of the first nitride layer; forming a second photoresist layer over the second silicon nitride layer; using the second photoresist layer as a photomask, an anisotropic surname Etch the second siliconized silicon layer; deposit a second inner metal dielectric layer over the surfaces of the first inner metal dielectric layer and the second dielectric layer, and use chemical mechanical polishing to make the second inner metal dielectric layer The metal dielectric layer is planarized to expose the second silicon nitride layer; the second silicon nitride layer and the first nitride are etched by a wet etching method. A silicon layer is used to etch a second layer of metal wiring and a first layer of metal wiring model, and then a dry silver engraving method is used to etch a second layer of metal wiring and a first layer of gold wiring; forming a barrier layer on S A second layer of wire, the inside of the first layer of wire, and the surface of the second inner metal dielectric layer; and a metal layer is deposited over the barrier layer, and the metal fills the second layer of wire and Inside the first layer of wire. Page 16 447080 6. Scope of patent application 1 1. The double-layer embedding method described in item 丨 0 of the scope of patent application, wherein the first inner metal dielectric layer can be plasma-assisted chemical vapor deposition ( PECVD) or high-density plasma (hdp) assisted chemical vapor deposition. 1 2 · The double-layer embedding method as described in the scope of the patent application, wherein the second internal metal dielectric layer may be plasma-assisted chemical vapor deposition (pECVD) or high-density plasma (HDp) ) Assisted chemical vapor deposition. Described. The upper part of the middle table, the upper part of the upper method of the inlay frame of the above method is described in the above table. The special line is larger than the 10th table.-The special line of Fan Shangli, please apply for the second layer. The double-layer embedding method as described in the item 10 of the scope, wherein the above-mentioned second-layer wire-line engraving is performed by a wet-type method and a dry-type method. The 15 * double-layer embedding method as described in item 10 of the scope of patent application, wherein the above-mentioned layer-frame wire etching is etched by wet etching and then by dry etching. 16 · The double-layer embedding method described in item 10 of the patent scope, wherein the above-mentioned i-type epitaxial method 'includes the removal of the first and second silicon nitride layers by hot phosphoric acid Page 17