TWI246163B - Method for fabricating an integrated semiconductor circuit - Google Patents

Abstract

The invention relates to a method for fabricating an integrated semiconductor circuit, in which electric contacts (20) for first conductive structures (1) are fabricated in the memory region (I) and contact is made with the first conductive structures (1) without contact being made with second conductive structures (2) which are arranged to the sides of the first conductive structures (1) and laterally adjoin the first conductive structures (1) or are arranged too closely next to them for it to be possible for the second conductive structures to be lithographically masked selectively with respect to the first conductive structures. According to the invention, contact is made with the first conductive structures (1) as a result of a conductive layer (L), which is used in the logic region for example for the production of gate electrodes, being deposited in the memory region, at the height of the first conductive structures (1) which are above the second conductive structures (2), after a planarization step and being patterned. In the process, intermediate contacts (10) are patterned, the width of which is such that contact holes for the electric contacts (20) can be aligned on them. This eliminates the need to deposit a nitride layer to protect the second conductive structures (2).

Description

1246163 V. Description of the Invention (1) The present invention relates to a method for manufacturing an integrated semiconductor circuit. The integrated semiconductor circuit has a memory region and a logic region on a semiconductor substrate, and is used for electrical contact of the first conductive structure. The pieces are manufactured in the memory area, and a conductive layer is deposited in the logic area; wherein the second conductive structure is laterally adjacent to the first conductive structure, or is arranged too close to the first conductive structure The conductive structure makes it impossible to be selectively masked with respect to the first conductive structure,-wherein the first conductive structure extends at least to a height higher than the second conductive structure, and-wherein a The second conductive structure is brought into contact with the first conductive structure. The invention also relates to an integrated semiconductor circuit as described in the preface to item 12 of the scope of patent application. The integrated semiconductor memory has a memory area of a cell array of a plurality of memory cells (memory c e 1 1 s), and each memory cell includes at least one selection transistor and a storage capacitor. The semiconductor memory also has a logic area in which logic circuits for operating and driving the cell array are arranged. The performance of semiconductor memory is determined by the density of the memory cells in the memory cell array of the semiconductor substrate. In order to be able to store the largest possible amount of information, the memory cell must be manufactured with the smallest possible memory cell area. In a memory cell array, a semiconductor memory has, for example, a deep trench capacitor (deep trench) for storing an information item and a vertical selection transistor, that is, a MOSFET (metal oxide semiconductor field effect transistor), etc. Two source / drain regions of a transistor

1246163 V. Description of the invention (2) One is arranged above the other and is connected by a channel extending vertically (that is, perpendicular to the substrate surface) according to the switch state. In the case of a vertical selection transistor, its gates are arranged laterally with respect to the source / drain regions and channel regions, and are often designed in the form of a vertical spacer due to space factors. This spacer is separated from other electrodes only by a vertically extending thin gate oxide layer. The lateral distance between the upper source / drain and the gate is not sufficient to make it possible for the second conductive structure to be selectively masked with respect to the first conductive structure. Therefore, selective contact can only be achieved with the assistance of a self-alignment procedure. In order to connect these memory cells, the upper source / drain must be connected to the bit line without gates. The gates are formed as part of the spacer word line, and the upper source / drain and A short circuit is formed with the bit lines. This causes difficulties when applying electrical contacts to the top side of the upper source / drain region from above, because the contact width and the inevitable alignment tolerance defined by the optical resolution limit mean that it is impossible to avoid the gate A short circuit occurred between the poles. In addition, the contact depth required to make the electrical contacts is so large that it is impossible to accurately determine when to reach the top side of the upper source / drain during the contact hole etching process. The etching irregularly extends to a larger depth than expected, and will contact the gate designed as a spacer without any countermeasures, and its top edge is at a level slightly deeper than the upper source / Depth on the top side of the drain. To avoid this short circuit, the zigzag lines that make up the gate are traditionally covered with nitride to stop the oxide layer before applying oxide as another filling material. The upper source is then performed by a selective etch process that does not attack the silicon nitride layer

Page 9 1246163 V. Description of the invention (3) Contact hole etching of electrical contacts in the pole / drain region. This deposits an additional nitride layer to avoid accidental contact with the second conductive structure (gate) during contact etch to achieve electrical contact with the first conductive structure (upper source / drain). The approach requires a more complex procedure, requiring additional labor and time, and additional costs. We would expect it to be possible to make electrical contact with the first conductive structure without the need to deposit and pattern an additional nitride layer (ie, without the need for an additional lithographic patterning step). In addition, I would expect that the process steps required to make the logic region anyway can be used to achieve selective contact with the first conductive structure in the memory region without the need for additional process steps. For example, it would be desirable to use a method of manufacturing gates in a logic region to achieve contact with a first conductive structure in a memory region. The object of the present invention is to make contact with the first conductive structure without causing the arrangement to be directly adjacent to the first conductive structure laterally or to be short from the lateral distance of the first conductive structure only by a self-alignment. The program achieves a short circuit with the second conductive structure that is in selective contact with the first conductive structure. Contact is intended to occur without additional cost, particularly without an additional lithographic patterning step. This § is achieved by the method described in the introduction, in which contact with the first conductive structure occurs through the following steps:-The integrated semiconductor circuit is flatter in the memory area than the second conductive structure, with the result being only The first conductive structure is not covered,-the conductive layer is thus deposited in the memory area at this height, and-an intermediate contact is formed on the first conductive structure by means of the conductive layer

Page 10 1246163 5. Description of the invention (4) The width of these intermediate contacts enables the contact holes for the electrical contacts to be-aligned on the intermediate contacts and-to apply the electrical contacts to the middle Contacts. According to the present invention, the silicon nitride layer traditionally required to cover the second conductive structure is eliminated. In order to selectively make contact with the first conductive structure relative to the second conductive structure arranged directly next to the first conductive structure, the present invention uses the elevation of the upper side of the first conductive structure (such as the source / drain region). (1 eve 1) The fact that it is slightly higher than the upper side of the second conductive structure, such as the gate. The semiconductor substrate is highly flattened in the memory region in which the first conductive structure is arranged but still above the second conductive structure. This means that even a slight difference in height between the upper sides of the two types of structures will form a surface that does not only cover the first conductive structure. This surface still does not provide protection against contact with a second conductive structure located directly below the surface. However, according to the present invention, the conductive layer deposited in the logic region is simultaneously deposited in the memory region only at a height where the first conductive structure is not covered. This conductive layer is used to form an intermediate contact on the first conductive structure. In the simplest case, the intermediate contact is formed directly from the material of the conductive layer. For this reason, the conductive layer is patterned in the memory area in such a way that the first conductive structure, which was previously uncovered in the planarized surface, is in any case covered by an intermediate contact made of a conductive layer material. . After β, as in the conventional method, a true electrical contact is formed, but in this case it is applied to the intermediate contact that has been introduced. These intermediate contacts are patterned by a lithography method by which the gates and layers in the logic region are patterned. Because the thickness of the dielectric to be etched is considerable,

Page 11 1246163 V. Description of the invention (5) During the contact hole etching to the substrate surface for a sufficient period of time, it will also contact the second conductive structure without any protective covering from above. However, according to the present invention, the intermediate contacts are applied to the first conductive structure, and the width of these intermediate contacts enables the contact holes for the electrical contacts to be aligned thereon. In this case, the lateral dimensions of the intermediate contact need only be wider than a contact hole at a height that contacts the upper side of an intermediate contact. The lateral dimension of the intermediate contact is larger than the lithographic feature size used; for example, it is possible to achieve a reliable alignment of the contact hole with respect to the upper side of the intermediate contact by a width of 1.2 times to 2.4 times the feature size. quasi. The larger the cross section of the intermediate contact than the feature size, the more reliable the alignment. The intermediate contact is preferably patterned with a lateral dimension of about 1.5 times to 2.5 times the optical resolution limit of the lithographic mask exposure. The gate of the transistor is preferably composed of a conductive layer in the logic region. These logic transistors are often also fabricated as MOSFETs, and the formation of a gate requires, in particular, the deposition of a polycrystalline silicon layer. According to the present invention, the polycrystalline silicon layer is simultaneously used to form an intermediate contact. The electrical contacts applied to the intermediate contacts are preferably applied together with the transistor contacts in the logic area. Although traditionally polysilicon layers are used as gates in logic regions and / or interconnects are manufactured, in the method according to the present invention, the electrical contacts above the intermediate contacts are on a plane connected to the logic region The contact holes of the source / drain region and / or the gate of the transistor are manufactured at the same time. These contacts are, for example, composed of tungsten. An embodiment of the method according to the present invention is proposed to be formed by the following steps

Page 12 1246163 V. Description of the invention (6) Contacts. -A pattern of a negative mask of one of the intermediate contacts is formed by the conductive layer, and a second material different from the material of the conductive layer is applied to the place where the second contact is to be formed,-relative to the first Two materials selectively etch back the conductive layer and replace them. A second material is introduced between the regions of the second material 'and-selectively etch back over the first conductive structure relative to the third material' The second material is replaced by a conductive material constituting the intermediate contact. Due to the imaging characteristics of the reticle used in lithography, only a limited contrast is reached between exposed and unexposed resist areas. If the area surrounding the base area of the middle and indirect contacts is to be exposed, the achieved contrast will be lower because the base area of the middle contact is also exposed to scattered and reflected light. Actually only the resist is exposed above the base area of the intermediate contact. If a negative image resist is used, i.e., the resist at the exposed position is removed in the developing step, the developed resist mask covers the area surrounding the base region of the intermediate contact. When the conductive layer is patterned, the latter is left uncovered in the area of the base region of the intermediate contact and left in place as a negative image mask on the remaining substrate surface. The area surrounding the source / drain contacts is thus covered by polycrystalline silicon. For the intermediate contact, polycrystalline silicon is required above the source / drain contact, so that subsequent deposition and etch-back operations are performed to reverse the negative image mask. First, a second material (which is different from polycrystalline silicon, preferably silicon oxide) is applied to the source / drain region (first conductive structure) by depositing on the entire surface, and then chemical mechanical Grinding. This layer must be used as an inter-metal dielectric to level the substrate above the gate in the logic region

Page 13 1246163 V. Description of the invention (7) Part of the mass deposition operation is automatically deposited. Then replace the negative image mask made of polycrystalline silicon with a negative image mask made of different materials. For this reason, the polycrystalline silicon conductive layer is selectively etched back with respect to the silicon oxide existing on the substrate region of the intermediate contact, and the polycrystalline silicon is deposited with a third material (preferably silicon nitride), and then replaces Polycrystalline silicon covers the area surrounding the substrate area of the intermediate contact. Secondly, the silicon oxide over the base region of the first conductive structure is etched back and replaced with a conductive material (preferably polycrystalline silicon again), at which time it forms an intermediate contact. Preferably, the conductive layer is composed of polycrystalline silicon, the second material is an oxide (preferably silicon oxide), the third material is a nitride (preferably silicon nitride), and the conductive material is polycrystalline Xi. Although the above embodiment reverses a negative image mask, according to an alternative embodiment, it is also possible to pattern the conductive layer into a positive image mask, in which case it remains in the first conductive structure and the immediately surrounding area (Equivalent to the width of the intermediate contact required for contact hole alignment). In this case, the intermediate contact is formed of the conductive layer. The method according to the present invention does not require a protective layer containing a nitride for the second conductive structure below the height to be planarized. Therefore, an oxide is applied to the second conductive structure and planarized together with the first conductive structure. With these intermediate contacts, an extra vertical space is achieved between the top side of the intermediate contact to be contacted and the top side of the second conductive structure to be protected according to the method of the present invention. The intermediate contact is preferably wider than the first conductive structure and covers the first conductive structure laterally. In particular, intermediate contacts

1246163 V. Description of the invention (8) It may extend laterally beyond the second conductive structure at a lower elevation. For example, this prevents accidental contact with the second conductive structure even during the considerable long etching time during contact hole etching. ~

According to a preferred application of the method of the present invention, the first conductive structure is a source / drain region of a vertical selection transistor of a memory cell, and the second conductive structure is a gate of a vertical selection transistor, and the latter is connected to the source / drain The polar regions are only laterally separated by a vertical gate oxide layer. However, the present invention can also be applied to selectively contacting any other desired structure, and is not limited to a vertically arranged transistor; in particular, it is possible to produce a memory cell having a buried word line. An alternative embodiment is for example the first conductive structure is a bit line or a storage node, that is, a selection transistor of a memory cell array is connected to the source / drain region of the storage capacitor. The purpose of the present invention is also achieved by the product of a semiconductor circuit as described in item 12 of the scope of the patent application. The intermediate contact in the memory area is applied to the first conductive structure at a higher degree than the second conductive structure. And the electrical contacts are applied to the intermediate contacts, the intermediate contacts:-their width enables the contact holes of the electrical contacts to be aligned on the intermediate contacts, and-their height is at most equal to the logic The thickness of the conductive region in the region. In an integrated semiconductor circuit, the conductive region is provided in the gate plane of the logic region, especially the gate layer itself and the contacts for the source / drain region and other substrate regions; in addition, in the gate electrode Highly formed interconnects. All such structures constructed at the same time as the gate is patterned have a consistent layer thickness

Page 15 1246163 V. Description of the invention (9) (and composed of the same material), the patterning and fabrication of parts that occur simultaneously are also apparent from the completed semiconductor circuit. The lateral dimensions of these structures are at least equal to the optical resolution of the lithographic mask exposure used in the process. The limit is that all lateral dimensions are always greater than a predetermined feature size. According to the present invention, the intermediate contact is applied to the memory area at a height higher than that of the second conductive structure, and then the electrical contact is applied to the intermediate contacts, which are wider than the first conductive structure. , Which laterally covers the second conductive structure and has a layer thickness at most equal to the layer thickness of the conductive region in the logic region. The fact that the second conductive structure is covered in the lateral direction prevents the second conductive structure from being short-circuited by the electrical contacts from above, and these electrical contacts are landed on the intermediate contacts according to the present invention. The layer thickness of the intermediate contact is not greater than the layer thickness of the conductive region formed in the logic region by the patterned conductive layer, because the intermediate contact in the memory region is made by means of the same conductive layer. The bottom side of the intermediate contact is preferably aligned at this height. In addition, the second conductive structure is preferably arranged at a deeper depth than the first conductive structure. The intermediate contact is preferably composed of the same material as the conductive region in the avoidance region. Because of the wide range of judgments, such as doping degree, layer sequence, particle size, crystal structure, particle size, alloy combination, etc., the material combination is a feature that will remain in the finished product, and because of the intermediate contacts and the conductive layer in the logic region _ The resulting structure is also made so that reliable conclusions can be made. The intermediate contact is preferably made of the same conductive material as the conductive region in the avoidance region. This eliminates the need for additional lithographic patterning operations. The conductive regions are preferably gate layers of transistors. As always need to be in the logic

Page 16 1246163 V. Description of the invention (ίο) The gates are made in the compilation area, and the intermediate contacts in the memory area can only be made with the aid of logical process steps which will be used anyway. The first conductive structure is preferably a source '/ dead region of a vertical selection transistor of the memory cell. FIG. 1 depicts a memory region I and a logic region II of an integrated semiconductor circuit, both of which are sketched in a cross-section and a top plan view. The cross-sectional views are A-A cross-sectional views of the basic outline plan view of the integrated semiconductor circuit. In the cross-sectional view, the top layer above a substrate is a bit line BL containing tungsten, and the electrical contact 20 is passed down to the surface of the substrate, where it is in contact with the first conductive structure 1 (that is, the vertical electrical selection). The strong negatively doped source / drain of the crystal) contacts. The lower source / drain region 5 is separated from the upper source / drain region 5 by the channel region 4 of the p-doped substrate. On the left-hand side, a thin gate oxide layer 3 and a word line 2 designed in the form of a spacer and protected on the top by a silicon nitride layer 6 a are located next to the channel region 4 in each case. The silicon nitride layer 6 a protects the gate electrode 2 during the etching process of the electrical contact 20 contact hole from above. According to the conventional method, this etching must be performed selectively with respect to the silicon nitride used to protect the layer 6a. Located below the transistor with electrodes 1, 2 and 5 is a p-doped semiconductor substrate S, of which a strongly negatively doped buried electrode BP (buried plate) is arranged at a large depth and is designed to penetrate deep into the substrate The external electrode of the storage capacitor DT (深 沟沟). In each case, the lower source / drain 5 is conductively connected to the internal capacitor electrode on the right hand side so that the information item is stored therein. The plan view of the basic outline of the memory area I shows the basic area of the storage capacitor DT and the basic area of the electrical contacts offset laterally therefrom.

Page 17 1246163 V. Description of the invention (id '—' ^ --- The electrical contacts are marked with a cross-shaped square area 20 and thus the electricity comes into contact with the upper source / drain area 1 from above. A planar transistor 40 and an interconnect 32 are shown in the logic region π, and the tungsten connection 1 from above passing through an insulating layer made of silicon dioxide contacts the two. 2 to 12 illustrate a method for manufacturing a semiconductor circuit, the design of the semiconductor circuit does not require the silicon nitride layer 6 a shown in FIG. 1 to protect the gate electrode 2 during the rest of the contact hole of the electrical contact 2 0. Figure丨 2 depicts a structure formed using the method according to the present invention at a method stage similar to that shown in FIG. 1. However, in the case of FIG. 12, a silicon nitride protective layer is not provided above the gate electrode 2. Only the oxide filling material 6 is guided above the gate 2 to the height of the source / inverted region 1. Fig. 2 illustrates a stage of the method according to the present invention, in which the semiconductor substrate s is already in the memory region. The source / drain region is uncovered and the height at which gate 2 is covered is flattened. The difference in the same degree between the source / drain 丨 and the top side of the gate 2 is not enough to etch the contact hole that will also attack the oxide layer 6 above the gate 3, preventing the gate 2 and the source / drain during time A short circuit occurs between the regions 丨. However, the present invention uses a substrate surface that has been flattened with respect to the height = to produce an intermediate contact in the vertical direction. For this reason, according to the diagram, in the case of the conventional semiconductor circuit, no matter what A polycrystalline silicon conductive layer that will be deposited on logic @ ΐ 1 is also deposited on memory area 1. The conductive layer is recorded on the area to form an intermediate contact on the source / side that is already uncovered at a high level. First make $ The electrical layer L forms a pattern in the memory area and the logic area.

Page 181246163 V. Description of the invention (12) If a gate electrode 3 丨 and an interconnecting part 32 of the planar transistor 40 are formed in the logic area I 丨, and the basic area of the intermediate contact is to be manufactured g is not covered by the parent in memory area I (Figure 4). A thin gate oxide layer having a thickness of about 3 nm (which had grown before the polycrystalline silicon conductive layer was deposited at a thickness of about 1000 nm) is located under the gate 31 which has been patterned in the logic region I. The polycrystalline stone layer 11 is shown in FIG. 4 in the lateral patterning operation in the memory area I and the logic area II in a conventional manner using a lithographic mask to pattern it and then using this Polycrystalline silicon is anisotropically etched using, for example, c2: f6 or oxygen. After the anti-resistance mask has been removed, for example, a thin oxide layer made of TE0s is deposited at a thickness of 20 nm and is anisotropically remnant. As a result, spacers are formed on the wall The remaining regions of the 3 9 crystalline silicon layer L 1 1, 3 1, 1 _ / μ… n 〇. -It also shows that the source / drain region 3 3 of the planar transistor 40 has been implanted in the logic region, and the surfaces of the electrodes 3 3, the gate 3 丨 and the interconnect 3 2 have been borrowed from The alignment debris processing process covers a silicide layer 34. The silicide layer 34 is used to improve the conductivity of the structure it covers. First, a nitride liner (not shown) having a thickness of, for example, 5 nm is deposited on the structure shown in FIG. 4, and then a dielectric (eg, TEOS having a thickness of 20 nm) is deposited on the nitride liner. The upper part then undergoes chemical mechanical franking operation (Figure 5). An n-doped polycrystalline silicon layer 36 having a thickness of, for example, 30 nm is deposited on the dielectric 35 to protect the logic region in a subsequent step for forming a middle corner in the cell array. The polycrystalline silicon layer is covered by an anti-resistive mask 4 which is removed from the cell array again after a while. The layer 36 is etched by means of CJe and oxygen; the nitride liner is also removed if appropriate. The negative image mask M surrounds the base region of the intermediate contact. Then apply one

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1246163 V. Description of the invention (13) The second material layer is the same as the negative image mask and is flattened, so that the filler 12 shown in FIG. 6 is formed above the base area of the intermediate contact. Then, the negative image mask 1 1 (FIG. 7) is removed, and a third material 13 (preferably a nitride ′) is deposited and etched back to the top side of the filler 12 (FIG. 8). Then, relative to the third material 1 3 (FIG. 9), the filling including the second material 12 is selectively removed. The filling is replaced by a conductive material 1 4 (preferably polycrystalline silicon), and the conductive material constitutes an intermediate contact. Piece 10 (Figure 10). In the process, a polycrystalline silicon layer 14 is first deposited and then planarized to the height of the top edge of the third material 13. Then, the arrangement of the intermediate contacts 10 (which is used as a termination pad) depicted in FIG. 10 allows the electrical contacts 20 to be formed, as shown in FIG. 11. After another insulating layer 37 including, for example, two φ silicon oxide has been deposited on the memory region I and the logic region II, the contact 20 and the transistor for the planar transistor source / drain terminal in the logic region The contacts 30 are formed together and / or with the contacts 4 2 for the interconnects 32 in the logical area. In the memory region, the electrical contact 20 formed by the oxide layer 37 having been patterned and deposited and planarized by a tungsten layer is adjacent to the top side of the intermediate contact 10. The lateral dimensions of the intermediate contact are selected so that the contact holes for the electrical contacts can be aligned thereon. In the process sequence shown in the figure, the polycrystalline silicon layer L by which interconnects and gates are formed in the logic region is also used to form a negative image mask of the intermediate contact 10 in the memory region I. An embodiment has been described above, in which one of the negative image masks N of the intermediate contacts 10 has been formed of the conductive layer L. Alternatively, it is possible that the intermediate contact 10 itself is formed directly from the conductive layer L. In this case, a positive mask is used to pattern the conductive layer L. -After the intermediate contact 10 has been formed according to one of the above embodiments,

Page 20 1246163 V. Description of the invention (14) ~ '一 " The contact holes of the electrical contact 20 are finally aligned on the intermediate contact 丨 0 and form an electrical * contact 2 0 (Fig. 1 1). Then, according to FIG. 12, a metallization layer is created; in the memory area, bit lines 38 are formed, and then these bit lines are connected to the selection via electrical contacts 20 and-intermediate contacts 10. The source / inverter 10 of the transistor is not shown in FIGS. 2 to 12 as just an example of a semiconductor circuit made by the method according to the present invention. Figures 1, 3, 15 and 17 depict three other conventional circuits. These circuits can also be made according to the present invention as shown in Figures 14, 16 and 18, without the need to use a stone nitride layer to protect the second. Conductive structure. Fig. 13 depicts a second embodiment of a memory cell in a memory area I, which is drawn in cross section and plane in each figure. The electrical contact 2 extends through a thick insulating layer 37 made of monoxide to the source / drain contact 1 and extends to a position where the gate electrode in the form of a spacer 2 is located slightly deeper. side. The free electrode 2 is covered by a silicon nitride layer 6a. The electrical contact 2 is connected by a bit line 4 丨, and these bit lines extend laterally with respect to the spacer word line 2 as shown in the plan view of FIG. FIG. 14 depicts an inventive forming method of this semiconductor circuit, in which the substrate is first planarized with respect to the height ′, and then intermediate contacts 1 to 0 are formed above this height, and electrical contacts 20 are formed only thereafter. As shown in the outline plan of this circuit, the intermediate contact 10 is wider than the electrical contact 20 in the lateral direction and especially covers the word line 2, which must not be short-circuited during the contact hole etching of the contact 20. A memory area of a third integrated circuit is derived from FIG. 15, and the source / drain region 1 is contacted by the contact 20. Silicon nitride thin at the top and sides

1246163, description of the invention (15) The spaced word line 2 covered by the layer 6a is positioned downward from the electrode 1 side. Fig. 16 = Bebe Example-a semiconductor circuit, which is produced by a method according to the present invention. § The self-memory region has been flattened to a certain height. At this height, only the source / drain region 1 above the vertical transistor is not covered, but not the word line or gate 2 designed as a spacer. A polycrystalline silicon layer 14 has been deposited to a high degree, and electrical contacts 20 have been applied to this polycrystalline silicon layer 1 such as ΐ1, the plan view of the memory region 1 *, and the inter-contacts 10 are from Xi Yu The stone evening layer 14 is formed in the form of interconnects, which are in contact with multiple source / non-electrode regions of the vertical transistor. The electrical contacts 20 are designed as interconnects 〇2: 2 μ 3 contacts Above, the gastric and other electrical contacts have a smaller lateral dimension and are directed upward toward the bit line 41. The embodiment shown in the figure is only an example. In particular, it is possible to make the following: Is a complementary form and the dielectric material is replaced with another material, == material, product, ^^, two materials, oxide-nitride-oxide layer sequence, or: change the dielectric constant of the L constant: eg The oxides of Shao, Wu, Zhe, Tsing, or Xun are replaced by perovskite, especially BZT. Tungsten silicon may also be used as an alternative to tungsten. Materials, titanium silicides, or cobalt silicides, which are today's materials such as cedar silicon, tungsten silicide, etc. are also suitable for manufacturing integrated semiconductor circuits made of characters. It is best to use dynamic random storage 7 (DRAMs). ° U body A well-known method for manufacturing a semiconductor circuit is self-alignment of contacts in a region and a cell array;

1246163 V. Description of the invention (16) Independent patterning procedure. The method according to the present invention only requires a single step of forming and patterning, because the intermediate contact 10, which is used as a termination pad, is made together with the contact in the logic area. That is, the same etch mask, the same etch etch chemistry and the contacts in the logic area are processed simultaneously. This greatly simplifies the fabrication of integrated semiconductors having a memory region and a logic region. According to the method of the present invention, a conventional silicidation process (self-aligned silicide) can be used and a dual working function technique is used to perform the method. 'In the navigation region, two types of dopants with different conductivity are implanted into the transistor in the logic region. Inside the gate.

Page 23 1246163 Brief description of the drawings Figure 1 shows a conventional integrated semiconductor circuit; Figures 2 to 12 show a method for manufacturing a integrated semiconductor circuit according to the present invention; Figure 13 shows a second type of conventional semiconductor circuit Design; FIG. 14 is a second design of a semiconductor circuit made by the method of the present invention; FIG. 15 is a third design of a conventional semiconductor circuit; FIG. Three designs of semiconductor circuits.

Description of component symbols: 1 first conductive structure 4 channel area 2 second conductive structure 5 lower source / drain 6 a word line protection layer 1 0 intermediate structure 1 2 first material 2 0 electrical contact 3 2 interconnection 3 3 silicide 3 7 insulating layer 4 1 interconnect DT trench 1 3 third material 3 0 transistor contact 3 3 source / in the slit region and electrode region 3 5 dielectric 3 8 bit Line BL bit line height 3 gate oxide 6 insulating layer 11 first material 1 4 conductive material 3 1 gate oxide 3 6 polycrystalline silicon layer 4 0 logic transistor PB electrode L conductive layer

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Claims (1)

1246163 Case No. 92124791 Revised: VI. Patent Application Scope 1. A method for manufacturing a semiconductor circuit with a memory region (I) and a logic region (II) on a semiconductor substrate (S), wherein the first conductive structure (1) The electrical contact (2 0) is manufactured in the memory area (I), and one of the conductive layers (L) is deposited in the logic area (II), where the second conductive structure (2) side Adjacent to the first conductive structure (1) to the ground or arranged too close to the first conductive structure (1) makes it impossible to be selectively lithographically masked relative to the first conductive structure (1), where the first A conductive structure (1) extends at least to a height (H) higher than the second conductive structure (2), and-wherein the first conductive structure (1) is prevented from contacting the second conductive structure (2) in a manner that prevents contact with the second conductive structure (2). ) Contact, wherein contact with the first conductive structure (1) is performed by the following steps:-making the integrated semiconductor circuit in the memory area (I) higher than the height (Η) of the second conductive structure (2) flat So that only the first conductive structure (1) is not covered,-also At this stage (Η), a conductive layer (L) is deposited in the memory area (I), and-耩 helps the conductive layer (L) to form an intermediate contact (1 0) on the first conductive structure (1). The width of the intermediate contact (1 0) is such that the contact holes for the electrical contact (2 0) can be aligned on the intermediate contact (1 0), and-the electrical contact (2 0) is applied to the intermediate contact Pieces (1 0). 2. The method of claim 1 in the scope of patent application, wherein the intermediate contact (1 0) is 1.2 times to 2.4 times the optical resolution limit equivalent to the exposure of the lithographic mask Page 25 1246163 _ Case No. 92124791 Year of the Bamboo ^ Month Day Amendment _ 6. The lateral dimensions (G) of the patent application form a pattern. 3. The method according to item 1 or 2 of the scope of patent application, wherein the gate (31) of the transistor is patterned by the conductive layer (L) in the logic region (II). 4. The method according to item 1 or 2 of the scope of patent application, wherein the electrical contact (20) applied to the intermediate contact (10) and the transistor contact (30) in the logic area are applied together. 5. The method of claim 1 or 2, wherein the intermediate contact (1 0) is formed by the following steps: -Forming a negative image mask (N) pattern of one of the intermediate contacts (1 0) from the conductive layer (L), and a second material (1 2) different from the material (1 1) of the conductive layer (L) ) Is applied where the intermediate contact (1 0) is to be formed,-the conductive layer (L) is selectively etched back relative to the second material (1 2), and a third material (1 3) is introduced into the first Between the areas of the two materials (1 2), and-relative to the third material (1 3), selectively etch back the second material (1 2) above the first conductive structure (1) and constitute an intermediate contact with one (1 0) instead of conductive material (1 4). 6. The method of claim 5 in which the conductive layer (L) is composed of polycrystalline silicon, and wherein the second material (1 2) is an oxide, preferably silicon oxide, and the third material (1 3) is The nitride, preferably silicon nitride, and the conductive material (1 4) is polycrystalline silicon. 7. The method of claim 1 or 2, wherein the intermediate contact (10) is formed of a conductive layer (L). 8. If you apply for the method of item 1 or 2 of the patent scope, Page 26 1246163 _ Case No. 92124791 _ Year Guangyue Yi __ VI. Patent application scope Conductive structure (1) An oxide (6) planarized together is applied to the second conductive structure (2). 9. The method of claim 1 or 2, wherein the first conductive structure (1) is a source / drain region of a vertical selection transistor (AT) of a memory cell. 10. The method according to item 1 or 2 of the patent application scope, wherein the second conductive structure (2) is a gate electrode of a vertical selection transistor (AT), which only uses a vertical gate oxide layer (3) and a source / The drain regions (1) are separated. 11. The method of claim 1 or 2, wherein the first conductive structure (1) is a bit line or a storage node. 12. An integrated semiconductor circuit comprising a memory region (I) and a logic region (II) on a semiconductor substrate (S), wherein the memory region (I) is formed by a patterned conductive layer (L) and has a thickness (S) and A conductive region (31, 3 2) having a lateral dimension at least equal to a predetermined feature size (F) is provided in the logic region (II), and wherein-the first conductive structure (1),-the second conductive structure (2 ),and -An electrical contact (2 0) which is only in contact with the first conductive structure (1) and not in contact with the second conductive structure (2) is provided in the memory area (I),-the first conductive structure (1) Extend at least to a height (Η) higher than the second conductive structure (2), and the second conductive structure (2) is laterally adjacent to the first conductive structure (1) Page 27 1246163 _ Case No. 92124791_ ^ year ~ month > Name __ VI. The scope of patent application or arrangement is too close to the first conductive structure (1) making it impossible to selectively oppose the first conductive structure ( 1) lithographic masking, wherein in the memory area (I), the height of the intermediate contact (1 0) higher than the second conductive structure (2) is applied to the first conductive structure (1), and Electrical contacts (2 0) are applied to intermediate contacts (1 0), these intermediate contacts (1 0)-the width of which enables the contact holes of the electrical contacts (2 0) to be in the intermediate contacts (1 0) Alignment, and -Its height is at most equal to the layer thickness (S) of the conductive area (31, 32) within the logic area (I). 13. For a semiconductor circuit according to item 12 of the scope of patent application, the bottom side of the intermediate contact (1 0) is arranged at a height (Η). 14. The semiconductor circuit of claim 12 or 13, wherein the second conductive structure (2) is arranged at a deeper depth than the first conductive structure (1). 15. For the semiconductor circuit of claim 12 or 13, wherein the intermediate contact (10) is composed of the same material as the conductive region (31, 32) in the logic region (II). 16. For the semiconductor circuit of claim 12 or 13, wherein the intermediate contact (10) is formed of the same conductive layer (L) as the conductive region (31, 32) in the logic region (II). 17. For a semiconductor circuit as claimed in item 12 or 13 of the patent application scope, wherein the conductive region (31, 3 2) is the gate layer (3 1) of the transistor. 18. For a semiconductor circuit with the scope of patent application No. 12 or 13 Page 28 Case No. 1246163 Amendment 6. Scope of Patent Application The conductive structure (1) is the source /; and polar region of the vertical selection transistor (AT) of the memory cell. ___ Painting hidden 1 page 29