JP3191288B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a buried multilayer wiring technique.

[0002]

2. Description of the Related Art At present, in semiconductor devices which have been highly miniaturized, in particular, in dynamic random access memories (DRAMs), a margin for superposing a gate electrode, a bit contact and a capacitance contact in a memory cell portion is increased. Therefore, a memory cell provided with a pad made of polycrystalline silicon is known. Such a memory cell DRAM
Cross-sectional views are shown in FIGS. 5 and 6, and the structure and manufacturing method of the memory cell will be described with reference to FIGS.

After an element isolation oxide film 2, a gate electrode 3, and an impurity diffusion layer 4 are formed on a substrate 1, an interlayer insulating film 7 such as a silicon oxide film (BPSG film) containing boron or phosphorus is deposited. The step of the gate electrode 3 is made flat.

Next, a cell contact 8 connected to the impurity diffusion layer 4 of the transistor of the memory cell is opened. The contact 8 can be opened in a self-aligned manner with respect to the gate electrode 3 by opening the silicon nitride film provided on the upper surface 5 and the side surface 6 of the gate electrode 3 as an etching stop layer. Further, polysilicon containing phosphorus or the like is deposited to form a contact plug 9.

On this, a silicon oxide film is deposited and patterned to form a mask 10 for processing the polysilicon pad 12 (FIG. 5A). At this time, by forming the mask side wall insulating film 11 made of the silicon oxide film on the side wall of the silicon oxide film, the polysilicon pad 12 can be enlarged, and the overlap margin with the contact can be increased.

Thereafter, as shown in FIG. 5B, using a silicon oxide film as a mask 10, polysilicon is processed to form a pad 12.

[0007] Next, as shown in FIG.
After forming an interlayer insulating film 13 such as a film, a bit contact 14 reaching the polysilicon pad 12 is opened.

Subsequently, as shown in FIG. 6D, a conductive film such as tungsten is deposited, the bit contact 14 is buried, and this is processed to form a bit line 15. When the bit line 15 is formed of a high melting point metal such as tungsten, a barrier metal such as titanium or titanium nitride may be deposited before growing tungsten.

Thereafter, the capacitor contact 16, the storage capacitor lower electrode 17, the storage capacitor upper electrode 18, the metal contact 1
9. The metal wiring 20 and the like are formed to complete the DRAM (FIG. 6E).

[0010]

As described above, by employing the structure having the connection pads, the overlay margin in the multilayer wiring was certainly improved, and a certain effect was obtained. However, as the density of the wiring has further increased, the margin for overlapping and dimension control of the upper and lower wirings in multilayer wiring has become increasingly strict.

The reason for this is that, in the case of the conventional method, FIG.
In order to connect the bit line 15 and the polysilicon pad 12 as described above, at least a fine contact 14 directly reaching the pad must be opened. For that purpose, a lithography process that ensures strict alignment accuracy is required. Also in this case, for example, as in a 1 Gbit DRAM, the overlap margin between the polysilicon pad 12 and the contact 14 is 0.02 μm.
For devices below m, overlaying and dimensional control of contacts 14 onto polysilicon pads 12 is very difficult.

In view of the above, the present invention relates to a method of manufacturing a semiconductor device in which multilayer wiring is performed via connection pads, by providing a manufacturing method for accurately and easily connecting upper and lower wirings, and a method for manufacturing a semiconductor device using this method. It is an object to provide an integrated semiconductor device.

[0013]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a semiconductor device having a structure in which an upper wiring is connected to a lower wiring or an impurity diffusion layer formed on a substrate via a connection pad. Forming a conductive film serving as a connection pad on a first interlayer insulating film on which a first contact plug connected to an impurity diffusion layer formed on a lower wiring or a substrate is formed; A mask insulating film forming step of forming a mask insulating film for processing into a connection pad on the conductive film, a connection pad forming step of forming a connection pad using the mask insulating film, and forming the mask insulating film and the connection pad. Depositing a second interlayer insulating film so as to be embedded, and etching the second interlayer insulating film until the mask insulating film is exposed; Step, depositing an etching stop film made of the same material as the mask insulating film, and depositing a third interlayer insulating film on the etching stop film according to the design thickness of the upper wiring. And etching the third interlayer insulating film until the etching stop film is exposed to form a pattern groove of an upper wiring, and selectively etching the mask insulating film and the etching stop film simultaneously. Forming a contact hole reaching the connection pad in a self-aligning manner, and forming both the contact groove reaching the connection pad and the pattern groove of the upper wiring formed in the third interlayer insulating film. A step of simultaneously forming the upper wiring and the second contact plug by filling with a conductive material; and etching the conductive material deposited on the third interlayer insulating film. The method of manufacturing a semiconductor device and a step of removing the back.

Further, the present invention relates to a method of manufacturing a semiconductor device having a structure in which an upper wiring and an impurity diffusion layer formed on a lower wiring or a substrate are connected via a connection pad. A conductive film forming step of forming a conductive film serving as a connection pad on the first interlayer insulating film having a first contact plug connected to the impurity diffusion layer formed thereon; A mask insulating film forming step of forming a mask insulating film for processing into a pad, a connection pad forming step of forming a connection pad using the mask insulating film, and a second step of burying the mask insulating film and the connection pad. Depositing an interlayer insulating film, and etching back the second interlayer insulating film until the mask insulating film is exposed. Depositing an etching stop film made of a material different from that of the mask insulating film, and depositing a third interlayer insulating film on the etching stop film in accordance with the design thickness of the upper wiring; Etching the third interlayer insulating film until the etching stop film is exposed, forming a pattern groove of the upper wiring, selectively etching the etching stop film, and then selecting the mask insulating film. Forming a contact hole reaching the connection pad in a self-aligned manner, and a contact groove reaching the connection groove and the pattern groove of the upper wiring formed in the third interlayer insulating film. A step of simultaneously forming an upper wiring and a second contact plug by filling both with a conductive material,
Removing the conductive material deposited on the third interlayer insulating film by etch-back.

Further, the present invention relates to a method for manufacturing a semiconductor device having a structure in which an upper wiring and an impurity diffusion layer formed on a lower wiring or a substrate are connected via a connection pad. A conductive film forming step of forming a conductive film serving as a connection pad on the first interlayer insulating film having a first contact plug connected to the impurity diffusion layer formed thereon; A mask insulating film forming step of forming a mask insulating film for processing into a pad, a connection pad forming step of forming a connection pad using the mask insulating film, and a second step of burying the mask insulating film and the connection pad. Depositing an interlayer insulating film, and etching back the second interlayer insulating film until the mask insulating film is exposed. Depositing an etching stop film made of a material different from that of the mask insulating film, and depositing a third interlayer insulating film on the etching stop film in accordance with the design thickness of the upper wiring; Etching the third interlayer insulating film until the etching stop film is exposed to form a pattern groove of the upper wiring; and depositing an insulating film made of the same material as the etching stop film in the pattern groove of the upper wiring. Forming a groove side wall insulating film, then exposing the mask insulating film by anisotropic etching while leaving the groove side wall insulating film, and selectively etching the mask insulating film, Forming a contact hole in a self-aligned manner, the pattern groove of the upper wiring formed in the third interlayer insulating film, and the connection Forming the upper wiring and the second contact plug simultaneously by filling both contact holes reaching the pad with a conductive material, and removing the conductive material deposited on the third interlayer insulating film by etch-back. And a method of manufacturing a semiconductor device.

Further, according to the present invention, in the method of manufacturing a semiconductor device, the mask insulating film forming step includes forming a mask insulating film on the conductive film formed in the conductive film forming step, and forming a mask insulating film on a side wall of the mask insulating film. A semiconductor device in which a step of forming a mask side wall insulating film made of a material different from a film is changed, and a step of forming a connection pad is changed to a step of forming a connection pad using the mask insulating film and the mask side wall insulating film. And a method for producing the same.

A feature of the present invention resides in a manufacturing method in which a contact hole reaches a connection pad in a self-aligned manner during etching by forming an etching stop layer around the connection pad. That is, by utilizing the etching selectivity between the hardly-etched etching stop layer formed around the connection pad and the contact hole (hereinafter referred to as the second contact hole) which becomes the second contact plug which is easily etched, Only the contact holes can be selectively etched. Using this method eliminates the need for a lithography process that ensures strict alignment accuracy, which was required in the conventional method, and makes it possible to manufacture a highly integrated semiconductor device by a simple method.

Further, the present invention relates to a semiconductor device manufactured by using the above method. As a preferable embodiment of such a semiconductor device, a MOS transistor formed on a semiconductor substrate and a first contact reaching an impurity diffusion layer through a first interlayer insulating film formed on the MOS transistor are provided. A plug, a connection pad provided in the second interlayer insulating film formed on the first interlayer insulating film and connected to the upper surface of the contact plug, and an etching formed on the second interlayer insulating film. A second contact plug penetrating the stop layer and reaching the connection pad, and an upper wiring provided in the third interlayer insulating film formed via the etching stop layer and connected to the second contact plug; Semiconductor device having the following.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the embodiments.

[Embodiment 1] FIGS. 1 and 2 are process cross-sectional views showing a manufacturing process of a DRAM according to an embodiment of the present invention. After forming an element isolation oxide film 2, a gate electrode 3, and an impurity diffusion layer 4 on a substrate 1, a first interlayer insulating film 7 such as a BPSG film is deposited to flatten a step of the gate electrode 3.

Subsequently, a cell contact 8 connected to the impurity diffusion layer 4 of the transistor of the memory cell is opened.

The contact 8 can be opened in a self-aligned manner with respect to the gate electrode 3 by opening the silicon nitride film provided on the upper surface 5 and the side surface 6 of the gate electrode 3 as an etching stop layer. it can. Further, polysilicon containing phosphorus or the like is deposited to form a first contact plug 9.

On top of this, a silicon nitride film is deposited and patterned to form a mask insulating film 21 for processing the polysilicon connection pad 12.
(FIG. 1A) At this time, by forming the mask side wall insulating film 11 made of a silicon oxide film on the side wall of the silicon nitride film, the polysilicon connection pad 12 can be enlarged.

Next, as shown in FIG. 1B, the connection pad 12 is formed by processing polysilicon using the silicon nitride film as a mask insulating film 21.

Next, as shown in FIG. 1C, a second interlayer insulating film 2 such as a BPSG film is formed on the connection pad 12.
2 is deposited and polished by chemical mechanical polishing (CMP) until the silicon nitride mask insulating film 21 is exposed.

On top of this, a thin silicon nitride film 23 of about 20 to 50 nm is deposited, and the thickness of the bit line (for example, 1
A third interlayer insulating film 24 made of a silicon oxide film having a thickness of 100 to 200 nm is formed.

In the silicon oxide film 24, for example, a groove 25 having a pattern used for a bit line is formed. (Figure 1
(D) In the etching of the pattern groove 25, the pattern groove 25 having a uniform depth can be formed by using the silicon nitride film 23 as an etching stop layer.

Subsequently, as shown in FIG. 2E, the silicon nitride film 23 exposed at the bottom of the pattern groove 25 and the silicon nitride film mask insulating film 21 used for forming the connection pad 12 are selected with heated phosphoric acid or the like. By removing it,
A contact hole 26 can be formed on polysilicon pad 12 in a self-aligned manner. Contact hole 2
6 holes do not require a new mask.

Next, the contact hole 26 and the pattern groove 25 are filled with a conductive material. As the conductive substance, for example, a metal such as tungsten is used. When a high melting point metal such as tungsten is used as the conductive material, a barrier metal (not shown) such as titanium or titanium nitride may be deposited before growing tungsten.

This conductive material is deposited as a conductive film 27. Next, the conductive film 27 is etched back by CMP or the like to fill the pattern groove 25 and the contact hole 26, and an upper wiring 28 to be a bit line, for example, is formed.
(FIG. 2 (g)) Thereafter, as shown in FIG. 2 (h), a DRAM is completed by forming a capacitor contact 16, a storage capacitor lower electrode 17, a storage capacitor upper electrode 18, a metal contact 19, a metal wiring 20, and the like. I do.

In this embodiment, the connection destination of the first contact plug is the diffusion layer of the MOS transistor.
The connection destination may be a wiring of an arbitrary layer in a semiconductor device having a multilayer structure. In this case, the manufacturing method of the present invention can be used to connect this wiring to the upper wiring formed in a layer above this wiring as a lower wiring.

[Second Embodiment] The second embodiment is characterized in that the mask insulating film and the etching stop layer are formed of films of different materials. 3 and 4 are sectional views showing the steps of manufacturing a DRAM according to an embodiment of the present invention.

The process is exactly the same as that of the first embodiment until the first contact plug 9 is formed on the MOS transistor structure.

On top of this, a silicon nitride film is deposited and patterned to form a mask insulating film 21 for processing the polysilicon connection pad 12.
(FIG. 3A) At this time, by forming the mask side wall insulating film 11 of the silicon oxide film on the side wall of the silicon nitride film, the polysilicon connection pad 12 can be enlarged.

Next, as shown in FIG. 3B, the connection pad 12 is formed by processing polysilicon using the silicon nitride film as a mask insulating film 21.

Next, as shown in FIG. 3C, a second interlayer insulating film such as a BPSG film is deposited on the connection pad 12, and the silicon nitride mask insulating film 21 is formed by CMP or the like.
Polish until exposed.

Next, the silicon nitride mask insulating film 21
A thin etching stop layer 29 of a material different from the above is deposited. As the etching stop layer 29, a material having an etching selectivity with respect to the silicon oxide film 24 and the silicon nitride film 21, for example, an insulating film such as an aluminum oxide film or a silicon oxide film containing excessive silicon is used. A third interlayer insulating film 24 made of a silicon oxide film having a thickness of the bit line (for example, 100 to 200 nm) is formed thereon. Subsequently, as shown in FIG.
Then, for example, a pattern groove 25 of a bit line pattern is formed as an upper wiring.

Since the etching of the pattern groove 25 is stopped at the etching stop layer 29, a groove having a uniform depth can be formed. Next, the etching stop layer 29 exposed at the bottom of the pattern groove 25 is selectively removed to expose the silicon nitride mask insulating film 21.

At this time, as shown in FIG. 4E, a thin insulating film of the same quality as the etching stopper layer 29 is deposited and anisotropically etched back, so that the side wall insulating film 30 is formed in the pattern groove 25. May be formed.

Next, by selectively removing the silicon nitride mask insulating film 21 exposed at the bottom of the pattern groove 25 with heated phosphoric acid or the like, a contact hole 26 is formed on the polysilicon pad 12 in a self-aligned manner. can do.

On top of this, a conductive film such as tungsten is deposited as in the first embodiment, and the trench 25 and the contact hole 26 are buried by etching back the conductive film.
A bit line 28 is formed. (FIG. 4 (g)) Thereafter, as shown in FIG. 4 (h), a DRAM is completed by forming a capacitor contact 16, a storage capacitor lower electrode 17, a storage capacitor upper electrode 18, a metal contact 19, a metal wiring 20, and the like. I do.

According to this embodiment, the etching stopper layer 29 for forming the pattern groove 25 of the bit line is made of a different material from the mask insulating film 21 for forming the polysilicon pad. When the contact hole 26 is opened, the etching stop layer 29 is not etched in the lateral direction, and the insulation reliability between the adjacent bit lines 28 is higher than in the first embodiment.

By providing the groove side wall film 30 in the bit line groove 25, the overlap margin of the bit line 28 and the capacitor contact 16 is increased.

In this embodiment, the connection destination of the first contact plug is the diffusion layer of the MOS transistor.
The connection destination may be a wiring of an arbitrary layer in a semiconductor device having a multilayer structure. In this case, the manufacturing method of the present invention can be used to connect this wiring to the upper wiring formed in a layer above this wiring as a lower wiring.

[0045]

As described in detail above, according to the present invention,
By selectively removing the silicon nitride film exposed at the bottom of the pattern groove of the upper wiring, a contact hole is formed in a polysilicon connection pad in a self-aligned manner. Therefore, there is no need for a lithography step of a bit contact requiring strict overlay accuracy and dimensional control.

Further, since the upper wiring is formed by embedding the conductive film in the groove, it is easy to use a conductive film which is difficult to finely process as the upper wiring. Such a manufacturing method is an optimum manufacturing method particularly as a method of manufacturing a DRAM requiring highly integrated multilayer wiring.

[Brief description of the drawings]

FIG. 1 is a process schematic diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic view of a process of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process schematic diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a process schematic diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a schematic process diagram of a semiconductor device for explaining a conventional example.

FIG. 6 is a schematic process diagram of a semiconductor device for explaining a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation oxide film 3 Gate electrode 4 Impurity diffusion layer 5 Silicon nitride film on a gate 6 Gate side wall silicon nitride film 7 First interlayer insulating film 8 Memory cell contact 9 Memory cell contact plug (first contact plug) 10 Mask insulating film (silicon oxide film) 11 Mask sidewall insulating film (silicon oxide film) 12 Connection pad (polysilicon pad) 13 Second interlayer insulating film 14 Bit contact 15 Bit line 16 Capacitance contact 17 Storage capacitor lower electrode 18 Storage capacitor Upper electrode 19 Metal contact 20 Metal wiring 21 Mask insulating film (silicon oxide film) 22 Second interlayer insulating film 23 Etch stop layer (Silicon nitride film) 24 Third interlayer insulating film (Silicon oxide film) 25 Pattern of upper wiring Groove 26 Second contact hole 27 Conductive film (for bit wiring) 28 Upper wiring (buried bit line) 29 Etching stop layer (aluminum oxide film) 30 Groove sidewall film (bit line sidewall film)

──────────────────────────────────────────────────の Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/768 H01L 21/8242

Claims (9)

(57) [Claims] 1. A method for manufacturing a semiconductor device having a structure in which an upper wiring and an impurity diffusion layer formed on a lower wiring or a substrate are connected via a connection pad, wherein the semiconductor device is formed on the lower wiring or the substrate. Forming a conductive film to be a connection pad on a first interlayer insulating film on which a first contact plug connected to the doped impurity diffusion layer is formed; and forming a connection pad on the conductive film Forming a mask insulating film for forming a connection pad using the mask insulating film; forming a connection pad using the mask insulating film; and forming a second interlayer insulating film so as to embed the mask insulating film and the connection pad. Depositing a film; etching back the second interlayer insulating film until the mask insulating film is exposed; Depositing an etching stop film made of the same material as the mask insulating film, depositing a third interlayer insulating film on the etching stop film in accordance with the design thickness of the upper wiring; Etching the interlayer insulating film until the etching stop film is exposed to form a pattern groove of an upper wiring; and selectively etching the mask insulating film and the etching stop film simultaneously to reach the connection pad. Forming a contact hole in a self-aligned manner, and filling both the pattern groove of the upper wiring formed in the third interlayer insulating film and the contact hole reaching the connection pad with a conductive material, Forming a wiring and a second contact plug at the same time; and removing a conductive material deposited on the third interlayer insulating film by etch-back. The method of manufacturing a semiconductor device characterized by a step. 2. The connection pad is made of polysilicon, the mask insulating film and the etching stopper film are made of a silicon nitride film, and the first, second and third interlayer insulating films are made of a silicon oxide film. The method for manufacturing a semiconductor device according to claim 1, wherein: 3. A method of manufacturing a semiconductor device having a structure in which an upper wiring and an impurity diffusion layer formed on a lower wiring or a substrate are connected via a connection pad, the method comprising the steps of: Forming a conductive film to be a connection pad on a first interlayer insulating film on which a first contact plug connected to the doped impurity diffusion layer is formed; and forming a connection pad on the conductive film Forming a mask insulating film for forming a connection pad using the mask insulating film; forming a connection pad using the mask insulating film; Depositing a film; etching back the second interlayer insulating film until the mask insulating film is exposed; Depositing an etching stop film made of a material different from that of the mask insulating film; depositing a third interlayer insulating film on the etching stop film in accordance with a design thickness of the upper wiring; Etching the interlayer insulating film until the etching stop film is exposed, forming a pattern groove of the upper wiring; selectively etching the etching stop film; and then selectively etching the mask insulating film. Forming a contact hole reaching the connection pad in a self-aligning manner, and conducting both the pattern groove of the upper wiring formed in the third interlayer insulating film and the contact hole reaching the connection pad. Simultaneously forming an upper wiring and a second contact plug by filling with a conductive material; and a conductive material deposited on the third interlayer insulating film. The method of manufacturing a semiconductor device characterized by a step of removing by etching back. 4. A method of manufacturing a semiconductor device having a structure in which an upper wiring and an impurity diffusion layer formed on a lower wiring or a substrate are connected via a connection pad, the method comprising the steps of: Forming a conductive film to be a connection pad on a first interlayer insulating film on which a first contact plug connected to the doped impurity diffusion layer is formed; and forming a connection pad on the conductive film Forming a mask insulating film for forming a connection pad using the mask insulating film; forming a connection pad using the mask insulating film; and forming a second interlayer insulating film so as to embed the mask insulating film and the connection pad. Depositing a film; etching back the second interlayer insulating film until the mask insulating film is exposed; Depositing an etching stop film made of a material different from that of the mask insulating film; depositing a third interlayer insulating film on the etching stop film in accordance with a design thickness of the upper wiring; Etching the interlayer insulating film until the etching stop film is exposed to form a pattern groove of the upper wiring; and depositing an insulating film made of the same material as the etching stop film in the pattern groove of the upper wiring, and forming a groove side wall. A step of forming an insulating film, and then anisotropic etching to leave a groove side wall insulating film;
Exposing the mask insulating film; selectively etching the mask insulating film to form a self-aligned contact hole reaching the connection pad; and forming the contact hole in the third interlayer insulating film. A step of filling both the pattern groove of the upper wiring and the contact hole reaching the connection pad with a conductive material to simultaneously form an upper wiring and a second contact plug; and Removing the deposited conductive material by etch-back. 5. The method according to claim 1, wherein said connection pad is made of polysilicon, said mask insulating film is made of a silicon nitride film, said first, second and third interlayer insulating films are made of a silicon oxide film, and etching is stopped. The film is made of an aluminum oxide film.
13. The method for manufacturing a semiconductor device according to item 5. 6. The connection pad is made of polysilicon, the mask insulating film is made of a silicon nitride film, the first, second and third interlayer insulating films are made of a silicon oxide film, and etching is stopped. 5. The method according to claim 3, wherein the film is made of a silicon oxide film containing excessive silicon. 7. The method for manufacturing a semiconductor device according to claim 1, wherein a diameter of a contact hole reaching said connection pad is smaller than a size of said connection pad. 8. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming a mask insulating film, a mask insulating film is formed on the conductive film formed in the conductive film forming step. A step of forming a mask side wall insulating film made of a material different from the mask insulating film on the side wall of the insulating film is changed, and a connection pad forming step is performed by forming a connection pad using the mask insulating film and the mask side wall insulating film. A method of manufacturing a semiconductor device, wherein the method comprises: 9. The method according to claim 8, wherein the mask sidewall insulating film is made of a silicon oxide film.