KR20010044903A - Method for preventing a step coverage between cell region and core/periphery region - Google Patents

Abstract

PURPOSE: A method is provided to improve step coverage of a cell region and a core/peripheral region, by simultaneously forming a capacitor and a metal contact in the cell region and the core/peripheral region, respectively. CONSTITUTION: A cell region and a core/peripheral region are defined in a semiconductor substrate. A gate electrode(214) and a bit line(222) are sequentially formed on the semiconductor substrate. A buried contact(BC) is formed in the cell region while a metal contact is formed in the core/peripheral region. A lower electrode of a capacitor is formed in the cell region while the first metal interconnection is formed in the core/peripheral region. A dielectric layer(236) and an upper electrode(238) of the capacitor are formed in the cell region. The second metal interconnection(248) is formed in the cell region and in the core/peripheral region, and is connected to the upper electrode and the first metal interconnection.

Description

METHOD FOR PREVENTING A STEP COVERAGE BETWEEN CELL REGION AND CORE / PERIPHERY REGION}

The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for preventing a step between a cell region and a core / peripheral region.

Semiconductor memory devices are becoming increasingly integrated and high capacity. Accordingly, as the design rules decrease and fine patterns are formed, the area occupied by the cells and the devices becomes smaller. In DRAM (Dynamic Random Access Memory), a cell is composed of one transistor and one capacitor. Thus, the reduction of cells involves the reduction of transistors and capacitors. However, if the transistor is too small, a problem occurs due to a decrease in channel length, and if the capacitor is too small, a problem arises in that a reduction in capacitance is caused by a decrease in electrode area. Since DRAM accumulates charges in capacitors, it stores information. Soft errors caused by alpha particles and coupling noise between the wires cause loss of stored charges. Thus, the capacitance must be maintained at least about 25 fF or more per cell to preserve information even when charge is lost.

As semiconductors become more integrated, various methods have been studied for producing capacitors having the same capacitance in a cell cross-sectional area that becomes smaller. Since the capacitance is proportional to the surface area of the electrode and the dielectric constant of the dielectric between the electrodes, the development of a dielectric having a high dielectric constant and various structures for increasing the surface area has been made.

In order to maintain the same capacitance in a small area by using a dielectric having a high dielectric constant, a dielectric such as TaO or alumina may be used while using a conventional structure of NO-Oxide (NO) or Oxide-Nitride-Oxide (ONO). Research to use is in progress and used. Recently, methods using dielectrics such as BST, PZT, and PLZT, which have high dielectric constants, have been studied and are reaching the application stage.

As a method of increasing the surface area of the electrode, a trench structure or a stack structure is used to change the shape of the electrode to increase the surface area of the electrode. The most commonly applied structure at this point is a cylindrical stack structure. The cylindrical stack structure forms an opening in the sacrificial oxide film, deposits a conductive film for the lower electrode of the capacitor on the inner wall of the opening, and then removes the sacrificial oxide film. Next, a capacitor is formed by depositing a dielectric film and a conductive film for the upper electrode. However, cylindrical cylinders must have deep openings to increase their area. Therefore, there is a disadvantage in that the height of the formed capacitor is gradually increased.

As the degree of integration becomes more than 1 Giga bit, the height of the capacitor is inevitably increased as the minimum line width decreases. This increase in height increases the level of difference between the cell area and the core / peripheral region within the wafer, adding to the difficulty in the photographic process of forming subsequent metal contacts and metal interconnects. In particular, in the case of a device using a multilayer metal while forming a capacitor such as MML (Memory Merged Login) and MDL, the problem of step difference between the cell area where the capacitor is formed and the core / peripheral area where the logic circuit is formed is more serious. Is emerging.

1 is a cross-sectional view illustrating a step in which a step is formed between a conventional cell region and a core / peripheral region.

Referring to FIG. 1, a cell region X and a core / peripheral region Y are defined on a semiconductor substrate 110. The gate electrode 112 is formed on the semiconductor substrate 110. The bit line 114 and the first interlayer insulating layer 116 are formed on the gate electrode 112. Since the first interlayer insulating layer 116 of the cell region X is filled with a conductive material, a buried contact (BC) contact plug 118 is formed. A capacitor including a lower electrode 120, a dielectric film 122, and an upper electrode 124 is formed on the BC contact plug 118. A second interlayer insulating layer 126 is deposited on the entire surface of the substrate 110. As shown in FIG. 1, since the capacitor formed in the cell region X is formed high, a high step is formed between the cell region X and the core / peripheral region Y. This step makes it difficult to align the photo process for the subsequent metal wiring process and the metal contact process.

It is an object of the present invention to provide a method for preventing a step between a cell area and a core / peripheral area that can reduce a step occurring between a cell area where a capacitor is formed and a core / peripheral area without a capacitor.

1 is a cross-sectional view showing a step formed between the conventional cell region and the core / peripheral region; And

2A through 2F are cross-sectional views sequentially illustrating a method for preventing a step between a cell region and a core / peripheral region according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

210: semiconductor substrate 212: device isolation film

214: gate electrode 220: first interlayer insulating film

222: bit line 226: second interlayer insulating film

228a: BC contact plug 228b: MC contact plug

230: third interlayer insulating film 234a: capacitor lower electrode

234b: first metal wiring 236: fourth interlayer insulating film

238 dielectric layer 240 capacitor upper electrode

242: fifth interlayer insulating film 244: sixth interlayer insulating film

246: Via 248: Second Metal Wiring

According to the present invention for achieving the above object, a step preventing method between the cell region and the core / peripheral region forms a gate electrode and a bit line in turn on the semiconductor substrate defined by the cell region and the core / peripheral region. A metal contact is simultaneously formed in BC and the core / peripheral region in the cell region. A first metal wire is simultaneously formed in the lower electrode and the core / peripheral region of the capacitor in the cell region. An upper electrode of the dielectric film and the capacitor is formed in the cell region. A second metal wiring is formed in the cell region and the core / peripheral region and connected to the upper electrode and the first metal wiring.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2F.

The novel step preventing method between the cell area and the core / peripheral area of the present invention forms a capacitor in the cell area and simultaneously forms a metal wiring in the core / peripheral area, thereby reducing the step difference.

2A to 2F are cross-sectional views illustrating a step preventing method between a cell region and a core / peripheral region according to an exemplary embodiment of the present invention.

In the drawings, X is a cross-sectional view of the X-axis cell region of the semiconductor substrate, and Y is a cross-sectional view of the Y-axis core / peripheral region of the semiconductor substrate.

Referring to FIG. 2A, an isolation layer 212 is formed on the semiconductor substrate 210 to define an active region and an inactive region. The first conductive layer 214 is deposited on the substrate 210 and then etched to form a gate electrode 214. After the first silicon nitride layer 216 is deposited on the entire surface of the substrate 210, a gate spacer 216 is formed on the gate electrode 214 through an etch back process. Polysilicon is filled between the gate spacers 216 to form a landing pad 218. The first interlayer insulating layer 220 is deposited on the entire surface of the substrate 210. The first interlayer insulating layer 220 is formed of O ₃ -TEOS USG (Undoped Silica Glass) by an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method.

2B, since one region of the first interlayer insulating layer 220 is etched, the landing pad 218 is exposed to form a contact hole. The second conductive layer 222 is deposited on the first interlayer insulating layer 220 and then etched to form a bit line 222. In this case, a second conductive layer 222 is filled in the contact hole to form a direct contact (DC) between the bit line 222 and the landing pad 218. After the second silicon nitride layer 224 is deposited on the entire surface of the substrate 210, a bit line spacer 224 is formed on the bit line 222 through an etch back process.

Referring to FIG. 2C, a second interlayer insulating layer 226 is deposited on the entire surface of the substrate 210. The second interlayer insulating film 226 is formed of BPSG (Boron Phosphorus Silica Glass) by the APCVD method. By using the bit line spacer 224 as a self-aligned contact in the cell region X, the second and first interlayer insulating layers 226 and 220 are etched until the source / drain is exposed, thereby forming a BC (Buried Contact). Contact holes are formed. At the same time, a contact hole is formed in the core / peripheral region Y to expose the source / drain region, the bit line 222 and the landing pad 218. The contact holes of the cell region X and the core / peripheral region Y are filled with a third conductive layer to form contact plugs 228a and 228b. The contact plug of the cell region X is connected to the lower electrode of the subsequent capacitor to form BC 228a, and the contact plug of the core / peripheral region Y is connected to the metal film so that MC (Metal Contact) 228b is formed. Is formed. A third silicon nitride film 230 is deposited on the second interlayer insulating film 226. A third interlayer insulating film 232 is deposited on the third silicon nitride film 230. The third interlayer insulating layer 232 is made of BPSG, USG, SiO _2, or the like as a sacrificial oxide layer.

Referring to FIG. 2D, an opening is formed on the third interlayer insulating layer 232 to form the opening of the BC contact plug 228a of the cell region X and the MC contact plug of the core / peripheral region Y. 228b) is exposed. A first metal film 234 is deposited on the entire surface of the substrate 210 so that the opening is filled with the first metal film 234. The first metal film 234 is formed of Ti, TiN, Pt, or the like. Since the first metal layer is planarized and etched until the third interlayer insulating layer 232 is exposed, the first metal interconnection 234b is disposed in the cell region X and the lower electrode 234a of the capacitor and the core / peripheral region Y. This is formed at the same time. The planarization etching is performed through a chemical mechanical polishing (CMP) or etch back process. As a result, the capacitor lower electrode 234a and the first metal wire 234b are formed at the same height. A fourth interlayer insulating film 236 is deposited on the entire surface of the substrate 210. The fourth interlayer insulating film 236 is formed of BPSG, USG, SiO _2, or the like.

Referring to FIG. 2E, a photoresist film (not shown) is deposited on the fourth interlayer insulating film 236. Since only the cell region X is exposed and developed on the photoresist film, only the cell region X is exposed. The fourth interlayer insulating layer 236 and the third interlayer insulating layer 232 of the cell region X are etched using the photoresist layer as a mask. As a result, the capacitor lower electrode 234a of the cell region X is exposed. The dielectric film 238 is deposited on the entire surface of the substrate 210, and the second metal film is deposited to form the capacitor upper electrode 240. The second metal film 240 is formed of Ti, TiN, Pt, or the like. A fifth interlayer insulating layer 242 is deposited on the entire surface of the substrate 210. The fifth interlayer insulating film 242 is formed of BPSG by APCVD or HDP oxide by HDP (High Density Plasma).

Referring to FIG. 2F, the fifth interlayer insulating film, the second metal film, and the dielectric films 242, 240, and 238 planarize etching until the fourth interlayer insulating film 236 of the core / peripheral region Y is exposed. do. The planarization etching is performed through chemical mechanical polishing or etch back process. As a result, the second metal film 240 and the dielectric film 238 in the core / peripheral region Y are removed, and a part of the fifth interlayer insulating film 242 remains in the cell region X, leaving the second metal film ( The upper electrode 240 of the capacitor formed of 240 is protected. A sixth interlayer insulating layer 244 is deposited on the entire surface of the substrate 210. The sixth interlayer insulating layer 244 is etched to expose the capacitor upper electrode 240 of the cell region X and the first metal interconnection 234b of the core / peripheral region Y so that a via hole is formed. Is formed. The via hole is filled with a fourth conductive layer to form a via 246. A third metal film is deposited on the entire surface of the substrate 210 to form a second metal wire 248. The third metal film 248 is formed of Ti, TiN, W, WSi _x , Al, or the like. The second metal wire 248 is connected to the capacitor upper electrode 240 of the cell region X and the first metal wire 234b of the core / peripheral region Y through the via 246. Since the metal contact and the wiring process are performed at the same time as the capacitor formation process, the photo process, which is conventionally added by separately performing the metal contact process after the capacitor formation, is reduced.

According to the present invention, since the capacitor of the cell region and the metal contact of the core / peripheral region are formed at the same time, there is an effect of eliminating the step difference between the regions.

In addition, the present invention has the effect of reducing two photographic processes.

In addition, there is an effect that can increase the misalignment margin of the metal contact.

Claims (3)

Sequentially forming a gate electrode 214 and a bit line 222 on a semiconductor substrate defined by a cell region X and a core / peripheral region Y; Simultaneously forming a BC 226a in the cell region X and a metal contact 226b in the core / peripheral region Y; Simultaneously forming a first metal wire (230b) in the lower electrode (230a) and the core / peripheral region (Y) of the capacitor in the cell region (X); Forming a dielectric film (236) and an upper electrode (238) of a capacitor in the cell region (X); And Forming a second metal wiring 248 in the cell region X and the core / peripheral region Y and connecting the second metal wiring 248 to the upper electrode 238 and the first metal wiring 232b. How to prevent step difference between / surrounding areas. The method of claim 1, And the lower electrode (232a) and the upper electrode (238) of the capacitor are formed of a metal and the step difference between the core region and the core / peripheral region. The method of claim 1, The dielectric film 236 is a step prevention method between the cell region and the core / peripheral region is formed of one selected from NO, ONO, TaO, BST and PZT.