CN102394216B

CN102394216B - Metal-oxide-metal capacitor manufacturing method

Info

Publication number: CN102394216B
Application number: CN 201110392608
Authority: CN
Inventors: 毛智彪; 胡友存; 徐强
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-11-30
Filing date: 2011-11-30
Publication date: 2013-12-18
Anticipated expiration: 2031-11-30
Also published as: CN102394216A

Abstract

The invention introduces a metal-oxide-metal (MOM) capacitor manufacturing method. A mixing layer of low-K media and high-K silicon oxide is formed, a metal groove is formed in the low-K media and high-K silicon oxide by utilizing traditional photoetching process, metal is filled in the metal groove, a high-performance MOM capacitor structure is realized in a high-K material silicon oxide area, and the mutual connection of the low-K media in other areas is realized. The way of PECVD (Plasma Enhanced Chemical Vapor Deposition) and oxygen containing gas treatment circulation is adopted for forming the high-K silicon oxide, and silicon hydrogen bond in the silicon oxide can be effectively removed. Compared with a traditional single-K medium structure, the MOM capacitor manufacturing method can effectively improve the capacitance of an inner capacitor, and can improve various characteristics such as breakdown voltage, current leakage, and the like of the MOM capacitor, and the electrical uniformity of all devices.

Description

A kind of manufacture method of metal-oxide-metal capacitor

Technical field

The present invention relates to microelectronic, particularly relate to a kind of manufacture method of metal-oxide-metal capacitor.

Background technology

Capacitor is electronic devices and components commonly used in integrated circuit, is also the important composition unit of integrated circuit, and it can be widely used in memory, microwave, and radio frequency, smart card, in the chips such as high pressure and filtering.At present, the capacitor widely adopted in chip is metal-insulator-metal type (MIM) capacitor that is parallel to silicon chip substrate.Wherein metal usually adopts and metal interconnected the technique copper, aluminium etc. of compatibility mutually, insulator mostly is dielectric substance silica or the silicon nitride of high-k (k), plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition be widely used in metal interconnected technique of its depositing temperature.The silica or the interior residual a large amount of si-h bond (Si-H) of silicon nitride film that utilize the PECVD method to make, make in it to exist more electric charge, this causes this silica or the silicon nitride film uniformity aspect electrical thickness poor, and the MIM capacitor of utilizing this silica or silicon nitride film to make also can be corresponding poor aspect each electrical characteristics such as puncture voltage, leakage current.

In addition, along with improving constantly of very lagre scale integrated circuit (VLSIC) integrated level, the continuous scaled down of device feature size, the capacitor sizes of making in circuit is corresponding dwindling also, the uniformity that electric capacity is manufactured, coherence request is more strict.And along with the minimizing of device size, and performance is to the demand of large electric capacity, how under limited area, obtaining highdensity electric capacity also becomes an attractive problem.

The Chinese patent that publication number is CN101577227A discloses a kind of method of improving aluminium-silicon nitride-tantalum compound capacitor performance, process silicon nitride film by oxygen-containing gas, the quantity of electric charge in the silicon nitride film formed is less, the electrical thickness of silicon nitride film and the uniformity of physical thickness have been improved, the MIM electric capacity that adopts the method to form is in puncture voltage, each electrical characteristics aspect such as leakage current makes moderate progress, but does not obtain highdensity electric capacity.Therefore, how under limited area, to obtain highdensity electric capacity and be still urgent problem in present technical development.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of formation method of metal-oxide-metal capacitor, to obtain highdensity electric capacity under limited area, and can effectively improve the electric capacity of layer inner capacitor, improve each electrical characteristics such as puncture voltage, leakage current of metal-oxide-metal (MOM) capacitor and the electricity uniformity between each device thereof.

For addressing the above problem, the invention provides a kind of manufacture method of metal-oxide-metal capacitor, said method comprising the steps of:

Substrate is provided;

The low k value dielectric layer of deposition on substrate;

Process by plasma enhanced chemical vapor deposition and oxygen-containing gas the mode that two steps circulate and form silica on low k value dielectric layer;

Remove a part of silica on low k value dielectric layer by photoetching and etching, the silica retained is for follow-up formation metal-oxide-metal capacitor;

At the low k value dielectric layer of said structure surface deposition;

Utilize cmp to remove the unnecessary low k value dielectric layer of silicon oxide surface top;

By photoetching be etched in low k value dielectric layer and silica and form respectively metallic channel;

Fill metal in metallic channel.

Preferably, the reacting gas that described plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.

Preferably, the flow of described silane is between 500sccm to 600sccm, the flow of described nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.

Preferably, the oxygen-containing gas that described oxygen-containing gas processing adopts comprises nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.

Preferably, the oxygen-containing gas flow that described oxygen-containing gas processing adopts is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.

Preferably, the described mode of processing two steps circulations by plasma enhanced chemical vapor deposition and oxygen-containing gas forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.

The present invention hangs down the mixed layer of k value medium and high k value silica by formation, then carry out the photoetching etching of traditional handicraft, in high k value region of silicon oxide, realizes the MOM structure, realizes low k value interconnection in other zones; Well improve the electric capacity in the capacitor unit are, improved capacitor density, also further improved the performance of MOM capacitor, thereby met the requirement of constantly microminiaturized chip to high performance capacitors.

The accompanying drawing explanation

Fig. 1 is the method flow diagram that the embodiment of the present invention forms MOM electric capacity;

Fig. 2 A～2F is the method schematic diagram that the embodiment of the present invention forms MOM electric capacity.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

The present invention proposes the process of a kind of making metal-oxide-metal (MOM) capacitor.Please refer to Fig. 1, for the present invention prepares the flow chart of MOM capacitor formation method.

Step 201: substrate 1 is provided; The substrate 1 provided in the present embodiment can be simple silicon substrate, also can form for surface the silicon substrate of semiconductor device.

Step 202: as shown in Figure 2 A, the low k value dielectric layer 2 of deposition on substrate 1.Described low k value dielectric layer 2 adopts chemical vapor deposition or spin coating process to form, and dielectric constant is 2～3.

Step 203: as shown in Fig. 2 B, the oxide of the high k value of deposition on low k value dielectric layer 2, preferably adopt silica 3 in the present invention.In order to improve silica 3 films that conventional P ECVD method makes in the uniformity aspect electrical thickness, the mode that adopts PECVD method cvd silicon oxide and oxygen-containing gas cycle for the treatment of to carry out in the present invention, after depositing one deck silica 3, carry out subsequently the oxygen-containing gas processing, and then cvd silicon oxide 3, carry out again the oxygen-containing gas processing, so circulation; The silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer, till the silica of deposition reaches the thickness needed in technique.Wherein, the reacting gas that PECVD adopts is silane and nitrous oxide, the flow that the process conditions of reaction are silane is between 500sccm to 600sccm, the flow of nitrous oxide is between 9000sccm to 15000sccm, the flow-rate ratio of silane and nitrous oxide is between 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute; Oxygen-containing gas is processed the oxygen-containing gas adopted and is comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide, and the flow of oxygen-containing gas is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees centigrade.And then silica by the deposition skim also carries out the oxygen-containing gas processing to it, can remove fully the si-h bond Si-H in silicon oxide film, and so circulation, can obtain the silica that electrical thickness evenness is good.

Step 204: as shown in Figure 2 C, by photoetching and etching, remove a part of silica on low k value dielectric layer, the silica retained is for follow-up formation metal-oxide-metal capacitor.

Step 205: as shown in Figure 2 D, again deposit low k value dielectric layer 2 on the said structure surface.

Step 206: utilize cmp to remove the unnecessary low k value medium 2 in silica 3 surfaces, form the mixed layer of low k value medium and silica.

Step 207: as shown in Figure 2 E, in low k value dielectric layer 2 and silica 3, form respectively

metallic channel

4a, 4b, wherein, the metallic channel 4a in low k value dielectric layer 2 is used to form interconnection, and the metallic channel 4b in silica 3 is for follow-up formation capacitor plate.Metallic channel 4b in silica 3 can evenly offer a plurality of, and the degree of depth of metallic channel 4b equals the degree of depth of silica 3, and the bottom-exposed of metallic channel 4b goes out to hang down k value dielectric layer 2.

Step 208: as shown in Figure 2 F, fill metal 5 in metallic channel, carry out the processing steps such as diffusion impervious layer deposition, copper plating, copper metal layer cmp of the copper of copper wiring technique in the metallic channel in low k value medium 2 and silica 3, complete the making of copper-connection and MOM capacitor.

The present invention, when utilizing schematic diagram that the embodiment of the present invention is described in detail in detail, for convenience of explanation, means that the profile of device architecture is disobeyed local amplification of general ratio work, should not using this as limitation of the invention.In addition, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.

Claims

1. the manufacture method of a metal-oxide-metal capacitor, is characterized in that, comprises the following steps:

Substrate is provided;

The low k value dielectric layer of deposition on substrate;

At the low k value dielectric layer of said structure surface deposition;

By photoetching be etched in low k value dielectric layer and silica and form respectively metallic channel, the metallic channel in low k value dielectric layer is used to form interconnection, and a plurality of metallic channels in silica are used for follow-up formation capacitor plate;

Fill metal in metallic channel.

2. the manufacture method of metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, the reacting gas that described plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.

3. the manufacture method of metal-oxide-metal capacitor as claimed in claim 2, it is characterized in that, the flow of described silane is between 500sccm to 600sccm, the flow of described nitrous oxide is between 9000sccm to 15000sccm, the flow-rate ratio of silane and nitrous oxide is 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.

4. the manufacture method of metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, described oxygen-containing gas is processed the oxygen-containing gas adopted and comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.

5. the manufacture method of metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, the oxygen-containing gas flow that described oxygen-containing gas processing adopts is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.

6. the manufacture method of metal-oxide-metal capacitor as claimed in claim 1, it is characterized in that, the described mode of processing two steps circulations by plasma enhanced chemical vapor deposition and oxygen-containing gas forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.