CN102779733A - Manufacturing method of metal-silicon oxide-metal capacitor - Google Patents

Manufacturing method of metal-silicon oxide-metal capacitor Download PDF

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Publication number
CN102779733A
CN102779733A CN2012102930716A CN201210293071A CN102779733A CN 102779733 A CN102779733 A CN 102779733A CN 2012102930716 A CN2012102930716 A CN 2012102930716A CN 201210293071 A CN201210293071 A CN 201210293071A CN 102779733 A CN102779733 A CN 102779733A
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metal
capacitor
low
silica
oxide
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CN2012102930716A
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毛智彪
周军
张月雨
王丹
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

The invention discloses a manufacturing method of metal-silicon oxide-metal capacitor. The manufacturing method comprises the steps of: firstly forming a mixing layer of a low-k-value medium and a high-k-value silicon oxide; conducting photoetching of a convention process to form a metallic channel and a capacitance metallic channel connected with each other in the low-k-value medium and high-k-value silicon oxide respectively, and filling metal in the channels so as to realize a high-performance MOM (Mass Optical Memory) capacitor structure in the region of the high-k-value silicon oxide and realize the interconnection of low k values in other regions, wherein the high-k-value silicon oxide is formed by adopting the mode of PECVD (Plasma Enhanced Chemical Vapor Deposition) and nitrogen-contained gas cyclic processing, and silicon-hydrogen bonds in silicon oxide can be removed effectively. Compared with a conventional single-k value medium structure, the manufacturing method provided by the invention has the advantages that the capacitance of a capacitor in a high layer can be improved effectively, the electrical characteristics of breakdown voltage, leakage current and the like of an MOM capacitor are improved, and the electricity uniformity of all the devices is improved.

Description

The manufacture method of metal-oxide silicon-metal capacitor
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of manufacture method of metal-oxide silicon-metal capacitor.
Background technology
Capacitor is the important composition unit in the integrated circuit, extensively applies in the chips such as memory, microwave, radio frequency, smart card, high pressure and filtering.The capacitor constructions that in chip, widely adopts is metal-insulator-metal type (MIM, Metal-Insulator-Metal) capacitor that is parallel to silicon chip substrate.Wherein metal is that manufacture craft is prone to the copper compatible mutually with metal interconnected technology, aluminium etc., and insulator then is the dielectric substance of high-ks (k) such as silicon nitride, silica.The performance of improving the high-k dielectric material is one of main method that improves capacitor performance.
Plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition that is widely used in the metal interconnected technology of its depositing temperature.Utilize residual a large amount of si-h bond (Si-H) in the silicon nitride film that the PECVD method makes; Make and have more electric charge in it; This causes the uniformity of this silicon nitride film aspect electrical thickness relatively poor, and the MIM capacitor that utilizes this silicon nitride film to make also can be corresponding relatively poor aspect each electrical characteristics such as puncture voltage, leakage current.Chinese patent CN101577227A has introduced a kind of method of improving aluminium-silicon nitride-tantalum thing capacitor performance; Handle this silicon nitride film through oxygen-containing gas; Can reduce si-h bond residual in the silicon nitride film effectively, thereby improve the performance of capacitor effectively.
Yet along with the continuous progress of semiconductor integrated circuit manufacturing technology, performance also is accompanied by device miniaturization, microminiaturized process when constantly promoting.More and more advanced processing procedure requires in as far as possible little zone, to realize device as much as possible, obtains high as far as possible performance.Therefore, how under limited area, to obtain highdensity electric capacity and become a problem that haves a great attraction.And do not obtain highdensity electric capacity among the above-mentioned Chinese patent CN101577227A.
(MOM, Metal-Oxide-Metal) capacitor is owing to realizing in less chip area that big electric capacity becomes the focus of present research perpendicular to the metal-oxide-metal of silicon chip substrate.Oxide wherein is generally silica, but in practical application, also can comprise the dielectric substance of high-ks (k) such as silicon nitride.MOM capacitor fabrication technology and metal interconnected technology compatible relatively good, the outer company of capacitor two-stage can realize with metal interconnected technology synchronously.But, utilize PECVD to make silicon oxide film and also have a large amount of si-h bond (Si-H) and remain in the silicon oxide film, thereby influence the performance of MOM capacitor.
Chinese patent CN111654.1 has introduced a kind of process of the MOM of making capacitor.Silica wherein adopts traditional P ECVD technology to make.A large amount of si-h bond (Si-H) remains in the silicon oxide film.Though the silica that this manufacture method is made conventional P ECVD technology has carried out the oxygen-containing gas processing, to reduce residual si-h bond in the silicon oxide film.Yet still residual in the silicon oxide film of this method preparation have a large amount of si-h bond (Si-H), can not satisfy the demand of high-performance MOM capacitor.
Therefore, be necessary further to improve the performance and the performance that improves the MOM capacitor of high-k dielectric material, thereby satisfy of the requirement of constantly microminiaturized chip high performance capacitors.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of metal-oxide silicon-metal capacitor, to improve the performance of MOM capacitor.
For addressing the above problem, the present invention proposes a kind of manufacture method of metal-oxide silicon-metal capacitor, comprises the steps:
Substrate is provided;
The low K value dielectric layer of deposition on said substrate;
The mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silica on said low K value dielectric layer;
Said silica is carried out photoetching and etching, remove the silica outside the MOM capacitor regions;
At the said low K value dielectric layer of body structure surface deposition of having removed partial oxidation silicon, and utilize cmp to remove the unnecessary low k value dielectric layer of silicon oxide surface top, form the mixed layer of low k value dielectric layer and silica;
Said low K value dielectric layer and said silica are carried out photoetching and etching, in said low K value dielectric layer and said silica, form interconnecting metal groove and electric capacity metallic channel respectively;
In said interconnecting metal groove and electric capacity metallic channel, fill metal.
Optional, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
Optional; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between the 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
Optional, said nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen.And be preferably nitrogen.
Optional, the nitrogenous gas flow that said nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
Optional, said mode through plasma reinforced chemical vapour deposition and nitrogenous gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
Compared with prior art, the present invention is through forming the mixed layer of low k value medium and high k value silica earlier; Then carry out the photoetching etching of traditional handicraft, in low k value medium and high k value silica, form interconnecting metal groove and electric capacity metallic channel respectively, and in groove, fill metal; Thereby in high K value silica, realized high-performance MOM capacitor arrangement, realized low k value interconnection in other zones.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.
Description of drawings
Fig. 1 forms the method flow diagram of MOM electric capacity for the embodiment of the invention;
Fig. 2 A～Fig. 2 F is the corresponding device architecture sketch map of each step of the method for embodiment of the invention formation MOM electric capacity.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacture method of the metal-oxide silicon-metal capacitor of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of manufacture method of metal-oxide silicon-metal capacitor is provided, and this method is through forming the mixed layer of low k value medium and high k value silica earlier; Then carry out the photoetching etching of traditional handicraft, in low k value medium and high k value silica, form interconnecting metal groove and electric capacity metallic channel respectively, and in groove, fill metal; Thereby in high K value silica, realized high-performance MOM capacitor arrangement, realized low k value interconnection in other zones.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.
Please refer to Fig. 1 and Fig. 2 A to Fig. 2 F; Wherein, Fig. 1 is the method flow diagram of embodiment of the invention formation MOM electric capacity, and Fig. 2 A～Fig. 2 F is the corresponding device architecture sketch map of each step of the method for embodiment of the invention formation MOM electric capacity, in conjunction with Fig. 1 and Fig. 2 A to Fig. 2 F; The manufacture method of metal-oxide silicon-metal capacitor provided by the invention comprises the steps:
Step 1: substrate 101 is provided; The substrate 101 that is provided in the present embodiment can be simple silicon substrate, also can form the silicon substrate of semiconductor device for the surface;
Step 2, the low K value dielectric layer 102 of deposition on said substrate 101 is shown in Fig. 2 A; Said low k value dielectric layer 102 adopts chemical vapour deposition (CVD) to form, and dielectric constant is 2～3; Certainly, said low k value dielectric layer 102 can also form through spin coating process.
Step 3, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silica 103 on said low K value dielectric layer 102, shown in Fig. 2 B; In order to improve silicon oxide film that conventional P ECVD method makes in the uniformity aspect the electrical thickness; The mode that adopts PECVD method cvd silicon oxide and nitrogenous gas cycle of treatment to carry out among the present invention; After promptly depositing one deck silica, carry out nitrogenous gas subsequently and handle, and then cvd silicon oxide; Carry out nitrogenous gas again and handle, so circulation; The silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer, until the silica 103 of deposition reaches till the thickness that needs in the technology.
Wherein, The reacting gas that PECVD adopts comprises silane and nitrous oxide; The process conditions of reaction are that the flow of silane is between 500sccm to 600sccm; The flow of nitrous oxide between 9000sccm to 15000sccm, the flow-rate ratio of silane and nitrous oxide be 1: 15 between the 1:30, rate of film build is between 1500 nm/minute to 5000 nm/minute; Nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen; And be preferably nitrogen; The nitrogenous gas flow that the nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
And then silica through the deposition skim also carries out the nitrogenous gas processing to it, can remove the si-h bond Si-H in the silicon oxide film fully, and so circulation can obtain the good silica of electrical thickness evenness.
Step 4 is carried out photoetching and etching to said silica 103, removes the silica outside the MOM capacitor regions; Removed device architecture figure behind the partial oxidation silicon shown in Fig. 2 C;
Step 5; At the said low K value dielectric layer of body structure surface deposition of having removed partial oxidation silicon; And utilize cmp to remove the unnecessary low k value dielectric layer of silica 103 surfaces, form the mixed layer of low k value dielectric layer 102 and silica 103, shown in Fig. 2 D;
Step 6 is carried out photoetching and etching to said low K value dielectric layer 102 and said silica 103, in said low K value dielectric layer 102 and said silica 103, forms interconnecting metal groove 200 and electric capacity metallic channel 300 respectively, shown in Fig. 2 E; Wherein, electric capacity metallic channel 300 is used for the capacitor plate of follow-up formation MOM electric capacity; Electric capacity metallic channel 300 can evenly be offered a plurality of, and the degree of depth of electric capacity metallic channel 300 equals the thickness of silica, and promptly the bottom-exposed of electric capacity metallic channel 300 goes out to hang down K value dielectric layer 102.Interconnecting metal groove 200 is used for follow-up formation interconnection, and its degree of depth can be identical with electric capacity metallic channel 300, also can adjust number, size, the degree of depth of interconnecting metal groove 200 according to the actual process demand.
Step 7 is filled metal in said interconnecting metal groove 200 and electric capacity metallic channel 300; Device architecture after this step is accomplished is shown in Fig. 2 F; Particularly, this step is included in processing steps such as the diffusion impervious layer deposition, copper plating, copper metal layer cmp of the copper that carries out copper wiring technique in interconnecting metal groove 200 and the electric capacity metallic channel 300, accomplishes copper and fills.
In sum, the invention provides a kind of manufacture method of metal-oxide silicon-metal capacitor, this method is through forming the mixed layer of low k value medium and high k value silica earlier; Then carry out the photoetching etching of traditional handicraft, in low k value medium and high k value silica, form interconnecting metal groove and electric capacity metallic channel respectively, and in groove, fill metal; Thereby in high K value silica, realized high-performance MOM capacitor arrangement, realized low k value interconnection in other zones.Wherein, the mode that the formation of high k value silica adopts PECVD deposition and nitrogenous gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (6)

1. the manufacture method of a metal-oxide silicon-metal capacitor is characterized in that, comprises the steps:
Substrate is provided;
The low K value dielectric layer of deposition on said substrate;
The mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and nitrogenous gas forms silica on said low K value dielectric layer;
Said silica is carried out photoetching and etching, remove the silica outside the MOM capacitor regions;
At the said low K value dielectric layer of body structure surface deposition of having removed partial oxidation silicon, and utilize cmp to remove the unnecessary low k value dielectric layer of silicon oxide surface top, form the mixed layer of low k value dielectric layer and silica;
Said low K value dielectric layer and said silica are carried out photoetching and etching, in said low K value dielectric layer and said silica, form interconnecting metal groove and electric capacity metallic channel respectively;
In said interconnecting metal groove and electric capacity metallic channel, fill metal.
2. the manufacture method of metal-oxide silicon-metal capacitor as claimed in claim 1 is characterized in that, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
3. the manufacture method of metal-oxide silicon-metal capacitor as claimed in claim 2; It is characterized in that; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between the 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
4. the manufacture method of metal-oxide silicon-metal capacitor as claimed in claim 1 is characterized in that said nitrogenous gas comprises nitric oxide, nitrous oxide or nitrogen.
5. the manufacture method of metal-oxide silicon-metal capacitor as claimed in claim 1; It is characterized in that; The nitrogenous gas flow that said nitrogenous gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
6. the manufacture method of metal-oxide silicon-metal capacitor as claimed in claim 1; It is characterized in that; Said mode through plasma reinforced chemical vapour deposition and nitrogenous gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
CN2012102930716A 2012-08-16 2012-08-16 Manufacturing method of metal-silicon oxide-metal capacitor Pending CN102779733A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10964779B2 (en) 2018-11-13 2021-03-30 International Business Machines Corporation Vertical plate capacitors exhibiting high capacitance manufactured with directed self-assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101079447A (en) * 2006-05-22 2007-11-28 台湾积体电路制造股份有限公司 Semiconductor element, IC and semiconductor element making method
CN102394216A (en) * 2011-11-30 2012-03-28 上海华力微电子有限公司 Metal-oxide-metal capacitor manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101079447A (en) * 2006-05-22 2007-11-28 台湾积体电路制造股份有限公司 Semiconductor element, IC and semiconductor element making method
CN102394216A (en) * 2011-11-30 2012-03-28 上海华力微电子有限公司 Metal-oxide-metal capacitor manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10964779B2 (en) 2018-11-13 2021-03-30 International Business Machines Corporation Vertical plate capacitors exhibiting high capacitance manufactured with directed self-assembly

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Application publication date: 20121114