CN102437023B - Method for manufacturing multilayer metal-oxide-metal capacitor - Google Patents
Method for manufacturing multilayer metal-oxide-metal capacitor Download PDFInfo
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- CN102437023B CN102437023B CN201110391743.2A CN201110391743A CN102437023B CN 102437023 B CN102437023 B CN 102437023B CN 201110391743 A CN201110391743 A CN 201110391743A CN 102437023 B CN102437023 B CN 102437023B
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Abstract
The invention provides a method for manufacturing a multilayer metal-oxide-metal (MOM) capacitor. The method comprises the following steps of: forming a mixed layer of a low-k-value medium and high-k-value silicon oxide; forming a metallic groove in the low-k-value medium by using photolithographic etching of the conventional process, and filling a metal into the metal groove; repeating the above steps; and thus, obtaining the multilayer metal-oxide-metal capacitor. An MOM capacitor structure is realized in a high-k-value silicon oxide area, and the interconnection of the low-k-value media is realized in another area; the high-k-value silicon oxide is formed in a mode of plasma enhanced chemical vapor deposition (PECVD) and oxygen-containing gas processing circulation; and silicon-hydrogen bonds in the silicon oxide can be effectively removed. Compared with the conventional single-k-value medium structure, the method can improve the capacitance of an in-layer capacitor effectively, and improve the electrical characteristics such as breakdown voltage, leakage current and the like of the MOM capacitor, and the electrical uniformity between devices.
Description
Technical field
The present invention relates to microelectronic, particularly relate to a kind of manufacture method of multilayer metal-oxide-metal capacitor.
Background technology
Capacitor is electronic devices and components conventional in integrated circuit, is also the important composition unit of integrated circuit, and it can be widely used in memory, microwave, and radio frequency, smart card, in the chips such as high pressure and filtering.At present, the capacitor widely adopting in chip is metal-insulator-metal type (MIM) capacitor that is parallel to silicon chip substrate.Wherein metal conventionally adopts and metal interconnected the technique copper, aluminium etc. of compatibility mutually, insulator mostly is dielectric substance silica or the silicon nitride of high-k (k), plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition being widely used in metal interconnected technique of its depositing temperature.The silica or the interior residual a large amount of si-h bond (Si-H) of silicon nitride film that utilize PECVD method to make, make to exist in it more electric charge, this causes this silica or the silicon nitride film uniformity aspect electrical thickness poor, and the MIM capacitor of utilizing this silica or silicon nitride film to make also can be corresponding poor aspect each electrical characteristics such as puncture voltage, leakage current.
In addition, along with improving constantly of very lagre scale integrated circuit (VLSIC) integrated level, the continuous scaled down of device feature size, the capacitor sizes of making in circuit is corresponding dwindling also, the uniformity that electric capacity is manufactured, coherence request is more strict.And along with the minimizing of device size, and the demand of performance to large electric capacity, how under limited area, obtaining highdensity electric capacity also becomes an attractive problem.
Publication number is that the Chinese patent of CN101577227A discloses a kind of method of improving aluminium-silicon nitride-tantalum compound capacitor performance, by oxygen-containing gas, process silicon nitride film, the quantity of electric charge in the silicon nitride film forming is less, the electrical thickness of silicon nitride film and the uniformity of physical thickness have been improved, adopt the MIM electric capacity of the method formation in puncture voltage, each electrical characteristics aspect such as leakage current makes moderate progress, but does not obtain highdensity electric capacity.Therefore, how under limited area, to obtain highdensity electric capacity and be still urgent problem in present technical development.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of formation method of multilayer metal-oxide-metal capacitor, to obtain highdensity electric capacity under limited area, and can effectively improve the electric capacity of layer inner capacitor, improve each electrical characteristics such as puncture voltage, leakage current of metal-oxide-metal (MOM) capacitor and the electricity uniformity between each device thereof.
For addressing the above problem, the invention provides a kind of manufacture method of multilayer metal-oxide-metal capacitor, comprise the following steps:
Step 4, at the low k value dielectric layer of said structure surface formation predetermined thickness;
Step 6 is filled metal in first, second metallic channel;
Repeating step 2～step 6.
Optionally, step 4 specifically comprises:
At the low k value of said structure surface deposition dielectric layer, and utilize cmp to remove the unnecessary low k value dielectric layer of silicon oxide surface top;
On said structure surface, again deposit low k value dielectric layer to predetermined thickness.
Optionally, step 4 specifically comprises:
At the low k value of said structure surface deposition dielectric layer, utilize cmp to carry out planarization to low k value dielectric layer surface, and above silica, retain the low k value dielectric layer of predetermined thickness.
Preferably, the reacting gas that described plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
Preferably, the flow of described silane is between 500sccm to 600sccm, the flow of described nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
Preferably, the oxygen-containing gas that described oxygen-containing gas processing adopts comprises nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.
Preferably, the oxygen-containing gas flow that described oxygen-containing gas processing adopts is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees Celsius to 600 degrees Celsius.
Preferably, the described mode of processing two steps circulations by plasma enhanced chemical vapor deposition and oxygen-containing gas forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
The present invention is by forming the mixed layer of low k value medium and high k value silica, then carry out the photoetching etching of traditional handicraft, in high k value region of silicon oxide, realize multilayer MOM structure, in other regions, realize low k value interconnection, wherein, the mode that the formation of high k silica adopts PECVD deposition and oxygen-containing gas cycle for the treatment of to carry out, can effectively remove the si-h bond in silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved again each electrical characteristics such as puncture voltage, leakage current of MOM capacitor, and the electricity uniformity between each device.By adopting vertical capacitor structure, can also effectively improve capacitor density, thereby realize larger electric capacity in less chip area.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that the embodiment of the present invention forms multilayer MOM electric capacity;
Fig. 2 A～2J is the method schematic diagram that the embodiment of the present invention forms multilayer MOM electric capacity.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
The present invention proposes the process of a kind of making multiple layer metal-oxide-metal (MOM) capacitor.Please refer to Fig. 1, for the present invention prepares the method flow diagram of multilayer MOM capacitor.
Step 201: substrate 1 is provided; The substrate 1 providing in the present embodiment can be simple silicon substrate, also can form for surface the silicon substrate of semiconductor device.
Step 202: as shown in Figure 2 A, deposit the oxide of high k value on substrate 1, preferably adopt silica 2 in the present invention.In order to improve silicon oxide film that conventional P ECVD method makes in the uniformity aspect electrical thickness, the mode that adopts PECVD method cvd silicon oxide and oxygen-containing gas cycle for the treatment of to carry out in the present invention, deposit after one deck silica, carry out subsequently oxygen-containing gas processing, and then cvd silicon oxide, carry out again oxygen-containing gas processing, so circulation; The silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer, till the silica 2 of deposition reaches the thickness needing in technique.
Wherein, the reacting gas that PECVD adopts is silane and nitrous oxide, the flow that the process conditions of reaction are silane is between 500sccm to 600sccm, the flow of nitrous oxide is between 9000sccm to 15000sccm, the flow-rate ratio of silane and nitrous oxide is between 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute; Oxygen-containing gas is processed the oxygen-containing gas adopting and is comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide, and the flow of oxygen-containing gas is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees Celsius.
And then silica by deposition skim also carries out oxygen-containing gas processing to it, can remove fully the si-h bond Si-H in silicon oxide film, and so circulation, can obtain the silica that electrical thickness evenness is good.
Step 203: as shown in Figure 2 B, remove a part of silica 2 on substrate 1 by photoetching and etching, the silica 2 retaining is for follow-up formation multilayer metal-oxide-metal capacitor.
Step 204: form the low k value dielectric layer 3 of predetermined thickness on said structure surface, described low k value dielectric layer 3 adopts chemical vapour deposition (CVD) or spin coating process to form, and dielectric constant is 2～3.The step that deposits low k value dielectric layer 3 can complete by two kinds of modes:
First kind of way: first deposit low k value dielectric layer at the body structure surface shown in Fig. 2 B, and take high k value silica 2 as grinding stop-layer, utilize cmp to remove the unnecessary low k value dielectric layer in silica 2 surfaces, form the mixed layer of low k value medium and silica; Then, on mixed layer, again deposit low k value dielectric layer to predetermined thickness, form the structure shown in Fig. 2 C;
The second way: deposit low k value dielectric layer at the body structure surface shown in Fig. 2 B, utilize cmp to carry out planarization to low k value dielectric layer surface, and retain the low k value dielectric layer 3 of predetermined thickness above silica 2, form the structure shown in Fig. 2 C.
Step 205: as shown in Figure 2 D, form respectively the first metallic channel 4a and the second metallic channel 4b in low k value dielectric layer 3, wherein, the first metallic channel 4a is positioned at silica 2 tops and is communicated to silica 2 surfaces, for the capacitor plate of follow-up formation multilayer MOM electric capacity.The first metallic channel 4a can evenly offer a plurality of, and the degree of depth of the first metallic channel 4a equals the thickness of silica 2 surface low k value dielectric layers, and the bottom-exposed of the first metallic channel 4a goes out silica 2.The second metallic channel 4b is for follow-up formation interconnection, and its degree of depth can be identical with the first metallic channel 4a, also can to the number of the second metallic channel 4b, size, the degree of depth, adjust according to actual process demand.
Step 206: as shown in Figure 2 E, fill metal 5 in metallic channel, carry out the processing steps such as diffusion impervious layer deposition, copper plating, copper metal layer cmp of the copper of copper wiring technique in first, second metallic channel, complete copper and fill.
Then, repeating step 202 to 206, specifically comprises: as shown in Figure 2 F, and the mode cvd silicon oxide 2 that adopts PECVD method and oxygen-containing gas cycle for the treatment of to carry out at the body structure surface shown in Fig. 2 E; As shown in Figure 2 G, remove a part of silica 2, the silica 2 of reservation is for follow-up formation multilayer MOM electric capacity; As shown in Fig. 2 H, low k value dielectric layer 3 at silica 2 surface deposition predetermined thickness, as shown in Fig. 2 I, in low k value dielectric layer 3, form respectively first, second metallic channel 6a, 6b, wherein the first metallic channel 6a is used for follow-up formation capacitor plate, and corresponding with the position of metallic channel 4a, and the second metallic channel 6b is used to form interconnection; As shown in Fig. 2 J, in metallic channel 6a, 6b, insert metal 5, thereby realize multilayer MOM capacitance structure in high k value region of silicon oxide, in other regions, realize low k value interconnection.
Certainly, also can be as required again or repeatedly repeating step 202 to 206 until reach the required MOM electric capacity number of plies.
The present invention, when utilizing schematic diagram that the embodiment of the present invention is described in detail in detail, for convenience of explanation, represents that the profile of device architecture is disobeyed local amplification of general ratio work, should not using this as limitation of the invention.In addition, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. a manufacture method for multilayer metal-oxide-metal capacitor, is characterized in that, comprises the following steps:
Step 1, provides substrate;
Step 2, the mode of processing two step circulations by plasma enhanced chemical vapor deposition and oxygen-containing gas forms silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer;
Step 3, removes a part of silica by photoetching and etching, and the silica retaining is for follow-up formation multilayer metal-oxide-metal capacitor;
Step 4 forms the low k value dielectric layer of predetermined thickness on the body structure surface being obtained by step 3;
Step 5, by photoetching be etched in low k value dielectric layer and form respectively the first metallic channel and the second metallic channel, wherein, the bottom that the first metallic channel is positioned at silica top and the first metallic channel is communicated to silica, and the second metallic channel is for follow-up formation interconnection;
Step 6 is filled metal in first, second metallic channel;
Repeating step 2～step 6.
2. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, described step 4 specifically comprises:
On the body structure surface being obtained by step 3, deposit low k value dielectric layer, and utilize cmp to remove the unnecessary low k value dielectric layer of silicon oxide surface top, and again deposit low k value dielectric layer to predetermined thickness.
3. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, described step 4 specifically comprises:
On the body structure surface being obtained by step 3, deposit low k value dielectric layer, utilize cmp to carry out planarization to low k value dielectric layer surface, and above silica, retain the low k value dielectric layer of predetermined thickness.
4. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, the reacting gas that described plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
5. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 4, it is characterized in that, the flow of described silane is between 500sccm to 600sccm, the flow of described nitrous oxide is between 9000sccm to 15000sccm, the flow-rate ratio of silane and nitrous oxide is 1:15 to 1:30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
6. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 1, is characterized in that, described oxygen-containing gas is processed the oxygen-containing gas adopting and comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.
7. the manufacture method of multilayer metal-oxide-metal capacitor as claimed in claim 1, it is characterized in that, the oxygen-containing gas flow that described oxygen-containing gas processing adopts is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees Celsius to 600 degrees Celsius.
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| CN102437023B true CN102437023B (en) | 2014-04-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102779736A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of metal-silicon oxide-metal capacitor |
| CN102779735A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of multi-layer metal-silicon oxide-metal capacitor |
| CN102779734A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor |
| CN102881564A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | MOM (metal oxide metal) capacitor manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004095582A1 (en) * | 2003-04-09 | 2004-11-04 | Newport Fab, Llc Dba Jazz Semiconductor | A high density mim capacitor with reduced voltage dependence in semiconductor dies |
| CN1734763A (en) * | 2004-08-13 | 2006-02-15 | 上海华虹Nec电子有限公司 | MIM capacitor on CMOS device and manufacturing method thereof |
| US7015110B2 (en) * | 2003-12-30 | 2006-03-21 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and structure of manufacturing high capacitance metal on insulator capacitors in copper |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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| US20030001188A1 (en) * | 2001-06-27 | 2003-01-02 | Nakagawa Osamu Samuel | High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004095582A1 (en) * | 2003-04-09 | 2004-11-04 | Newport Fab, Llc Dba Jazz Semiconductor | A high density mim capacitor with reduced voltage dependence in semiconductor dies |
| US7015110B2 (en) * | 2003-12-30 | 2006-03-21 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and structure of manufacturing high capacitance metal on insulator capacitors in copper |
| CN1734763A (en) * | 2004-08-13 | 2006-02-15 | 上海华虹Nec电子有限公司 | MIM capacitor on CMOS device and manufacturing method thereof |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
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